Acceleration unit, computing device, system on chip and message transmission acceleration method

Abstract

The embodiment of the invention provides an acceleration unit, a computing device, a system on chip and a message transmission acceleration method, and the acceleration unit comprises a receiving subunit which is used for receiving a network message through a network; the message writing subunit is used for determining a target memory buffer area from a plurality of memory buffer areas according to the state information of the memory buffer areas, and writing the network message into the target memory buffer area; and the queue writing subunit is used for writing the address information of the target memory buffer area into a completion queue after the network message is written into the target memory buffer area, so that a message receiving end on a host reads the network message from the target memory buffer area according to the completion queue. According to the scheme, the packet receiving efficiency of the network message can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to an acceleration unit, a computing device, a system on chip, and a message transmission acceleration method. Background Art

[0002] In the cloud computing scenario, the network needs to be virtualized. The host builds multiple virtual machines (VMs). After receiving the network message, the infrastructure processor (IPU) writes the network message into the memory buffer allocated by the virtual machine. Then the virtual machine can read the network message from the memory buffer and perform corresponding processing.

[0003] Currently, the host is divided into multiple memory buffers for receiving network messages. After receiving the network messages, the infrastructure processor writes the network messages into the multiple memory buffers in sequence.

[0004] However, the performance of the processor on the host in reading data from different memory buffers varies. Writing network packets to the memory buffers in sequence cannot fully utilize the memory buffers with higher read and write performance, resulting in low efficiency in receiving network packets. Summary of the invention

[0005] In view of this, embodiments of the present application provide a distribution unit, a computing device, a system on chip, and a message transmission acceleration method to at least solve or alleviate the above-mentioned problems.

[0006] According to the first aspect of an embodiment of the present application, an acceleration unit is provided, comprising: a receiving subunit, for receiving a network message through a network; a message writing subunit, for determining a target memory buffer from a plurality of memory buffers according to status information of the memory buffer, and writing the network message into the target memory buffer; a queue writing subunit, for writing the address information of the target memory buffer into a completion queue after the network message is written into the target memory buffer, so that a message receiving end on a host reads the network message from the target memory buffer according to the completion queue.

[0007] According to a second aspect of an embodiment of the present application, a computing device is provided, comprising: a processing unit for constructing a host, the host being used to allocate multiple memory buffers; and an acceleration unit according to the first aspect above.

[0008] According to a third aspect of an embodiment of the present application, a system on chip is provided, comprising an acceleration unit according to the first aspect above.

[0009] According to a fourth aspect of an embodiment of the present application, a server is provided, which is deployed in a data center and is provided with an acceleration unit as described in the first aspect above.

[0010] According to a fifth aspect of an embodiment of the present application, a data center is provided, comprising a server according to the fourth aspect above.

[0011] According to the sixth aspect of the embodiment of the present application, an Internet network is provided, comprising: a message receiving device and at least one message sending device; the message receiving device comprises an acceleration unit as described in the first aspect above; the message sending device is connected to the acceleration unit included in the message receiving device through a network, and the message sending device is used to send a message sent to a message receiving end on the message receiving device to the acceleration unit.

[0012] According to the seventh aspect of the embodiment of the present application, a method for accelerating message transmission is provided, including: receiving a network message through a network; determining a target memory buffer from multiple memory buffers based on status information of the memory buffer, and writing the network message into the target memory buffer; after the network message is written into the target memory buffer, writing the address information of the target memory buffer into a completion queue, so that a message receiving end on the host reads the network message from the target memory buffer according to the completion queue.

[0013] According to the solution provided by the embodiment of the present application, after the receiving subunit receives the network message, the message writing subunit can determine the target memory buffer according to the status information of the memory buffer, and then write the network message to the target memory buffer, so that the network message can be written into the memory buffer with relatively high read and write efficiency, and the queue writing subunit can write the address information of the target memory buffer into the completion queue, and then the message receiving end on the host can read the network message from the target memory buffer according to the address information in the completion queue. Since the message writing subunit can write the network message to the target memory buffer according to the status information of the memory buffer, by selecting a memory buffer with relatively high read and write performance as the target memory buffer, the packet receiving efficiency of writing the network message can be improved, thereby improving the efficiency of the CPU accessing the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0015] Figure 1 is a schematic diagram of a data center according to an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of a server according to an embodiment of the present application;

[0017] Figure 3 is a schematic diagram of an Internet network according to an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of an acceleration unit according to an embodiment of the present application;

[0019] Figure 5 It is a schematic diagram of a network message writing process of an embodiment of the present application;

[0020] Figure 6 is a schematic diagram of a network message writing process of another embodiment of the present application;

[0021] Figure 7 This is a flowchart of a method for accelerating message transmission according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0023] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0024] Infrastructure Processor: Infrastructure Processing Units (IPU) is a special processor designed for cloud data centers. It connects to physical computing, storage, and network resources, quickly cloudifies and performs hardware acceleration, and connects to the cloud operating system to manage and control the servers in the cloud data center. The infrastructure processor can solve the problem of data migration bandwidth and can also cloudify and virtualize the data center.

[0025] Host: A host is a cloud server, physical server, or virtual host that has a virtualized environment deployed. A host can create multiple virtual machines and provide software and hardware support for the operation of virtual machines. A host can also include a bare metal server, which is a hardware device with the characteristics of a traditional physical server and the virtualization function of cloud computing technology. It is a combination of hardware and software advantages.

[0026] Virtual Machine: A virtual machine (VM) is a complete computer system that is simulated by software and has complete hardware system functions and runs in an isolated environment.

[0027] Message receiving end: The message receiving end is the main body on the host that receives and processes network messages. The message receiving end can be a virtual machine or a bare metal server. After the network message is stored in the target memory buffer, the virtual network card can notify the message receiving end that the network message has been written to the target memory buffer by writing to the completion queue (CQ). Then, the message receiving end can read the network message from the target memory buffer.

[0028] Memory buffer: A memory buffer is a storage space of a specified size reserved in the memory for temporary storage of input / output (I / O) data. The memory buffer in the embodiment of the present application refers to a receive buffer (RXBuffer), and the target memory buffer determined from the receive buffer according to the status information is a storage space reserved in the memory for storing network messages.

[0029] System on a chip: System on a chip (SoC) refers to a technology that integrates a complete system on a single chip and groups all or part of the necessary electronic circuits. The so-called complete system generally includes a processor (CPU) or an acceleration unit, memory, and peripheral circuits. SoC is developed in parallel with other technologies, such as Silicon on Insulator (SOI), which can provide enhanced clock frequencies and thus reduce the power consumption of microchips.

[0030] Data Center

[0031] Data centers are a globally collaborative network of specific devices used to transmit, accelerate, display, calculate, and store data information on the Internet network infrastructure. In the future, data centers will also become competitive assets for enterprises. With the widespread application of data centers, virtualization technology is increasingly being applied to data centers. As an important support for virtualization technology, infrastructure processors have been widely used in input / output virtualization scenarios in data centers.

[0032] In traditional large data centers, the network structure is usually as follows Figure 1 As shown in the figure, it is the hierarchical inter-networking model. This model includes the following parts:

[0033] Server 140 : Each server 140 is a processing and storage entity of the data center. The processing and storage of a large amount of data in the data center are completed by these servers 140 .

[0034] Access switch 130: Access switch 130 is used to connect servers 140 to the switch in the data center. One access switch 130 connects to multiple servers 140. Access switches 130 are usually located at the top of the rack, so they are also called top of rack switches, and they are physically connected to the servers.

[0035] Aggregation switch 120: Each aggregation switch 120 connects to multiple access switches 130 and provides other services, such as firewall, intrusion detection, network analysis, etc.

[0036] Core switch 110: The core switch 110 provides high-speed forwarding for packets entering and leaving the data center, and provides connectivity for the aggregation switch 120. The network of the entire data center is divided into an L3 layer routing network and an L2 layer routing network. The core switch 110 usually provides a flexible L3 layer routing network for the network of the entire data center.

[0037] Generally, the aggregation switch 120 is the demarcation point between the L2 and L3 layer routing networks. The network below the aggregation switch 120 is the L2 network, and the network above is the L3 network. Each group of aggregation switches manages a delivery point (POD), and the POD is an independent VLAN network. The server does not need to modify the IP address and default gateway when migrating within the POD, because one POD corresponds to one L2 broadcast domain.

[0038] The spanning tree protocol (Spanning Tree Protocol, STP) is usually used between the aggregation switch 120 and the access switch 130. STP makes only one aggregation switch 120 available for a VLAN network, and other aggregation switches 120 are used only when a failure occurs. In other words, horizontal expansion cannot be achieved at the level of the aggregation switch 120, because even if multiple aggregation switches 120 are added, only one is still working.

[0039] The embodiments of the present application can be applied to input / output virtualization scenarios. A virtualization environment can be deployed on the server 140, and multiple virtual machines and / or bare metal servers can be created based on the virtualization environment. Network packets can be sent through the network between virtual machines, between virtual machines and bare metal servers, between bare metal servers, between virtual machines and clients, or between bare metal servers and clients.

[0040] server

[0041] The computing device in the embodiment of the present application may be a server 140 included in a data center. The server 140 is a real processing device in the data center. Figure 2The structural block diagram of the inside of a server 140 is shown. The server 140 includes a memory 210, a processing unit cluster 270 and an acceleration unit cluster 280 connected by a bus. The processing unit cluster 270 includes a plurality of processing units 220. The acceleration unit cluster 280 includes a plurality of acceleration units 230. The acceleration unit 230 is a special processor designed mainly for writing network packets into the most efficient memory buffer in the embodiment of the present application, and can be embodied as a graphics processing unit (GPU) specially designed for input / output virtualization, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a cloud infrastructure processor (Cloud Infrastructure Processing Units, CIPU), an infrastructure processor (IPU) or a data processing unit (DPU), etc.

[0042] The architecture design of the traditional processing unit makes the control unit and the storage unit occupy a large part of the space in the architecture, while the space occupied by the computing unit is insufficient. Therefore, it is very effective in terms of logic control, but not efficient enough in terms of large-scale parallel computing. Therefore, various special acceleration units have been developed to more effectively improve the processing speed of calculations for different functions and different fields. In an embodiment of the present application, the acceleration unit 230 is a hardware accelerator designed specifically for improving the efficiency of reading network messages at the message receiving end. After receiving the network message, the acceleration unit 230 can determine the target memory buffer from multiple memory buffers according to the status information of the memory buffer, and write the network message to the target memory buffer, so that the network message can be written into a memory buffer with relatively high read-write efficiency, improve the efficiency of writing network messages, and then improve the efficiency of CPU access to memory, which will be described in detail below.

[0043] The processing unit 220 is used to construct a host, and the host may include multiple message receiving ends, and the message receiving ends perform input / output through the acceleration unit 230. For example, the message receiving end receives network messages through the acceleration unit 230. The host can be constructed based on one or more processing units 220, and the message receiving end may include multiple virtual machines. Multiple virtual machines can be created based on one processing unit 220. Multiple virtual machines created in the same host can perform input / output through one or more acceleration units 230. Multiple virtual machines that perform input / output through one acceleration unit 230 can be created based on the same processing unit 220 or based on different processing units 220. In an embodiment of the present application, the host constructed by the processing unit 220 can allocate a memory buffer. After the acceleration unit 230 writes the network message into the target memory buffer, the message receiving end on the host can read the network message from the target memory buffer.

[0044] The embodiment of the present application mainly focuses on the structure and configuration of the acceleration unit 230 , and the structure and configuration of the acceleration unit 230 will be described in detail hereinafter.

[0045] Internet

[0046] Figure 3 is a schematic diagram of an Internet network according to an embodiment of the present application, such as Figure 3 As shown, the internetwork includes a message receiving device 301 and at least one message sending device 302 ( Figure 3 Two message sending devices 302 are shown, but those skilled in the art should understand that the Internet may also include other numbers of message sending devices 302). The message receiving device 301 includes an acceleration unit 230, and the message sending device 302 is connected to the acceleration unit 230 included in the message receiving device 301 through a network. The message sending device 302 can send the message sent to the message receiving end on the message receiving device 301 to the acceleration unit 230.

[0047] A virtualization environment is deployed on the message receiving device 301, and multiple virtual machines and / or bare metal servers are created based on the virtualization environment. The message sending device 302 can send messages to the virtual machines and / or bare metal servers on the message receiving device 301 through the network. The message sending device 302 sends the message to be sent to the virtual machine and / or bare metal server to the acceleration unit 230 through the network, and the acceleration unit 230 sends the received message to the corresponding virtual machine and / or bare metal server.

[0048] After receiving the message, the acceleration unit 230 writes the received message into the memory buffer on the message receiving device 301, and then the virtual machine and / or bare metal server on the message receiving device 301 reads the message from the memory buffer. In the related technology, the received message is written into the memory buffer in sequence according to the order in which the memory buffer is used. However, the virtual machine and / or bare metal server reads data from different memory buffers at different speeds and cannot fully utilize the memory buffer with higher read and write performance.

[0049] In an embodiment of the present application, after receiving a message, the acceleration unit 230 selects a target memory buffer with a higher read / write virtuality from multiple memory buffers according to the status information of the memory buffer, writes the received message into the target memory buffer, and then writes the address information of the target memory buffer into the completion queue. Then, the virtual machine and / or bare metal server on the message receiving device 301 can read the message from the memory buffer in sequence according to the completion queue. On the premise of ensuring that the message reading order is correct, the memory buffer with higher read / write performance can be fully utilized to improve the efficiency of the acceleration unit 230 in transmitting messages.

[0050] The embodiment of the present application mainly focuses on the structure and configuration of the acceleration unit 230 , and the structure and configuration of the acceleration unit 230 will be described in detail hereinafter.

[0051] Internal structure of the acceleration unit

[0052] Combine the following Figure 4 The internal structure diagram of the acceleration unit 230 shown in FIG. 2 specifically illustrates how the acceleration unit 230 works.

[0053] like Figure 4 As shown, the acceleration unit 230 includes a receiving subunit 231, a message writing subunit 232, and a queue writing subunit 233. The receiving subunit 231 can receive a network message through a network, and the message writing subunit 232 can determine a target memory buffer from multiple memory buffers according to the status information of the memory buffer, and write the network message received by the receiving subunit 231 into the target memory buffer. After the network message is written into the target memory buffer, the queue writing subunit 233 can write the address information of the target memory buffer into the completion queue, so that the message receiving end on the host can read the network message from the target memory buffer according to the completion queue.

[0054] One or more message receiving terminals are running on the host. After receiving a network message sent to a message receiving terminal, the acceleration unit 230 needs to write the network message into the memory buffer on the host, and then the corresponding message receiving terminal can read the network message from the memory buffer and perform corresponding processing according to the read network message. The host is pre-allocated with a receiving buffer (RX Buffer) for caching network messages. The receiving buffer includes multiple memory buffers, and the memory buffer is located in the main memory (also called memory, internal memory) of the host.

[0055] The message receiving end running on the host can be connected to multiple virtual network cards, which are virtualized by the acceleration unit 230. Before receiving packets in the virtual network, the network card driver of the message receiving end can allocate one or more queues for receiving packets to the virtual network card, and each queue includes multiple memory buffers. When the virtual network card receives a network message, it can write the received network message into the queue allocated to it, and then the message receiving end to which the virtual network card belongs can read the network message from the queue.

[0056] After the network card driver on the host allocates a memory buffer for the message receiving end, the host will store the address information of the memory buffer in the submission queue (Submission Queue, SQ), and send the submission queue to the acceleration unit 230. The submission queue includes multiple data, and the position of each data in the submission queue indicates the writing order of the corresponding memory buffer. The acceleration unit 230 can store network messages in the memory buffer allocated to the host based on the submission queue. After receiving the network message, the acceleration unit 230 will determine the target memory buffer according to the status information of the memory buffer, and then write the network message into the target memory buffer.

[0057] The target memory buffer may include one memory buffer or multiple memory buffers according to the data volume of the network message received by the receiving subunit 231. For example, when the data volume of the network message is small and the network message can be cached by one memory buffer, the target memory buffer includes one memory buffer, and when the data volume of the network message is large and the network message cannot be cached by one memory buffer, the target memory buffer includes two or more memory buffers.

[0058] After the receiving subunit 231 receives the network message, the message writing subunit 232 determines the target memory buffer according to the state information of the memory buffer, and writes the network message into the determined target memory buffer. After the message writing subunit 232 writes the network message into the target memory buffer, the queue writing subunit 233 can write the address information of the target memory buffer into the completion queue (CQ), and then the message receiving end can find the target memory buffer that caches the network message according to the address recorded in the address information in the completion queue, and read the data of the network message from the found target memory buffer.

[0059] After the message writing subunit 232 writes the network message into the target memory buffer, the queue writing subunit 233 writes the address information of the target memory buffer into the completion queue, ensuring that the network message is first written into the target memory buffer, and then the address information of the target memory buffer is written into the completion queue, thereby ensuring that the message receiving end reads the correct network message from the target memory buffer according to the completion queue. For example, after the message writing subunit 232 completes writing the network message data into a target memory buffer, the queue writing subunit 233 writes the address information of the target memory buffer into the completion queue.

[0060] In the embodiment of the present application, after the receiving subunit 231 receives the network message, the message writing subunit 232 can determine the target memory buffer according to the status information of the memory buffer, and then write the network message into the target memory buffer, so that the network message can be written into the memory buffer with relatively high read and write performance efficiency, and the queue writing subunit 233 can write the address information of the target memory buffer into the completion queue, and then the message receiving end on the host can read the network message from the target memory buffer according to the address information in the completion queue. Since the message writing subunit 232 can write the network message to the target memory buffer according to the status information of the memory buffer, by selecting the memory buffer with relatively high read and write efficiency as the target memory buffer, the packet receiving efficiency of writing the network message can be improved, and then the efficiency of the CPU accessing the memory can be improved.

[0061] In one possible implementation, the message writing subunit 232 can write the address information of the target memory buffer into the completion queue according to the order in which the message receiving end reads the completion queue, so that the message receiving end reads the network messages from the memory buffer according to the completion queue and the order in which the receiving subunit 231 receives the network messages.

[0062] The completion queue can store multiple data, each of which includes the address information of the memory buffer. The message receiving end reads the data stored in the completion queue in order, and reads the network message from the corresponding memory buffer according to the address information included in the read data. For example, data 1 and data 2 are two adjacent data in the completion queue, and data 1 is before data 2, then the message receiving end will first read data 1, and according to the address information 1 included in the read data 1, read the network message from the memory buffer corresponding to address information 1, and then read the data 2, and according to the address information 2 included in the read data 2, read the network message from the memory buffer corresponding to address information 2.

[0063] The message writing subunit 232 writes the network messages received by the receiving subunit 231 into the memory buffer in order, and the network messages received first are written into the memory buffer first, and the address information of the memory buffer of the network message written first is written into the first read position in the completion queue, so that the network messages written into the memory buffer first will be read by the message receiving end first, so the order in which the receiving subunit 231 receives the network messages is the same as the order in which the message receiving end reads the network messages. Therefore, changing the memory buffer for caching network messages will not change the order in which the receiving end reads the network messages, so the memory buffer can be used out of order, and the order in which the message receiving end reads the network messages is guaranteed to be consistent with the order in which the acceleration unit 230 receives the network messages, thereby ensuring the accuracy of the data read by the message receiving end.

[0064] In an embodiment of the present application, the queue writing subunit 232 writes the address information of the target memory buffer into the completion queue according to the order in which the message receiving end reads the completion queue, thereby ensuring that the order of network messages in the completion queue is consistent with the order of network messages received by the receiving subunit, thereby avoiding the problem of disordered network messages.

[0065] Figure 5 is a schematic diagram of the network message writing process in the related art. After the host allocates the memory buffer, the address information of the memory buffer is stored in the submission queue (SQ), such as Figure 5 As shown, the submission queue records the address information of memory buffer S0 to memory buffer S5, and the address information of memory buffer S0 to memory buffer S5 is Desc0 to Desc5 respectively. After the host sends the submission queue to the acceleration unit, the acceleration unit writes the network message into the memory buffer in the order from memory buffer 0 to memory buffer 5 according to the submission queue.

[0066] like Figure 5 As shown, the acceleration unit receives network message 0, network message 1, and network message 2 in sequence. After receiving network message 0, the acceleration unit writes network message 0 into the memory buffer S0, and writes the address information Desc0 of the memory buffer S0 into the completion queue (CQ). After receiving network message 1, the acceleration unit writes network message 1 into the memory buffer S1, and writes the address information Desc1 of the memory buffer S1 after the address information Desc0 in the completion queue. After receiving network message 2, the acceleration unit writes network message 2 into the memory buffer S2, and writes the address information Desc2 of the memory buffer S2 after the address information Desc1 in the completion queue.

[0067] From the above analysis, it can be seen that when writing data to multiple memory buffers in sequence, due to the different read and write efficiencies of different memory buffers, the memory buffer with lower read and write efficiency may be used first, while the memory buffer with higher read and write efficiency is idle, which leads to lower efficiency of writing network messages to the memory buffer.

[0068] Figure 6 It is a schematic diagram of a network message writing process according to an embodiment of the present application. Figure 6 The memory buffer shown is Figure 5 The memory buffers shown remain consistent and will not be described again here.

[0069] like Figure 6As shown, the acceleration unit 230 receives network message 0, network message 1 and network message 2 in sequence. After the acceleration unit 230 receives network message 0, the message writing subunit 232 determines the memory buffer S0 as the target memory buffer of the network message 0 according to the status information of the memory buffer. After the message writing subunit 232 writes the network message 0 into the memory buffer S0, the queue writing subunit 233 writes the address information Desc0 of the memory buffer S0 into the completion queue. After the acceleration unit 230 receives network message 1, the message writing subunit 232 determines the memory buffer S2 as the target memory buffer of the network message 1 according to the status information of the memory buffer. After the message writing subunit 232 writes the network message 1 into the memory buffer S2, the queue writing subunit 233 writes the address information Desc2 of the memory buffer S2 after the address information Desc0 in the completion queue. After the acceleration unit 230 receives the network message 2, the message writing subunit 232 determines the memory buffer S1 as the target memory buffer for the network message 2 based on the status information of the memory buffer. After the message writing subunit 232 writes the network message 2 into the memory buffer S1, the queue writing subunit 233 writes the address information Desc1 of the memory buffer S1 after completing the address information Desc2 in the queue.

[0070] When the message receiving end on the host reads the network message according to the completion queue, it reads Desc0, Desc2, and Desc1 in the completion queue in sequence. After the message receiving end reads Desc0, it reads network message 0 from the memory buffer S0 according to Desc0. After reading network message 0, the message receiving end reads Desc2 from the completion queue in sequence, and reads network message 1 from the memory buffer S2 according to Desc2. After reading network message 1, the message receiving end reads Desc1 from the completion queue in sequence, and reads network message 2 from the memory buffer S1 according to Desc1.

[0071] From the above analysis, it can be seen that when writing network messages into the target memory buffer determined according to the status information, the target memory buffer has a relatively high read and write efficiency, thereby improving the packet receiving efficiency of writing network messages, and further improving the efficiency of CPU accessing memory.

[0072] It should be noted that the above Figure 6 The network message writing process shown is only an example of an embodiment of the present application. The order in which the message writing subunit 232 writes the network message into the memory buffer may be the same as the order of the memory buffer indicated by the submission queue, or may be different from the order of the memory buffer indicated by the submission queue. This embodiment of the present application does not limit this.

[0073] In one possible implementation, the message writing subunit 232 can determine a first memory buffer for caching a first network message from multiple memory buffers based on status information of the memory buffers, and determine a second memory buffer for caching a second network message from multiple memory buffers. The first network message is received by the receiving subunit 231 before the second network message, and the address information of the first memory buffer is located after the address information of the second memory buffer in the submission queue.

[0074] In the process of storing network messages, the message writing subunit 232 can first judge the status information of each memory buffer after receiving the network message, and determine the memory buffer corresponding to the received network message according to the status information. For example, for the first network message and the second network message received sequentially, after receiving the first network message, the first memory buffer for caching is determined according to the status information, and the second memory buffer for caching the second network message is determined in the same way. However, the address information of the first memory buffer can be located after the address information of the second memory buffer, that is, the memory buffer can be used out of order to cache the network message, and the order in which the acceleration unit 230 uses the memory buffer can be different from the order of the memory buffer indicated by the submission queue.

[0075] In an embodiment of the present application, after receiving a network message, the target memory buffer for caching the network message is determined through status information, and then the network message is written into the target memory buffer, so that the order of use of the memory buffer is no longer limited to the order defined by the submission queue, so that the memory buffer with higher read and write efficiency can be used preferentially to cache the network message, thereby improving the read and write efficiency of the message.

[0076] In a possible implementation, the state information used to determine the target memory buffer may include at least one of frequency information, cache information, and location information. The frequency information is used to indicate the usage frequency of the memory buffer, the cache information is used to indicate whether the data in the memory buffer is read into the cache memory, and the location information is used to indicate the message receiving end to which the memory buffer belongs.

[0077] The state information may include at least one of frequency information, cache information, and location information. For example, the state information may include frequency information and cache information, or the state information may include only location information. When the state information includes two or more of frequency information, cache information, and location information, the acceleration unit 230 determines the target memory buffer in combination with the various information included in the state information. For example, if the state information includes frequency information and cache information, the acceleration unit 230 determines the memory buffer with the highest usage frequency and the cached data read into the cache memory as the target memory buffer.

[0078] In an embodiment of the present application, by determining the target memory buffer through at least one of the frequency information, cache information and location information, a relatively efficient memory buffer can be determined according to the actual application scenario, thereby improving the efficiency of writing network packets and further improving the efficiency of CPU accessing memory.

[0079] In one possible implementation, the message writing subunit 232 may determine a target memory buffer from multiple memory buffers based on frequency information included in the status information, and there is at least one memory buffer among the multiple memory buffers whose usage frequency is less than the usage frequency of the target memory buffer.

[0080] The usage frequency of a memory buffer is positively correlated with the CPU's read and write efficiency of the memory buffer. Relatively speaking, the higher the usage frequency of a memory buffer, the higher the CPU's read and write efficiency of the memory buffer. The frequency of a memory buffer can be the frequency or number of times the CPU reads and writes the memory buffer. Therefore, based on the frequency information of the memory buffer, a memory buffer with a higher usage frequency can be determined as a target memory buffer.

[0081] When determining the target memory buffer according to the frequency information, the memory buffer with the highest usage frequency among the available memory buffers may be determined as the target memory buffer.

[0082] In an embodiment of the present application, by determining a memory buffer with a higher usage frequency as a target memory buffer, the efficiency of writing network messages can be improved, thereby improving the efficiency of CPU accessing memory.

[0083] In a possible implementation, the message writing subunit 232 may determine, according to the cache information included in the state information, a memory buffer in which data stored in the plurality of memory buffers is read into the cache memory as a target memory buffer.

[0084] It takes hundreds of clock cycles for the CPU to read data from the main memory, and the CPU will be stuck most of the time waiting for data. However, it only takes 2-50 clock cycles for the CPU to read data from the cache memory, so the CPU can read the required data in a shorter time through the cache memory.

[0085] For the memory buffer whose data has been read into the cache memory, there is a high probability that the data cached in the memory buffer will be pre-synchronized to the cache memory, and then when the message receiving end reads the memory buffer, it can read the network message cached in the memory buffer from the cache memory, so as to improve the efficiency of the message receiving end in reading the network message.

[0086] When the state information includes cache information, the memory buffer in which the stored data has been read into the cache memory has a higher access speed for the CPU than the memory buffer in which the stored data has not been read into the cache memory. Therefore, the memory buffer in which the stored data has been read into the cache memory among the multiple memory buffers is determined as the target memory buffer.

[0087] In an embodiment of the present application, the message writing subunit 232 determines the memory buffer in which the stored data is read into the cache memory as the target memory buffer based on the status information, so that the network messages stored in the target memory buffer are likely to be pre-read into the cache memory. When the message receiving end needs to read the network messages in the target memory buffer, the network messages cached in the target memory buffer can be read from the cache memory, thereby improving the efficiency of the message receiving end in reading the network messages.

[0088] In one possible implementation, the message writing subunit 232 can determine the target message receiving end of the network message, and based on the location information included in the status information, determine a memory buffer among multiple memory buffers that is located on the same host as the target message receiving end as the target memory buffer, and the target message receiving end is the message receiving end that reads the network message from the target memory buffer.

[0089] The message receiving end and the memory can be located on the same or different hosts. Due to the influence of the communication distance, the message receiving end reads data from the memory located on the same host as it, which is faster than reading data from the memory located on a different host. Therefore, when determining the target memory buffer, the target message receiving end of the network message can be used as the target memory buffer. The target message receiving end is the receiver of the network message.

[0090] In one example, a non-uniform memory access (NUMA) architecture includes multiple nodes, each node may have multiple CPUs (each CPU may have multiple cores or threads), and the memory of a node is the same for the CPU of the node, but different for the CPUs in other nodes. Nodes are divided into local nodes, neighboring nodes, and remote nodes. The speed at which the CPU accesses the memory of different types of nodes is different. The speed of accessing the memory of a local node is faster than the speed of accessing the memory of a neighboring node, and the speed of accessing the memory of a neighboring node is faster than the speed of accessing the memory of a remote node.

[0091] After determining the target message receiving end of the network message, the message writing subunit 232 determines the target node where the target message receiving end is located, and then determines the target memory buffer in the memory buffer of the target node based on the location information included in the status information, and then writes the network message into the target memory buffer, so that the message receiving end reads the network message from the local node memory, thereby improving the speed at which the message receiving end reads the network message.

[0092] In an embodiment of the present application, when the status information includes location information, the message writing subunit 232 determines the target memory buffer as the recipient of the network message based on the location information, and then determines a memory buffer located on the same host as the target memory buffer from multiple available memory buffers as the target memory buffer, so that when the message receiving end reads the network message from the target memory buffer, the communication distance of the message receiving end in the process of reading the network message is shortened, thereby improving the efficiency of the message receiving end in reading the network message.

[0093] System on Chip

[0094] An embodiment of the present application further provides a system on chip, which includes the acceleration unit 230 in any of the above embodiments.

[0095] It should be noted that the application of the acceleration unit 230 in the embodiment of the present application is not limited to the system on chip, but can also be applied in various other suitable ways. For example, the acceleration unit 230 and the processing unit (CPU), main memory and other interactive components are deployed on a printed circuit board, and the acceleration unit 230 interacts with the processing unit (CPU), main memory, etc. through a bus on the printed circuit board.

[0096] Message transmission acceleration method

[0097] The acceleration unit 230 in the aforementioned embodiment can be applied to a network virtualization scenario to realize the transmission of network packets to the packet receiving end. The acceleration unit 230 writes the received network packets into a target memory buffer determined according to the status information of the receiving buffer. The following is an example of a packet transmission acceleration method to illustrate the working process of the acceleration unit 230 in a network virtualization scenario.

[0098] Figure 7 FIG. 1 is a flow chart of a method for accelerating message transmission according to an embodiment of the present application. Figure 7 As shown, the message transmission acceleration method includes the following steps:

[0099] Step 601: receiving a network message through a network;

[0100] Step 602: determine a target memory buffer from multiple memory buffers according to the state information of the memory buffer, and write the network message into the target memory buffer;

[0101] Step 603: After the network message is written into the target memory buffer, the address information of the target memory buffer is written into the completion queue, so that the message receiving end on the host reads the network message from the target memory buffer according to the completion queue.

[0102] In an embodiment of the present application, after receiving a network message, the target memory buffer can be determined according to the status information of the memory buffer, and then the network message can be written into the target memory buffer, so that the network message can be written into a memory buffer with relatively high read and write performance efficiency, and the address information of the target memory buffer can be written into the completion queue, and then the message receiving end on the host can read the network message from the target memory buffer according to the address information in the completion queue. Since the network message can be written into the target memory buffer according to the status information of the memory buffer, by selecting a memory buffer with relatively high read and write efficiency as the target memory buffer, the packet receiving efficiency of writing the network message can be improved, thereby improving the efficiency of the CPU accessing the memory.

[0103] It should be noted that the message transmission acceleration method of the embodiment of the present application is a specific application of the acceleration unit 230 in the aforementioned embodiment in the network virtualization scenario. The specific message transmission acceleration method can be found in the description in the aforementioned acceleration unit embodiment, which will not be repeated here.

[0104] The commercial value of the present application embodiment

[0105] In an embodiment of the present application, the acceleration unit determines a target memory buffer from multiple memory buffers according to the state information of the memory buffer, and writes the network message into the target memory buffer, so that the order of using the memory buffer may not be the order of writing the network message, but the target memory buffer with relatively high writing efficiency, thereby improving the efficiency of writing the network message, thereby improving the efficiency of the CPU accessing the memory, and improving the performance of the host. This solution can be applied to network virtualization scenarios, such as data centers, and has good market prospects.

[0106] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0107] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0108] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0109] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0110] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. An acceleration unit, comprising: A receiving subunit, used for receiving network messages through the network; A message writing subunit, used for determining a target memory buffer from a plurality of memory buffers according to the state information of the memory buffer, and writing the network message into the target memory buffer; The queue writing subunit is used to write the address information of the target memory buffer into the completion queue after the network message is written into the target memory buffer, so that the message receiving end on the host reads the network message from the target memory buffer according to the completion queue.

2. The acceleration unit according to claim 1, wherein: The queue writing subunit is used to write the address information of the target memory buffer into the completion queue according to the order in which the message receiving end reads the completion queue, so that the message receiving end reads the network message from the memory buffer according to the completion queue and the order in which the receiving subunit receives the network message.

3. The acceleration unit according to claim 1, wherein: The message writing subunit is used to determine a first memory buffer for caching a first network message from multiple memory buffers according to status information of the memory buffer, and to determine a second memory buffer for caching a second network message from multiple memory buffers, the first network message is received by the receiving subunit before the second network message, and the address information of the first memory buffer is located after the address information of the second memory buffer in the submission queue.

4. The acceleration unit according to claim 1, wherein: The status information includes at least one of frequency information, cache information and location information, the frequency information is used to indicate the usage frequency of the memory buffer, the cache information is used to indicate whether the data in the memory buffer is read into the cache memory, and the location information is used to indicate the message receiving end to which the memory buffer belongs.

5. The acceleration unit according to claim 4, wherein: The message writing subunit is used to determine a target memory buffer from the multiple memory buffers according to the frequency information included in the status information, and there is at least one memory buffer among the multiple memory buffers whose usage frequency is less than the usage frequency of the target memory buffer.

6. The acceleration unit according to claim 4, wherein: The message writing subunit is used to determine the memory buffer in which the data stored in the multiple memory buffers is read into the cache memory as the target memory buffer according to the cache information included in the status information.

7. The acceleration unit according to claim 4, wherein: The message writing subunit is used to determine the target message receiving end of the network message, and according to the location information included in the status information, determine the memory buffer in the multiple memory buffers that is located on the same host as the target message receiving end as the target memory buffer, and the target message receiving end is the message receiving end that reads the network message from the target memory buffer.

8. A computing device, comprising: A processing unit for constructing a host, wherein the host is used to allocate a plurality of memory buffers; An acceleration unit according to any one of claims 1 to 7.

9. A system on chip, comprising: An acceleration unit according to any one of claims 1 to 7.

10. A server deployed in a data center, provided with an acceleration unit as claimed in any one of claims 1 to 7.

11. A data center, comprising: The server according to claim 10.

12. An Internet network comprising: A message receiving device and at least one message sending device; The message receiving device comprises an acceleration unit as described in any one of claims 1 to 7; The message sending device is connected to the acceleration unit included in the message receiving device through a network, and the message sending device is used to send the message sent to the message receiving end on the message receiving device to the acceleration unit.

13. A method for accelerating message transmission, comprising: Receiving network messages through the network; Determine a target memory buffer from multiple memory buffers according to the state information of the memory buffer, and write the network message into the target memory buffer; After the network message is written into the target memory buffer, the address information of the target memory buffer is written into the completion queue, so that the message receiving end on the host reads the network message from the target memory buffer according to the completion queue.

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