Inter-chip interconnection circuit and system

Abstract

The invention provides an inter-chip interconnection circuit and system.The inter-chip interconnection circuit comprises a CCIX protocol layer message exchange and forwarding module, a far-end agent module, a local agent module and a self-defined message exchange and forwarding module, and the local agent module comprises a message caching module, a scheduling module, a storage module, a protocol processing module and a processing result output module; wherein the CCIX protocol layer message exchange and forwarding module is in communication connection with the message caching module, the remote agent module and the processing result output module; the far-end agent module is also in communication connection with the self-defined message exchange and forwarding module; the user-defined message exchange and forwarding module is also in communication connection with the message caching module and the processing result output module; the message caching module is also in communication connection with the scheduling module and the storage module; the scheduling module is also in communication connection with the protocol processing module and the storage module; and the protocol processing module is also in communication connection with the processing result output module and the storage module. The inter-chip interconnection circuit and system provided by the invention can be used for interconnection of various types of processor chips, the universality of the inter-chip interconnection circuit is improved, and the transmission delay is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware, and in particular to an inter-chip interconnection circuit and system. Background Art

[0002] With the advent of the big data era, many fields such as high-performance computing and intelligent multimedia have put forward higher requirements on the performance of computer systems. To meet performance requirements, computer systems have gradually developed from single-core to multi-core, and from multi-core to multi-chip. The transmission efficiency of the inter-chip interconnection interface has also become increasingly prominent in affecting system performance.

[0003] There's a CPU interconnect technology called QuickPath Interconnect (QPI). Officially known as CSI, it stands for Common System Interface and is used to directly connect chips. However, QPI is a bus used by Intel CPUs to communicate with each other, not a general-purpose bus, and therefore lacks universal compatibility. Summary of the Invention

[0004] The present invention provides an inter-chip interconnection circuit and system, which are used to solve the defect of the prior art that there is a lack of a universal inter-chip interconnection circuit, and to provide a universal inter-chip interconnection circuit.

[0005] The present invention provides an inter-chip interconnection circuit, comprising: a CCIX protocol layer message switching and forwarding module, a remote proxy module, a local proxy module, and a custom message switching and forwarding module. The local proxy module comprises a message buffer module, a scheduling module, a storage module, a protocol processing module, and a processing result output module. The CCIX protocol layer message switching and forwarding module is communicatively connected to the message buffer module, the remote proxy module, and the processing result output module; the remote proxy module is also communicatively connected to the custom message switching and forwarding module; the custom message switching and forwarding module is also communicatively connected to the message buffer module and the processing result output module; the message buffer module is also communicatively connected to the scheduling module and the storage module; the scheduling module is also communicatively connected to the protocol processing module and the storage module; and the protocol processing module is also communicatively connected to the processing result output module and the storage module.

[0006] According to an inter-chip interconnection circuit provided by the present invention, the cache processing module is used to implement an input path for messages and data within the local agent module pipeline; the storage module is used to store and update directory information, wherein the directory information includes message addresses and cache status; the scheduling module is used to implement message scheduling processing; the protocol processing module is used to implement protocol processing of each message based on the CCIX protocol, and the processing result output module is used to output the protocol processing result.

[0007] According to an inter-chip interconnection circuit provided by the present invention, the cache processing module is further used to send the message and data together with the assigned data_id and dc_id to the scheduling module; wherein the data_id is used to identify the storage location of the data, and the dc_id is used to identify the storage address of the message in the directory information.

[0008] According to an inter-chip interconnection circuit provided by the present invention, when applied to inter-chip interconnection, the CCIX protocol layer message switching and forwarding module is also communicatively connected to a local processor chip, and the custom message switching and forwarding module is also communicatively connected to the custom message switching and forwarding modules of other inter-chip interconnection circuits connected to a remote processor chip.

[0009] According to an inter-chip interconnection circuit provided by the present invention, messages received by the message cache module include rqt0 channel messages and rqt2 channel messages sent by the custom message switching and forwarding module; wherein the rqt0 channel information includes a read request and a no-data request from a remote processor; the rqt2 channel message includes a snoop response from a local processor chip and a write-back request from a remote processor; and the messages received by the message cache module also include a request response and a snoop request sent by the CCIX protocol layer message switching and forwarding module from a local processor chip.

[0010] According to an inter-chip interconnection circuit provided by the present invention, the protocol processing module is further used to store request-related information into a first table item and store monitoring-related information into a second table item; wherein: the storage content of the first table item includes the validity information of the first table item, the hit information of the directory information, the request type code, the request source ID, the transaction ID in the request message, the newly generated transaction ID sent to the local processor chip, the request message address, and the request destination ID obtained according to the address in the request message; the storage content of the second table item includes the validity information of the second table item, the hit information of the directory information, the monitoring type code, the monitoring address, and the number of monitoring responses not returned. The number of inter-chip interconnect circuits, the request destination ID in the snoop message when initiating snooping on other inter-chip interconnect circuits, the transaction ID in the snoop message when initiating snooping on other inter-chip interconnect circuits, the cache attributes in the returned snoop response message, the data validity indication signal returned in the snoop response, the ID number assigned to the data in the returned snoop response, whether the snoop indication information initiated by the local CPU has been received when all snoop responses are returned, the indication information of whether to re-initiate snooping based on the protocol table, the initiator ID of the snoop message, the transaction ID of the snoop message received from the local processor chip, and the indication information of the CCIX protocol layer message switching and forwarding module received in the snoop response message.

[0011] According to an inter-chip interconnect circuit provided by the present invention, the protocol processing module, when used to implement protocol processing of each message based on the CCIX protocol, is specifically used to: generate a new transaction ID, request source ID, and request destination ID for the read request, the no-data request, and / or the write-back request, and output the request to the local processor chip; determine whether to initiate monitoring based on the received directory information, generate a monitoring request, and send it to the remaining inter-chip interconnect circuits, and record the first table entry and the second table entry; for the request response, modify the transaction ID, request source ID, and request destination ID in the received request response based on the recorded information in the first table entry, and send the newly generated request response to the local processor chip; To other inter-chip interconnect circuits, determine whether a confirmation message needs to be sent based on the request type stored in the first table entry. If so, send the confirmation message; if not, clear the first table entry; for the snoop request, update the content of the second table entry based on the second table entry and the received snoop information, and regenerate a snoop request and send it to the other inter-chip interconnect circuits or generate a snoop response and send it to the local processor chip according to the CCIX protocol; for the snoop response, update or clear the content of the second table entry based on the second table entry and the received snoop response information, and regenerate a snoop request and send it to the other inter-chip interconnect circuits or generate a snoop response and send it to the local processor chip according to the CCIX protocol.

[0012] The present invention also provides an inter-chip interconnect system. The system is based on the inter-chip interconnect chip provided in the above embodiment and includes at least one pair of interconnect structures. The interconnect structure includes a first processor chip, a first inter-chip interconnect circuit, a second inter-chip interconnect circuit, and a second processor chip. The first inter-chip interconnect circuit includes a first CCIX protocol layer message switching and forwarding module, a first remote agent module, a first local agent module, and a first custom message switching and forwarding module. The first local agent module includes a first message buffer module, a first scheduling module, a first storage module, a first protocol processing module, and a first processing result output module. The second inter-chip interconnect circuit includes a second CCIX protocol layer message switching and forwarding module, a second remote agent module, a second local agent module, and a second custom message switching and forwarding module. The second local agent module includes a second message buffer module, a second scheduling module, a second storage module, a second protocol processing module, and a second processing result output module. The first processor chip is connected to the first CCIX protocol layer message switching and forwarding module, the first custom message switching and forwarding module is connected to the second custom message switching and forwarding module, and the second processor chip is connected to the second CCIX protocol layer message switching and forwarding module.

[0013] According to an inter-chip interconnection system provided by the present invention, for a read request, no data request, write-back request, and / or snoop response sent by a first processor chip to a second processor chip, the transmission link is, in order: the first processor chip, the first custom message switching and forwarding module, the first remote proxy module, the first CCIX protocol layer message switching and forwarding module, the second CCIX protocol layer message switching and forwarding module, the second message buffer module, the second scheduling module, the second protocol processing module, the second processing result output module, the second custom message switching and forwarding module, and the second processor chip. For a read request, no data request, write-back request, or snoop response sent by the second processor chip to the first processor chip, the transmission link is, in order: the second processor chip, the second custom message switching and forwarding module, the second remote proxy module, the second CCIX protocol layer message switching and forwarding module, the first CCIX protocol layer message switching and forwarding module, the first message buffer module, the first scheduling module, the first protocol processing module, the first processing result output module, the first custom message switching and forwarding module, and the first processor chip.

[0014] According to an inter-chip interconnection system provided by the present invention, for a request response and / or a snoop request sent by the first processor chip to the second processor chip, the transmission link is, in order, the first processor chip, the first custom message switching and forwarding module, the first message buffer module, the first scheduling module, the first protocol processing module, the first processing result output module, the first custom message switching and forwarding module, the second custom message switching and forwarding module, the second remote proxy module, the second CCIX protocol layer message switching and forwarding module, and the second processor chip. For a request response and / or a snoop request sent by the second processor chip to the first processor chip, the transmission link is, in order, the second processor chip, the second custom message switching and forwarding module, the second message buffer module, the second scheduling module, the second protocol processing module, the second processing result output module, the second custom message switching and forwarding module, the first custom message switching and forwarding module, the first remote proxy module, the first CCIX protocol layer message switching and forwarding module, and the first processor chip.

[0015] The inter-chip interconnection circuit and system provided by the present invention include a CCIX protocol layer message switching and forwarding module, a remote proxy module, a local proxy module, and a custom message switching and forwarding module. The local proxy module includes a message cache module, a scheduling module, a storage module, a protocol processing module, and a processing result output module. The CCIX protocol layer message switching and forwarding module is communicatively connected to the message cache module, the remote proxy module, and the processing result output module. The remote proxy module is also communicatively connected to the custom message switching and forwarding module. The custom message switching and forwarding module is also communicatively connected to the message cache module and the processing result output module. The message cache module is also communicatively connected to the scheduling module and the storage module. The scheduling module is also communicatively connected to the protocol processing module and the storage module. The protocol processing module is also communicatively connected to the processing result output module and the storage module. Based on the CCIX protocol, an inter-chip interconnection circuit is implemented, which can be used to interconnect various types of processor chips, thereby improving the versatility of the inter-chip interconnection circuit and effectively reducing transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a structural schematic diagram of the inter-chip interconnection circuit provided by the present invention.

[0018] Figure 2 This is a schematic diagram of communication between the message cache module, the storage module and the scheduling module in the inter-chip interconnection circuit provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the protocol pipeline processing clock information of the inter-chip interconnection circuit provided by the present invention.

[0020] Figure 4 It is a structural diagram of the inter-chip interconnection system provided by the present invention. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0022] The CCIX standard enables processor, accelerator, and other peripheral device manufacturers to simplify the architectural design of heterogeneous systems, establish seamless inter-chip transmission, and achieve higher bandwidth, lower latency, and lower power consumption. However, due to its high technical complexity, few institutions or companies in China have implemented inter-chip interconnection using the CCIX protocol. On the other hand, the CCIX consistency protocol is vendor-independent, allowing CPUs, GPUs, and other accelerators to participate equally without licensing restrictions. Therefore, the present invention implements a design for inter-chip interconnect circuitry based on the CCIX standard.

[0023] Figure 1 FIG. 1 is a schematic diagram of the structure of the inter-chip interconnection circuit provided by the present invention. Figure 1 As shown, the inter-chip interconnection circuit includes: a CCIX protocol layer message switching and forwarding module 1, a remote proxy module 2, a local proxy module 3, and a custom message switching and forwarding module 4. The local proxy module 3 includes a message buffer module 301, a scheduling module 302, a storage module 303, a protocol processing module 304, and a processing result output module 305. The CCIX protocol layer message switching and forwarding module 1 is communicatively connected to the message buffer module 301, the remote proxy module 2, and the processing result output module 305; the remote proxy Module 2 is also communicatively connected to the custom message switching and forwarding module 4; the custom message switching and forwarding module 4 is also communicatively connected to the message cache module 301 and the processing result output module 305; the message cache module 301 is also communicatively connected to the scheduling module 302 and the storage module 303; the scheduling module 302 is also communicatively connected to the protocol processing module 304 and the storage module 303; the protocol processing module 304 is also communicatively connected to the processing result output module 305 and the storage module 303.

[0024] The inter-chip interconnection circuit includes not only the CCIX protocol layer message switching and forwarding module 1, the remote agent module 2, the local agent module 3 and the custom message switching and forwarding module 4, but also the link layer and physical layer modules. Figure 1 Not shown. Remote agent module 2 and local agent module 3 are closely related to the protocol, with local agent module 3 performing master agent functions. Local agent module 3 processes messages based on the CCIX protocol. In the inter-chip interconnect circuit, CCIX protocol layer message switching and forwarding module 1 and custom message switching and forwarding module 4 are used to connect to external modules. CCIX protocol layer message switching and forwarding module 1 is used to connect to the local processor chip, while custom message switching and forwarding module 4 is used to connect to the remote processor chip via another inter-chip interconnect circuit. The processor chip can be a CPU.

[0025] Each module of the inter-chip interconnect circuit can be converted into a hardware circuit by writing Verilog (a hardware description language) code. This inter-chip interconnect circuit can be manufactured into a chip.

[0026] The inter-chip interconnection circuit provided by the present invention includes a CCIX protocol layer message switching and forwarding module, a remote proxy module, a local proxy module, and a custom message switching and forwarding module. The local proxy module includes a message cache module, a scheduling module, a storage module, a protocol processing module, and a processing result output module. The CCIX protocol layer message switching and forwarding module is communicatively connected to the message cache module, the remote proxy module, and the processing result output module. The remote proxy module is also communicatively connected to the custom message switching and forwarding module. The custom message switching and forwarding module is also communicatively connected to the message cache module and the processing result output module. The message cache module is also communicatively connected to the scheduling module and the storage module. The scheduling module is also communicatively connected to the protocol processing module and the storage module. The protocol processing module is also communicatively connected to the processing result output module and the storage module. Based on the CCIX protocol, an inter-chip interconnection circuit is implemented, which can be used to interconnect various types of processor chips, thereby improving the versatility of the inter-chip interconnection circuit and effectively reducing transmission delay.

[0027] According to an inter-chip interconnection circuit provided by the present invention, the cache processing module 301 is used to implement the input path of messages and data within the pipeline of the local agent module 3; the storage module 303 is used to store and update directory information, and the directory information includes message addresses and cache status; the scheduling module 302 is used to implement message scheduling processing; the protocol processing module 304 is used to implement protocol processing of each message based on the CCIX protocol, and the processing result output module 305 is used to output the protocol processing results.

[0028] Storage module 303 primarily implements the input path for messages and data within the local proxy module 3 pipeline. Protocol processing module 304 primarily performs protocol processing on individual messages, while processing result output module 305 primarily implements the output path for messages and data. Storage module 303 is primarily used to store and update directory information (message addresses and cache status) so that directory information can be queried when requests or snoops arrive. It also modifies directory information based on protocol processing results to meet cache coherency requirements.

[0029] The inter-chip interconnection circuit provided by the present invention realizes the reasonable division of labor and collaboration of various modules in the local processing module.

[0030] According to an inter-chip interconnection circuit provided by the present invention, the cache processing module 301 is also used to send the message and data together with the assigned data_id and dc_id to the scheduling module; wherein the data_id is used to identify the storage location of the data, and the dc_id is used to identify the storage address of the message in the directory information.

[0031] After receiving the message and data, the cache processing module 301 is further used to send the message and data together with the allocated data_id and dc_id to the scheduling module; wherein data_id is used to identify the storage location of the data, and dc_id is used to identify the storage address of the message in the directory information.

[0032] The inter-chip interconnection circuit provided by the present invention improves scheduling reliability by sending the storage location of data and the storage address of the message in the directory information to the scheduling module together with the message and data.

[0033] According to an inter-chip interconnection circuit provided by the present invention, when applied to inter-chip interconnection, the CCIX protocol layer message switching and forwarding module 1 is also communicatively connected to a local processor chip, and the custom message switching and forwarding module 4 is also communicatively connected to the custom message switching and forwarding modules of other inter-chip interconnection circuits connected to remote processor chips.

[0034] When the inter-chip interconnect module is in use (i.e., used to interconnect processor chips), the CCIX protocol layer message switching and forwarding module 1 is also in communication with the local processor chip, and the custom message switching and forwarding module 4 is also in communication with the custom message switching and forwarding modules of other inter-chip interconnect circuits connected to the remote processor chip. Custom message switching and forwarding module 4 communicates with the remote processor chip by communicating with the custom message switching and forwarding modules of other inter-chip interconnect circuits connected to the remote processor chip, thereby establishing interconnection between the local and remote processor chips.

[0035] The inter-chip interconnection circuit provided by the present invention improves the reliability of inter-chip interconnection by enabling, when applied to inter-chip interconnection, the CCIX protocol layer message switching and forwarding module to also communicate with the local processor chip, and the custom message switching and forwarding module to also communicate with the custom message switching and forwarding modules of other inter-chip interconnection circuits connected to the remote processor chip.

[0036] According to an inter-chip interconnect circuit provided by the present invention, the messages received by the message cache module 301 include rqt0 channel messages and rqt2 channel messages sent by the custom message switching and forwarding module 4; wherein the rqt0 channel information includes a read request and a no-data request from a remote processor; the rqt2 channel message includes a snoop response from a local processor chip and a write-back request from a remote processor; and the messages received by the message cache module 301 also include a request response and a snoop request sent by the CCIX protocol layer message switching and forwarding module 1 from a local processor chip.

[0037] Figure 2 FIG. 1 is a schematic diagram of the communication between the message cache module, the storage module and the scheduling module in the inter-chip interconnection circuit provided by the present invention. Figure 2 As shown,

[0038] Message buffer module 3 receives rqt0 channel messages (read & dataless read and dataless requests), rqt2 channel messages (snp_rsp & writeback snoop response and writeback request), and ack_rsp (ACK response) messages (ack_rsp may or may not be present as required) from the custom message switching and forwarding module (denoted as XBAR), as well as req_rsp (request response) and snp (snoop request) messages from the CCIX protocol layer message switching and forwarding module (denoted as PD). It caches the messages and sends them, along with the assigned data ID (identifying the data storage location) and DC ID (the message's address in the directory information), to the scheduling module (denoted as schedule).

[0039] Assign data id to the rqt2 (snp_rsp & writeback) message and store the snp_rsp data and writeback data in the corresponding RAM respectively (since the write request sent to PD and the snprsp sent to PD are two different channels, the wb / snprsp data are stored separately). The message information is written to the FIFO after adding the data id.

[0040] The snp_rsp information in rqt2 is directly scheduled into the schedule module.

[0041] The req_rsp message is stored in RAM according to the PD's input address (PD pre-assigns data id).

[0042] The SNP request is read from the FIFO and written into the storage module (denoted as DC), and the SNP request with dc_id information output by DC is output to the schedule module.

[0043] The above allocation of data_id and dc_id is to provide corresponding data storage addresses.

[0044] After reading the write-back requests in rqt0 and rqt2, the system first checks whether a request with the same address is being processed. If so, it pauses and enters the DC module. Otherwise, it outputs the message to the DC module and outputs the write-back requests in rqt0 and rqt2 with the dc_id information from the DC to the schedule module according to the scheduling situation.

[0045] The method for determining address conflicts is as follows: Read / dataless / wb requests store the requested address (as RAM write data) in rhb_addr_dram based on the rhbid (RAM write address) assigned by the schedule module. Each new request is compared with all addresses in rhb_addr_dram. rhb_addr_dram is a distributed RAM implemented as a two-dimensional array.

[0046] The schedule module receives input from multiple channels of the cache processing module and arbitrates the packets to be processed in the order of ack_rsp > memrsp > snp_rsp > snp > req. Req represents the write-back request in rqt0 and rqt2.

[0047] Figure 2 The meanings of other symbols are as follows: fifo_rqt2: listen for responses / writeback requests temporarily

[0048] dataid_alloc_free: dataid allocation release

[0049] wb_databuf: write back data buffer

[0050] snprsp_databuf: monitor response data buffer

[0051] wb_dmbuf: write back data valid indication buffer

[0052] snprsp_dmbuf: monitor response data valid indication cache

[0053] fifo_rqt2_snprsp_msg: monitor response message control information cache

[0054] fifo_rqt2_wb_msg: write back data message control information cache

[0055] fifo_rqt0: read / no data request buffer

[0056] shift_reg: register cache, select non-conflicting address requests

[0057] rhb_addr: storage of request address in process

[0058] fifo_ack_rsp(rsp2): ack response cache

[0059] fifo_rqt0: read / no data request buffer with directory ID

[0060] fifo_wb: writeback request cache with directory ID

[0061] memrsp_fifo: request response control information cache

[0062] memrsp_dmbuf: request response data valid indication cache

[0063] memrsp_databuf: request response data buffer

[0064] fifo_snp: snoop message cache

[0065] dc_id+snp: snoop message cache with directory ID

[0066] The inter-chip interconnection circuit provided by the present invention implements cache processing of different types of messages by receiving rqt0 channel messages and rqt2 channel messages sent by a custom message switching and forwarding module, and receiving request responses and monitoring requests from a local processor chip sent by a CCIX protocol layer message switching and forwarding module.

[0067] According to an inter-chip interconnection circuit provided by the present invention, the protocol processing module is further used to store request-related information into a first table item and store monitoring-related information into a second table item; wherein: the storage content of the first table item includes the validity information of the first table item, the hit information of the directory information, the request type code, the request source ID, the transaction ID in the request message, the newly generated transaction ID sent to the local processor chip, the request message address, and the request destination ID obtained according to the address in the request message; the storage content of the second table item includes the validity information of the second table item, the hit information of the directory information, the monitoring type code, the monitoring address, and the number of monitoring responses not returned. The number of inter-chip interconnect circuits, the request destination ID in the snoop message when initiating snooping on other inter-chip interconnect circuits, the transaction ID in the snoop message when initiating snooping on other inter-chip interconnect circuits, the cache attributes in the returned snoop response message, the data validity indication signal returned in the snoop response, the ID number assigned to the data in the returned snoop response, whether the snoop indication information initiated by the local CPU has been received when all snoop responses are returned, the indication information of whether to re-initiate snooping based on the protocol table, the initiator ID of the snoop message, the transaction ID of the snoop message received from the local processor chip, and the indication information of the CCIX protocol layer message switching and forwarding module received in the snoop response message.

[0068] The protocol processing module 304 first receives and caches the messages sent by the scheduling module 302 to speed up the scheduling of the scheduling module 302. When the cache is about to overflow, the scheduling is stopped. Since the formats of each message are inconsistent, a valid flag (for distinguishing the message type) is added to each message during caching to distinguish the messages.

[0069] An RHB module can be configured within the protocol processing module 304 to store and retrieve the first entry (RHB entry) for request-related information. The depth is calculated as: credit value (the maximum number of requests a CPU can store) * number of CPUs * number of NCs. NC represents the inter-chip interconnect circuit. One RHB entry is used to store request information for both CPUs. To ensure proper functionality, after reset, the rhb_array is initialized, clearing the RAM to zeros.

[0070] RHB entries store the following contents: v_rhb+v_dir+reqop+srcid+cc_txnid+ccix_txnid+addr+ccix_tgtid.

[0071] in: v_rhb: RHB table entry is valid, it is valid after the request arrives and invalid after the request ends

[0072] v_dir: Directory validity information. If the directory is not hit, it is 0; if the directory is hit, it is 1.

[0073] reqop: request encoding, indicating various request types

[0074] srcid: request source ID

[0075] cc_txnid: transaction ID in the request message

[0076] ccix_txnid: newly generated transaction ID sent to the local CPU

[0077] addr: request message address

[0078] ccix_tgtid: Destination ID obtained based on the address in the request message

[0079] The above information is the content of input and output messages.

[0080] An LSB module can be set up in the protocol processing module 304 to store and search the second table entry (LSB entry) for monitoring-related information. The depth is: credit value * number of CPUs * number of NCs. To ensure correct functionality, after reset, rhb_array will be initialized, that is, the RAM will be cleared to zero.

[0081] The contents of the lsb storage include: v_lsb+v_dir+snpop+addr+snpnum+cc_tgtid+cc_txnid+respattr+v.data+dataid+ccixsnp.get+resnp+srcid+ccix_txnid+pd.

[0082] in: v_dir: Directory validity information. If the directory is not hit, it is 0; if the directory is hit, it is 1.

[0083] snpop: monitoring type code

[0084] addr: listening address

[0085] snpnum: The number of listening NCs that did not return a listening response

[0086] cc_tgtid: Destination ID in the monitoring message when monitoring other NCs

[0087] cc_txnid: The transaction ID in the monitoring message when monitoring other NCs

[0088] respattr: Returns the cache attributes (NC cache status) in the listening response message

[0089] v.data: Returns the valid data indication signal of the monitoring response

[0090] dataid: Returns the ID number assigned to the data in the monitoring response

[0091] ccixsnp.get: When all monitoring responses are returned, whether the monitoring initiated by the local CPU has been received

[0092] resnp: Indicates whether to re-initiate monitoring based on the protocol table

[0093] srcid: Source ID of the received monitoring message

[0094] ccix_txnid: Transaction ID for receiving local CPU monitoring messages

[0095] pd: PD information indication received in the monitoring response message

[0096] In addition to the message content, the above information, ccixsnp.get and resnp, are information obtained based on the actual snoop reception. ccixsnp.get indicates that the local processing module (LP) has received the snoop information sent by the CPU before the LP module's snoop response arrives. This information is used to determine when to clear the LSB table content. resnp indicates that the snoop request initiated by the CPU requires a higher level of authority, causing the LP module to resend the snoop request.

[0097] The inter-chip interconnection circuit provided by the present invention provides a basis for protocol processing of messages by setting a first table entry and a second table entry to store request related information and monitoring related information respectively.

[0098] According to an inter-chip interconnect circuit provided by the present invention, the protocol processing module, when used to implement protocol processing of each message based on the CCIX protocol, is specifically used to: generate a new transaction ID, request source ID, and request destination ID for the read request, the no-data request, and / or the write-back request, and output the request to the local processor chip; determine whether to initiate monitoring based on the received directory information, generate a monitoring request, and send it to the remaining inter-chip interconnect circuits, and record the first table entry and the second table entry; for the request response, modify the transaction ID, request source ID, and request destination ID in the received request response based on the recorded information in the first table entry, and send the newly generated request response to the local processor chip; To other inter-chip interconnect circuits, determine whether a confirmation message needs to be sent based on the request type stored in the first table entry. If so, send the confirmation message; if not, clear the first table entry; for the snoop request, update the content of the second table entry based on the second table entry and the received snoop information, and regenerate a snoop request and send it to the other inter-chip interconnect circuits or generate a snoop response and send it to the local processor chip according to the CCIX protocol; for the snoop response, update or clear the content of the second table entry based on the second table entry and the received snoop response information, and regenerate a snoop request and send it to the other inter-chip interconnect circuits or generate a snoop response and send it to the local processor chip according to the CCIX protocol.

[0099] A mph module can be set in the protocol processing module 304 to be responsible for protocol processing. It needs to process the input req, req_rsp, ack_rsp, snp, snp_rsp messages according to the CCIX protocol, and perform write, read or erase operations on rhb, lsb, DC according to the protocol processing results, and generate req, snp, ackrsp, snprsp, memrsp messages and output them to the corresponding modules.

[0100] The req protocol processing primarily involves generating a new transaction ID, srcid (the ID of the source CPU to the NC), and tgtid (the ID of the NC to the target CPU), and then outputting the request to the local CPU. Based on the directory information retrieved, the CPU determines whether to initiate a snoop and generates snoop requests based on relevant information such as the request type, sending them to other NCs. The CPU also records the RHB and LSB entries.

[0101] The req_rsp protocol processing mainly modifies the transaction ID, srcid, tgtid, etc. in the received req_rsp based on the record information in the RHB table entry and sends the newly generated req_rsp to other NCs. It also determines whether ack_rsp is required based on the request type stored in the RHB. If not, the RHB table entry can be cleared.

[0102] The ack_rsp protocol processing mainly modifies the transaction ID number, srcid, tgtid, etc. in the received ack_rsp according to the record information in the RHB table entry and sends the newly generated ack_rsp to the local CPU.

[0103] The SNP protocol mainly updates the LSB table content based on the LSB table entry and the received monitoring information. It then regenerates the SNP according to the CCIX protocol and sends it to other NCs or generates an SNP_RSP to send to the local CPU. The LP handles it according to different situations: if all other NCs have returned SNP_RSP and the LP has received SNP, it can generate SNP_RSP and send it to the local CPU. If not all other NCs have returned SNP_RSP, even if the LP has received SNP, it will wait until all other NCs have returned SNP_RSP before generating SNP_RSP and sending it to the local CPU.

[0104] The snp_rsp protocol mainly updates or clears the LSB entry based on the received snoop response information. It then regenerates the snoop request (SNP) and sends it to other NCs, or generates an snop_rsp and sends it to the local CPU, according to the CCIX protocol. Upon receipt of the snp_rsp, the resnp flag in the LSB entry is checked (resnp is generated according to the protocol after the snoop request arrives). If it detects that snooping needs to be re-initiated, it generates an SNP and sends it to other NCs.

[0105] Figure 3 This is a schematic diagram of the protocol pipeline processing clock information of the inter-chip interconnection circuit provided by the present invention. In order to speed up the processing, pipeline processing is adopted, and the delay is mainly calculated from the output of the cache processing module (LPS) to the input of the processing result output module (LPQ module), such as Figure 3 As shown, it takes seven clock cycles from receiving the scheduled protocol to completing the protocol processing, with the main delay coming from reading the directory information. In practical situations, if timing permits, receiving the protocol message and reading the directory can be completed in the same clock cycle. Currently, reading the directory requires a three-clock delay. Similarly, if overall timing permits, this delay can be reduced.

[0106] The LPQ module implements the output path for messages and data. This includes storage and transmission of outputs, release of data IDs, and release of rhbid and lsbids. The above allocation of rhbid and lsbids is used to allocate storage addresses for RHB and LSB entries.

[0107] The inter-chip interconnection circuit provided by the present invention realizes the protocol processing of read request, no-data request, write-back request, request response, monitoring request and monitoring response.

[0108] Figure 4This is a schematic diagram of the structure of the inter-chip interconnection system provided by the present invention. Figure 4 As shown, the inter-chip interconnect system includes at least one pair of interconnect structures, the interconnect structure including a first processor chip, a first inter-chip interconnect circuit, a second inter-chip interconnect circuit, and a second processor chip. The first inter-chip interconnect circuit includes a first CCIX protocol layer message switching and forwarding module, a first remote agent module, a first local agent module, and a first custom message switching and forwarding module. The first local agent module includes a first message buffer module, a first scheduling module, a first storage module, a first protocol processing module, and a first processing result output module. The second inter-chip interconnect circuit includes a second CCIX protocol layer message switching and forwarding module, a second remote agent module, a second local agent module, and a second custom message switching and forwarding module. The second local agent module includes a second message buffer module, a second scheduling module, a second storage module, a second protocol processing module, and a second processing result output module. The first processor chip is connected to the first CCIX protocol layer message switching and forwarding module, the first custom message switching and forwarding module is connected to the second custom message switching and forwarding module, and the second processor chip is connected to the second CCIX protocol layer message switching and forwarding module.

[0109] The prefixes "first" and "second" are used to distinguish identical modules. The first inter-chip interconnect circuit and the second inter-chip interconnect circuit can employ the inter-chip interconnect circuit provided in the above embodiment. The internal module structures and connection methods of the first and second inter-chip interconnect circuits can also be the same as those in the above embodiment.

[0110] The first processor chip is connected to the first CCIX protocol layer message switching and forwarding module, meaning that the first processor chip is the local processor chip connected to the first inter-chip interconnect circuit. The second processor chip is connected to the second CCIX protocol layer message switching and forwarding module, meaning that the second processor chip is the local processor chip connected to the second inter-chip interconnect circuit. The first custom message switching and forwarding module is connected to the second custom message switching and forwarding module, thereby establishing connectivity between the first inter-chip interconnect circuit and the second inter-chip interconnect circuit, further enabling interconnection between the first processor chip and the second processor chip.

[0111] The inter-chip interconnect system may include multiple pairs of the aforementioned interconnect structures. The interconnect structures may overlap. For example, the inter-chip interconnect system may also include a third processor chip interconnected with the first processor chip, and a third inter-chip interconnect circuit connected to the third processor chip. The first processor chip is connected to the first CCIX protocol layer message switching and forwarding module, the first custom message switching and forwarding module is further connected to the custom message switching and forwarding module of the third inter-chip interconnect circuit, and the third processor chip is connected to the CCIX protocol layer message switching and forwarding module of the third inter-chip interconnect circuit.

[0112] The inter-chip interconnection system provided by the present invention includes at least one pair of interconnection structures, the interconnection structure including a first processor chip, a first inter-chip interconnection circuit, a second inter-chip interconnection circuit, and a second processor chip. The first processor chip is connected to a first CCIX protocol layer message switching and forwarding module, the first custom message switching and forwarding module is connected to a second custom message switching and forwarding module, and the second processor chip is connected to a second CCIX protocol layer message switching and forwarding module. The inter-chip interconnection system is implemented based on the inter-chip interconnection circuit.

[0113] According to an inter-chip interconnection system provided by the present invention, for a read request, no data request, write-back request, and / or snoop response sent by a first processor chip to a second processor chip, the transmission link is, in order: the first processor chip, the first custom message switching and forwarding module, the first remote proxy module, the first CCIX protocol layer message switching and forwarding module, the second CCIX protocol layer message switching and forwarding module, the second message buffer module, the second scheduling module, the second protocol processing module, the second processing result output module, the second custom message switching and forwarding module, and the second processor chip. For a read request, no data request, write-back request, or snoop response sent by the second processor chip to the first processor chip, the transmission link is, in order: the second processor chip, the second custom message switching and forwarding module, the second remote proxy module, the second CCIX protocol layer message switching and forwarding module, the first CCIX protocol layer message switching and forwarding module, the first message buffer module, the first scheduling module, the first protocol processing module, the first processing result output module, the first custom message switching and forwarding module, and the first processor chip.

[0114] Each module on the transmission link processes the received signal or forwards the signal according to the description of the above embodiments.

[0115] The inter-chip interconnection system provided by the embodiment of the present invention realizes data transmission of read requests, no-data requests, write-back requests and / or snoop responses.

[0116] According to an inter-chip interconnection system provided by the present invention, for a request response and / or a snoop request sent by the first processor chip to the second processor chip, the transmission link is, in order, the first processor chip, the first custom message switching and forwarding module, the first message buffer module, the first scheduling module, the first protocol processing module, the first processing result output module, the first custom message switching and forwarding module, the second custom message switching and forwarding module, the second remote proxy module, the second CCIX protocol layer message switching and forwarding module, and the second processor chip. For a request response and / or a snoop request sent by the second processor chip to the first processor chip, the transmission link is, in order, the second processor chip, the second custom message switching and forwarding module, the second message buffer module, the second scheduling module, the second protocol processing module, the second processing result output module, the second custom message switching and forwarding module, the first custom message switching and forwarding module, the first remote proxy module, the first CCIX protocol layer message switching and forwarding module, and the first processor chip.

[0117] Each module on the transmission link processes the received signal or forwards the signal according to the description of the above embodiments.

[0118] The inter-chip interconnection system provided by the embodiment of the present invention realizes data transmission of request response and / or monitoring request.

[0119] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0120] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An inter-chip interconnection circuit, characterized in that: include: CCIX protocol layer message switching and forwarding module, remote proxy module, local proxy module and custom message switching and forwarding module, the local proxy module includes a message buffer module, a scheduling module, a storage module, a protocol processing module and a processing result output module, wherein: The CCIX protocol layer message switching and forwarding module is communicatively connected with the message buffer module, the remote proxy module and the processing result output module; The remote proxy module is also in communication connection with the custom message exchange and forwarding module; The custom message switching and forwarding module is also communicatively connected with the message buffer module and the processing result output module; The message buffer module is also in communication connection with the scheduling module and the storage module; The scheduling module is also in communication connection with the protocol processing module and the storage module; The protocol processing module is also communicatively connected with the processing result output module and the storage module.

2. The inter-chip interconnection circuit according to claim 1, characterized in that: The cache processing module is used to implement the input path of the internal messages and data of the local proxy module pipeline; the storage module is used to store and update directory information, and the directory information includes message address and cache status; the scheduling module is used to implement the scheduling processing of messages; the protocol processing module is used to implement the protocol processing of each message based on the CCIX protocol, and the processing result output module is used to output the protocol processing result.

3. The inter-chip interconnection circuit according to claim 2, characterized in that: The cache processing module is also used to send the message and data together with the allocated data_id and dc_id to the scheduling module; wherein the data_id is used to identify the storage location of the data, and the dc_id is used to identify the storage address of the message in the directory information.

4. The inter-chip interconnection circuit according to claim 2, characterized in that: When applied to inter-chip interconnection, the CCIX protocol layer message switching and forwarding module is also communicatively connected to the local processor chip, and the custom message switching and forwarding module is also communicatively connected to the custom message switching and forwarding modules of other inter-chip interconnection circuits connected to the remote processor chip.

5. The inter-chip interconnection circuit according to claim 3, characterized in that: The message received by the message cache module includes the rqt0 channel message and the rqt2 channel message sent by the custom message exchange forwarding module; wherein the rqt0 channel information includes a read request and a no data request from a remote processor; the rqt2 channel message includes a snoop response from a local processor chip and a write back request from a remote processor; The message received by the message buffer module also includes a request response and a monitoring request from the local processor chip sent by the CCIX protocol layer message switching and forwarding module.

6. The inter-chip interconnection circuit according to claim 5, characterized in that: The protocol processing module is also used to store request related information into the first table item and store monitoring related information into the second table item; wherein: The storage content of the first table entry includes validity information of the first table entry, hit information of the directory information, request type code, request source ID, transaction ID in the request message, newly generated transaction ID sent to the local processor chip, request message address, and request destination ID obtained according to the address in the request message; The storage content of the second table item includes validity information of the second table item, hit information of the directory information, monitoring type code, monitoring address, number of inter-chip interconnection circuits that have not returned monitoring responses, request destination ID in the monitoring message when initiating monitoring to other inter-chip interconnection circuits, transaction ID in the monitoring message when initiating monitoring to other inter-chip interconnection circuits, cache attribute in the returned monitoring response message, data validity indication signal returned in the monitoring response, ID number assigned to the data in the returned monitoring response, indication information of whether the monitoring initiated by the local CPU has been received when all monitoring responses are returned, indication information of whether the monitoring needs to be re-initiated according to the protocol table, initiator ID of the monitoring message, transaction ID of the local processor chip monitoring message received, and indication information of the CCIX protocol layer message switching and forwarding module received in the monitoring response message.

7. The inter-chip interconnection circuit according to claim 6, characterized in that: When the protocol processing module is used to implement protocol processing of each message based on the CCIX protocol, it is specifically used to: For the read request, the no-data request and / or the write-back request, generate a new transaction ID, a request source ID and a request destination ID and output the request to a local processor chip; According to the received directory information, determine whether to initiate monitoring and generate a monitoring request to send to other inter-chip interconnection circuits, and record the first table entry and the second table entry; For the request response, modify the transaction ID, request source ID, and request destination ID in the received request response according to the record information in the first table entry, and send the newly generated request response to other inter-chip interconnection circuits, and determine whether a confirmation message needs to be sent according to the request type stored in the first table entry, and if so, send the confirmation message; if not, clear the first table entry; For the monitoring request, according to the second table entry and the received monitoring information, update the content of the second table entry, and regenerate a monitoring request and send it to other inter-chip interconnection circuits or generate a monitoring response and send it to a local processor chip according to the CCIX protocol; For the monitoring response, according to the second table entry and the received monitoring response information, the content of the second table entry is updated or cleared, and according to the CCIX protocol, a monitoring request is regenerated and sent to other inter-chip interconnection circuits or a monitoring response is generated and sent to a local processor chip.

8. An inter-chip interconnection system based on the inter-chip interconnection circuit according to any one of claims 1 to 7, characterized in that: The method comprises at least one pair of interconnect structures, wherein the interconnect structure comprises a first processor chip, a first inter-chip interconnect circuit, a second inter-chip interconnect circuit and a second processor chip; wherein: The first inter-chip interconnection circuit includes a first CCIX protocol layer message switching and forwarding module, a first remote agent module, a first local agent module and a first custom message switching and forwarding module, and the first local agent module includes a first message buffer module, a first scheduling module, a first storage module, a first protocol processing module and a first processing result output module; The second inter-chip interconnection circuit includes a second CCIX protocol layer message switching and forwarding module, a second remote agent module, a second local agent module and a second custom message switching and forwarding module, and the second local agent module includes a second message buffer module, a second scheduling module, a second storage module, a second protocol processing module and a second processing result output module; The first processor chip is connected to the first CCIX protocol layer message switching and forwarding module, the first custom message switching and forwarding module is connected to the second custom message switching and forwarding module, and the second processor chip is connected to the second CCIX protocol layer message switching and forwarding module.

9. The inter-chip interconnection system according to claim 8, characterized in that: For a read request, a no-data request, a write-back request and / or a snoop response sent by the first processor chip to the second processor chip, the transmission links are, in sequence, the first processor chip, the first custom message switching and forwarding module, the first remote proxy module, the first CCIX protocol layer message switching and forwarding module, the second CCIX protocol layer message switching and forwarding module, the second message cache module, the second scheduling module, the second protocol processing module, the second processing result output module, the second custom message switching and forwarding module, and the second processor chip; For a read request, a no-data request, a write-back request or a snoop response sent by the second processor chip to the first processor chip, the transmission links are, in sequence, the second processor chip, the second custom message switching and forwarding module, the second remote agent module, the second CCIX protocol layer message switching and forwarding module, the first CCIX protocol layer message switching and forwarding module, the first message cache module, the first scheduling module, the first protocol processing module, the first processing result output module, the first custom message switching and forwarding module, and the first processor chip.

10. The inter-chip interconnection system according to claim 8, characterized in that: For the request response and / or monitoring request sent by the first processor chip to the second processor chip, the transmission link is sequentially the first processor chip, the first custom message switching and forwarding module, the first message cache module, the first scheduling module, the first protocol processing module, the first processing result output module, the first custom message switching and forwarding module, the second custom message switching and forwarding module, the second remote agent module, the second CCIX protocol layer message switching and forwarding module, and the second processor chip; For the request response and / or monitoring request sent by the second processor chip to the first processor chip, the transmission links are sequentially the second processor chip, the second custom message switching and forwarding module, the second message cache module, the second scheduling module, the second protocol processing module, the second processing result output module, the second custom message switching and forwarding module, the first custom message switching and forwarding module, the first remote agent module, the first CCIX protocol layer message switching and forwarding module, and the first processor chip.

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