Method and system for realizing RDMA network card request queue

Abstract

The invention relates to the technical field of computer networks, in particular to an implementation method and system for an RDMA network card request queue, and the method comprises the steps: checking whether a residual space exists in an RDMA Cache module or not when a write request is received; if yes, writing the writing information of the writing request into an RDMA Cache module, updating a free bit, and recording a queue pair number and an unfinished pointer; if not, writing the writing information of the writing request into a host memory module; when a read request is received, checking whether the queue pair number and the unfinished pointer carried by the read request are matched with historical records in the RDMA Cache module or not; if yes, reading from the RDMA Cache module; and if not, reading from the host memory module. According to the invention, multiple QPs in the RDMA network card share the internal resources of the Cache, the resource consumption is reduced, and the utilization rate of the cache is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer networks, and in particular to a method and system for realizing an RDMA network card request queue. Background Art

[0002] RDMA (Remote Direct Memory Access) network card is a high-performance network interface card that allows one computer in the network to directly access the memory of another computer without the intervention of the operating system.

[0003] In RDMA communication, such as Figure 1 As shown in the figure, SQ (Send Queue) and RQ (Receive Queue) are the two basic components of QP (Queue Pair), which are used to send and receive data respectively. The TX side of the local node sends multiple unresponded request packets, namely outstanding requests, to the RX side of the remote node through SQ, and the RX side of the remote node receives these request packets through RQ. In order to ensure that the RX side of the local node can correctly process the response packet returned by the TX side of the remote node, the local node needs to store the corresponding write information in the write information queue when sending the request packet. When the number of QPs is large, how to effectively record and manage these request queue information while ensuring read and write performance becomes a key issue in the design of RDMA network cards. At present, there are two main implementation schemes for RDMA network card request queues: the first is to cache all request queue information inside the network card, avoiding high latency in accessing the host memory, thereby improving performance. The second method is to cache only part of the information inside the network card, and store the rest of the information in the host memory. The linked list management method is used to implement multi-QP shared cache, which can effectively reduce the internal storage requirements.

[0004] In the above schemes, the first implementation requires placing a larger storage unit inside the RDMA network card, which increases the chip area and power consumption. The second implementation may affect performance due to some limitations in its linked list management method, such as write restrictions when resources are insufficient and the complexity of packet loss retransmission. Summary of the invention

[0005] In view of this, the present invention provides a method and system for implementing an RDMA network card request queue to solve the limitations of the existing linked list management method.

[0006] In a first aspect, the present invention provides a method for implementing an RDMA network card request queue, the method being applied to an RDMACache module in an implementation system of an RDMA network card request queue, the system further comprising a host memory module connected to the RDMACache module, the RDMACache module managing a cache address stored in the request queue, a free bit of the cache address, a queue pair number and an unfinished pointer, the method comprising:

[0007] When receiving a write request, checking whether there is any remaining space inside the RDMACache module;

[0008] If there is remaining space, the write information of the write request is written into the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated, and the queue pair number and the unfinished pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written into the host memory module;

[0009] When a read request is received, checking whether the queue pair number and the incomplete pointer carried by the read request match the historical records in the RDMACache module;

[0010] If there is a match, the storage data corresponding to the read request is read from the RDMACache module; if there is no match, the storage data corresponding to the read request is read from the host memory module.

[0011] The above scheme associates the queue pair number (QPN) in the RDMA network card with the unfinished pointer on the host side. By mapping the queue pair number and the unfinished pointer to the internal storage address of the cache, multiple request queues can be effectively managed, thereby realizing that multiple QPs in the RDMA network card share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the cache. In addition, the above scheme avoids the defects of the traditional linked list management method that may cause performance bottlenecks and resource waste through the optimized data structure of the direct mapping mechanism, improves data access efficiency, and enables the cache to respond to requests more efficiently. In addition, the above scheme processes read requests through outstanding. When the on-chip cache misses, it immediately initiates a read request to the host memory module. While waiting for the host memory module to respond, it processes the next read request to achieve parallel processing. By processing read requests in parallel, the waiting time is reduced, the read throughput of the cache is improved, and the overall delay caused by waiting for a single read request to be completed is reduced. The above solution achieves efficient resource utilization by sharing cache resources and avoiding linked list management. It improves the cache read performance and overall throughput by outstandingly processing read requests, reduces management complexity and overhead, and improves system stability and reliability.

[0012] In an optional implementation, when receiving a write request, checking whether there is remaining space inside the RDMACache module includes:

[0013] When a write request is received, an address free bit query is performed on the RDMACache module based on the free bits of the Cache address to obtain the remaining space in the RDMACache module.

[0014] In an optional implementation, if there is remaining space, writing the write information of the write request into the target free address of the RDMA Cache module, updating the free bit corresponding to the target free address, and recording the queue pair number and the unfinished pointer corresponding to the write request, including:

[0015] If there is remaining space in the RDMA Cache module, selecting a target free address from the free address bits of the RDMA Cache module;

[0016] Writing the write information of the write request into the target idle address, and updating the address valid position of the target idle address to a non-idle state;

[0017] The queue pair number and the incomplete pointer corresponding to the write request are recorded and associated with the target idle address.

[0018] In an optional implementation, when receiving a read request, checking whether the queue pair number and the incomplete pointer carried by the read request match the historical record in the RDMACache module includes:

[0019] When a read request is received, extracting the queue pair number and the unfinished pointer carried by the read request;

[0020] It is determined whether the queue pair number and the incomplete pointer carried by the read request match the historical record corresponding to the target cache address in the RDMA Cache module, and at the same time, it is determined whether the target cache address is in a non-idle state.

[0021] In an optional implementation manner, if there is a match, reading the storage data corresponding to the read request from the RDMACache module includes:

[0022] If there is a match, and the matched target cache address is in a non-idle state, a cache hit is determined, and the storage data corresponding to the read request is read from the target cache address.

[0023] In an optional implementation, if there is no match, reading the storage data corresponding to the read request from the host memory module includes:

[0024] If there is no match, or the matched target Cache address is in an idle state, it is determined that the Cache does not hit, and a read request is initiated to the host memory module to read the storage data corresponding to the read request;

[0025] While waiting for the host memory module to respond, the next read request is processed to achieve parallel processing of multiple read requests.

[0026] In an optional embodiment, the method further includes:

[0027] After each matching query, the hit result is recorded in the read direction record FIFO of the RDMA Cache module;

[0028] When the read direction record FIFO is not empty, a data reading path is selected according to the record information in the read direction record FIFO; the data reading path includes reading the storage data corresponding to the read request from the RDMACache module and reading the storage data corresponding to the read request from the host memory module.

[0029] In a second aspect, the present invention provides a system for implementing an RDMA network card request queue, the system comprising: an RDMA Cache module and a host memory module connected to each other, the RDMA Cache module managing a Cache address stored in the request queue, a free bit of the Cache address, a queue pair number and an unfinished pointer;

[0030] The RDMA Cache module is used to execute the above-mentioned method for implementing an RDMA network card request queue.

[0031] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute a method for implementing an RDMA network card request queue according to the first aspect or any corresponding embodiment thereof.

[0032] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a method for implementing an RDMA network card request queue according to the first aspect or any corresponding embodiment thereof.

[0033] In a fifth aspect, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute a method for implementing an RDMA network card request queue according to the first aspect or any corresponding embodiment thereof.

[0034] The present invention associates the queue pair number (QPN) in the RDMA network card with the unfinished pointer on the host side. By mapping the queue pair number and the unfinished pointer to the internal storage address of the Cache, multiple request queues can be effectively managed, thereby realizing that multiple QPs in the RDMA network card share the internal resources of the Cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the Cache. In addition, the present invention avoids the defects of the traditional linked list management method that may cause performance bottlenecks and resource waste through the optimized data structure of the direct mapping mechanism, improves data access efficiency, and enables the Cache to respond to requests more efficiently. In addition, the present invention processes read requests through outstanding. When the on-chip Cache does not hit, it immediately initiates a read request to the host memory module. While waiting for the host memory module to respond, it processes the next read request to achieve parallel processing. By processing read requests in parallel, the waiting time is reduced, the read throughput of the Cache is improved, and the overall delay caused by waiting for a single read request to be completed is reduced. The present invention realizes efficient resource utilization by sharing Cache high-speed cache resources and avoiding linked list management, improves the read performance and overall throughput of the Cache by outstandingly processing read requests, reduces management complexity and overhead, and improves the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 The working diagram of the RDMA network card is shown;

[0037] Figure 2 A schematic diagram showing the structure of multi-QP shared Cache using the traditional linked list management method;

[0038] Figure 3 It is a structural schematic diagram of an implementation system of an RDMA network card request queue according to an embodiment of the present invention;

[0039] Figure 4 It is a flowchart of a method for implementing an RDMA network card request queue according to an embodiment of the present invention;

[0040] Figure 5 is a flowchart of another method for implementing an RDMA network card request queue according to an embodiment of the present invention;

[0041] Figure 6 is a flowchart of a method for implementing a write operation according to an embodiment of the present invention;

[0042] Figure 7 is a flow chart of a method for implementing a read operation according to an embodiment of the present invention;

[0043] Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0045] See also Figure 2 The schematic diagram of the structure of the traditional linked list management method to realize multi-QP shared Cache cache, when interacting with the host memory to manage the request information of multiple queue pairs (Queue Pairs, QPs), Figure 2 The RDMA network card has a cache inside, which is used to store part of the request queue information (for example, request descriptors, metadata, etc.). The complete information or when the cache space is insufficient, the remaining information will be stored in the host memory. The RDMA network card's cache uses a linked list management method to allow multiple QPs to share the cache space. Each QP has one or more outstanding requests, and the information of these requests (such as the request status, data location, etc.) is stored in the cache or host memory.

[0046] When the RDMA network card needs to access the request queue information of a certain QP, it will first search in the cache. If the required information is not found in the cache (cache miss), the RDMA network card will read the corresponding information from the host memory through the PCIE bus. Each QP's request queue in the host memory has an "off-chip pointer" (outptr) that points to the location of the currently processed request in the queue. The cache manages the storage address of these request queue information in the cache through a linked list.

[0047] exist Figure 2In the example, the host memory supports "x" QPs, and each QP supports outstanding storage of "y" unresponded request information, that is, y data entries. Each entry is associated with a specific outptr value. Each data entry (such as entry.0, entry.1,..., entry.y-1) has an associated outptr value. Outptr represents the pointer to the request queue information in the host memory. RDMA_CACHE is used to cache data from the host memory to improve access speed. The linked list control module is used to manage the entries in RDMA_CACHE, which uses a linked list data structure to maintain the association between entries. Each cache entry in the linked list control module can contain the following information: ram_addr-the address of the cache entry, ram_data-the data content of the cache entry, bitmap-a bitmap used to mark whether the address is occupied, and next_addr-the address pointing to the next cache entry. In the data content of the ram_data-cache entry, info0 represents the first or initial data block of the queue pair, or the information entry with sequence number 0, qp0 refers to the queue pair (QueuePair) numbered 0, "qp" is the abbreviation of queue pair, and the number 0 represents a specific queue pair number. Exemplarily, "info0_of_qp0" represents the first or initial data entry (info0) in the storage area reserved for the queue pair (qp0) numbered 0.

[0048] Figure 2 It can effectively reduce internal storage, but its linked list management method has the following two disadvantages:

[0049] 1) When the internal resources of the cache are insufficient, the request queue information can only be written into the host memory, not into the cache. Even if there is space in the cache later, if there is information in the host memory that is not in the cache, if the subsequent request queue information of the QP is to be written into the cache, it will cost a lot to maintain the relationship between the cache internal linked list and the host memory request queue pointer;

[0050] 2) In the RDMA protocol, there will be a scenario where the request packet needs to be retransmitted due to packet loss during transmission. At this time, the off-chip pointer of the Cache needs to be rolled back. For the linked list management method, because it is stored in sequence, the linked list corresponding to the QP in the Cache needs to be cleared to maintain the order of the request queue. In order to solve the disadvantages of the linked list management method, this embodiment provides an implementation method of the RDMA network card request queue, which associates the queue pair number (QueuePair Number, QPN) in the RDMA network card with the unfinished pointer on the host side. By mapping the queue pair number and the unfinished pointer to the internal storage address of the Cache, multiple request queues can be effectively managed, thereby realizing the sharing of internal Cache resources by multiple QPs in the RDMA network card. This mapping mechanism reduces resource consumption and improves the utilization of the Cache.

[0051] First, some key terms in the present invention are explained:

[0052] 1. RDMA (Remote Direct Memory Access): Remote direct data access is a technology that allows network devices (such as RDMA network cards) to directly access the memory of another computer without the intervention of the operating system. It can reduce data processing delays in network transmission and improve data transmission efficiency.

[0053] 2. Cache: A memory that can perform high-speed data exchange. It is usually used to store frequently accessed data to reduce the number of accesses to slow storage (such as hard disks). It can increase data access speed and optimize system performance.

[0054] 3. SQ (Send Queue): The send queue in the RDMA protocol, used to store data or requests to be sent.

[0055] 4. RQ (Receive Queue): The receive queue in the RDMA protocol, used to store received data or responses.

[0056] 5. QP (Queue Pair): The combination of the sending queue and the receiving queue in the RDMA protocol is called a pair of QPs. As the basic unit of RDMA communication, it realizes data sending and receiving.

[0057] 6. QPN (Queue Pair Number): The number of a QP, which is used to uniquely identify different QPs. In RDMA communication, QPN can be used to determine the specific QP to which data should be sent.

[0058] 7. TX (Transmit): The sending side of the RDMA network card, used to send request and response messages.

[0059] 8. RX (Receive): The receiving side of the RDMA network card, used to receive request and response messages.

[0060] 9. Outstanding: It means that after initiating a request, you can continue to send the next request before receiving a response, which can improve the concurrency and throughput of RDMA communication.

[0061] 10. Outptr (Out Pointer): off-chip pointer, that is, unfinished pointer, used to identify the corresponding positions of different information in the request queue stored in the host memory, so as to quickly locate and process the requests in the host memory.

[0062] 11. PCIE (Peripheral Component Interconnect Express): The medium through which the RDMA Cache module accesses the host memory. It provides high-speed and reliable connections, enabling the RDMA Cache to efficiently access the host memory.

[0063] 12. SRAM (Static Random Access Memory): Static random access memory. The RDMA Cache module uses this unit to store request queue information to ensure that the RDMA Cache module can efficiently process request queue information.

[0064] 13. FIFO (First Input First Output): A first-in, first-out queue is a data structure that outputs data in the order in which it is input, to ensure that data is processed in the order in which it is input, to avoid data loss or disorder of order.

[0065] 14. CAM (Context Addressable Memory): Content-addressable memory is a type of memory that can quickly find matches based on content.

[0066] According to an embodiment of the present invention, a system implementation embodiment of an RDMA network card request queue is provided. Figure 3 is a structural diagram of an implementation system of an RDMA network card request queue according to an embodiment of the present invention, such as Figure 3 As shown, the system includes: an RDMA Cache module and a host memory module connected to each other, and the RDMA Cache module manages the Cache address (i.e. Figure 3 RAM addr in the cache address) and the free bits of the cache address (i.e. Figure 3 bitmap in), queue pair number (i.e. Figure 3 QPN in) and the unfinished pointer (i.e. Figure 3 outptr); the RDMACache module is used to execute the following method for implementing an RDMA network card request queue. The method includes:

[0067] When a write request is received, check whether there is any remaining space inside the RDMACache module;

[0068] If there is remaining space, the write information of the write request is written to the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated, and the queue pair number and unfinished pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written to the host memory module;

[0069] When a read request is received, check whether the queue pair number and the incomplete pointer carried by the read request match the historical records in the RDMACache module;

[0070] If there is a match, the storage data corresponding to the read request is read from the RDMA Cache module; if there is no match, the storage data corresponding to the read request is read from the host memory module.

[0071] In an optional implementation, the RDMACache module includes a control unit and an on-chip address mapping management unit, a first end of the control unit is connected to the on-chip address mapping management unit, a second end of the control unit is also connected to the host memory module, and the control unit includes a read control unit and a write control unit;

[0072] The write control unit is used to receive a write request and control a write operation, and the read control unit is used to receive a read request and control a read operation;

[0073] The on-chip address mapping management unit is used to manage the cache address, free bits of the cache address, queue pair number and incomplete pointer stored in the request queue, as well as the mapping relationship between the cache address, the queue pair number and the incomplete pointer, and is also used to store write information written to the RDMACache module (the on-chip address mapping management unit also includes an SRAM static random access memory, which is used to store write information written to the RDMACache module).

[0074] Furthermore, ram_data in the SRAM static random access memory is used to cache data content of each cache entry, such as data in the form of "infoX_of_qpY", where X represents the data number and Y represents the queue pair number (qp).

[0075] In an optional embodiment, the system further includes a read initiation module and a write initiation module; the read initiation module is connected to the input end of the read control unit via the read interface, and the write initiation module is connected to the input end of the write control unit via the write interface;

[0076] The read initiation module is used to initiate a read operation and send a read request to the read control unit; the write initiation module is used to initiate a write operation and send a write request to the write control unit.

[0077] Furthermore, when performing a write operation, the write initiation module initiates a write request to the write control unit through the write interface. The write control unit controls the logic of the write operation to ensure that the data is correctly written, and searches for an idle address in the chip, searches for an idle location in the RDMA Cache module to store new data, and writes the data to the idle address of the RDMA Cache module. The on-chip address mapping management unit manages the mapping relationship between the cache address and the queue pair number (Queue Pair Number, QPN) and the unfinished pointer (Outptr) of the host side queue.

[0078] When performing a read operation, the read initiation module initiates a read request to the read control unit through the read interface. The read control unit controls the logic of the read operation to ensure that the data is retrieved correctly. The read control unit searches for a match in the on-chip information of the RDMA Cache module and checks whether there is data matching the request in the RDMA Cache module. If so, the matching data is read from the RDMA Cache module.

[0079] In summary, this embodiment associates the queue pair number (QPN) in the RDMA network card with the unfinished pointer on the host side. By mapping the queue pair number and the unfinished pointer to the internal storage address of the Cache, multiple request queues can be effectively managed, thereby realizing that multiple QPs in the RDMA network card share the internal resources of the Cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the Cache. In addition, this embodiment avoids the defects of the traditional linked list management method that may cause performance bottlenecks and resource waste through the optimized data structure of the direct mapping mechanism, improves data access efficiency, and enables the Cache to respond to requests more efficiently. In addition, this embodiment processes read requests through outstanding. When the on-chip Cache does not hit, it immediately initiates a read request to the host memory module. While waiting for the host memory module to respond, it processes the next read request to achieve parallel processing. By processing read requests in parallel, the waiting time is reduced, the read throughput of the Cache is improved, and the overall delay caused by waiting for a single read request to be completed is reduced. This embodiment achieves efficient resource utilization by sharing cache resources and avoiding linked list management, improves cache read performance and overall throughput by outstandingly processing read requests, reduces management complexity and overhead, and improves system stability and reliability.

[0080] According to an embodiment of the present invention, an implementation method embodiment of an RDMA network card request queue is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0081] In this embodiment, a method for implementing an RDMA network card request queue is provided, which is applied to Figure 3 In the RDMACache module in the implementation system of the RDMA network card request queue shown, the system also includes a host memory module connected to the RDMACache module, and the RDMACache module manages the cache address stored in the request queue, the free bit of the cache address, the queue pair number and the unfinished pointer, Figure 4 is a flow chart of a method for implementing an RDMA network card request queue according to an embodiment of the present invention, such as Figure 4 As shown, the process includes the following steps:

[0082] Step S401: When a write request is received, check whether there is any remaining space inside the RDMACache module.

[0083] Furthermore, when the RDMA Cache module receives a write request, it first needs to determine whether there is enough space inside it to store the data of the write request. The RDMA Cache module is a cache area located on the RDMA network card, which is used to temporarily store data to reduce access to the host memory module, thereby improving data transmission efficiency. The purpose of this step is to determine whether the write request can be processed directly in the RDMA Cache module without sending it directly to the host memory module.

[0084] The RDMA Cache module is managed by the RDMA network card and related software (such as drivers), which uses special algorithms and data structures to optimize data transmission, such as the mapping mechanism of queue pair numbers (QPN) and unfinished pointers. When the RDMA network card receives a write request, if the RDMA Cache module has enough space, the data is stored in the RDMA Cache module; if the space in the RDMA Cache module is full, the data is directly written to the host memory module. Similarly, when a read request is received, it first checks whether there is the requested data in the RDMA Cache module. If so, it is read directly from the RDMA Cache module, otherwise it is read from the host memory module. The RDMA Cache module and the host memory module work together to support the data storage and access requirements of the computer system. By optimizing the data transmission mechanism, the overall performance and stability of the system can be improved. The host memory module is located on the computer motherboard and is the main area in the computer for temporary storage of data. It is directly connected to the CPU and is used to store running programs and data.

[0085] Step S402: If there is remaining space, the write information of the write request is written into the target free address of the RDMA Cache module, and the free bit corresponding to the target free address is updated, and the queue pair number and the unfinished pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written into the host memory module.

[0086] Furthermore, if the RDMA Cache module has free space, the write information of the write request (i.e., the data to be written) is stored in the specified free address (i.e., the target free address, which can be any free address), and the free state of this address is updated (marked as used), and the queue pair number (QueuePair Number, QPN) and the unfinished pointer (out pointer, combined with the queue pair number, used to determine the location of the corresponding request information stored in the cache or the host memory module) corresponding to this write request are recorded. If the RDMA Cache module does not have free space, the write information of the write request is directly stored in the host memory module to avoid delays caused by waiting for cache space.

[0087] Step S403: when a read request is received, check whether the queue pair number and the incomplete pointer carried in the read request match the historical records in the RDMA Cache module.

[0088] Furthermore, when the RDMA Cache module receives a read request, the RDMA Cache module needs to determine whether the data of this request is stored in the RDMA Cache module. This is achieved by checking whether the queue pair number and the incomplete pointer carried by the read request match the historical records in the RDMA Cache module. This step is to determine whether the read request can obtain data directly from the RDMA Cache module without obtaining it from the host memory module.

[0089] Step S404: if there is a match, then the storage data corresponding to the read request is read from the RDMACache module; if there is no match, then the storage data corresponding to the read request is read from the host memory module.

[0090] Furthermore, if the queue pair number and the incomplete pointer of the read request match the record in the RDMA Cache module, it means that the data of the read request has been cached in the RDMA Cache module, and the data can be read directly from the RDMA Cache module. If they do not match, it means that the data of the read request is not in the RDMA Cache module, and the data needs to be read from the host memory module. This embodiment can effectively manage multiple request queues and realize multi-QP sharing of cache resources by mapping the queue pair number of the request queue and the incomplete pointer on the host side to the internal storage address of the cache.

[0091] In this embodiment, the queue pair number (QPN) is a number used to uniquely identify each queue pair in the RDMA architecture. Each QP has a unique QPN so that the RDMA network card can accurately identify and process requests from different queue pairs. The incomplete pointer is used to enable the RDMACache module to determine the location of different request information in a single queue pair. As the request is completed, the corresponding pointer will be released and can be used to record new request information. In the RDMACache module of this embodiment, by mapping the queue pair number (QPN) and the incomplete pointer on the host side to the internal storage address of the Cache, effective management of multiple request queues can be achieved. The mapping mechanism of the on-chip address mapping management unit in the RDMA Cache module allows the RDMA network card to quickly locate the corresponding incomplete pointer according to the QPN when receiving a request, and check the status of the request. When multiple QPs send requests to the RDMA network card at the same time, the RDMA network card will store each request in different locations in the RDMA Cache module according to its QPN. Since each QP has a unique QPN, the RDMA network card can accurately identify and process requests from different QPs without confusion or conflict. That is, through the mapping mechanism of QPN and incomplete pointer, the RDMA Cache module can enable multiple QPs to share Cache resources.

[0092] In summary, this embodiment associates the queue pair number (QPN) in the RDMA network card with the unfinished pointer on the host side. By mapping the queue pair number and the unfinished pointer to the internal storage address of the Cache, multiple request queues can be effectively managed, thereby realizing that multiple QPs in the RDMA network card share the internal resources of the Cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the Cache. In addition, this embodiment avoids the defects of the traditional linked list management method that may cause performance bottlenecks and resource waste through the optimized data structure of the direct mapping mechanism, improves data access efficiency, and enables the Cache to respond to requests more efficiently. In addition, this embodiment processes read requests through outstanding. When the on-chip Cache does not hit, it immediately initiates a read request to the host memory module. While waiting for the host memory module to respond, it processes the next read request to achieve parallel processing. By processing read requests in parallel, the waiting time is reduced, the read throughput of the Cache is improved, and the overall delay caused by waiting for a single read request to be completed is reduced. This embodiment achieves efficient resource utilization by sharing cache resources and avoiding linked list management, improves cache read performance and overall throughput by outstandingly processing read requests, reduces management complexity and overhead, and improves system stability and reliability.

[0093] In this embodiment, another implementation method of the RDMA network card request queue is provided, which is applied to Figure 3 In the RDMA Cache module in the implementation system of the RDMA network card request queue shown, the system also includes a host memory module connected to the RDMACache module, and the RDMACache module manages the cache address stored in the request queue, the free bit of the cache address, the queue pair number and the unfinished pointer, Figure 5 FIG. 4 is a flowchart of another method for implementing an RDMA network card request queue according to an embodiment of the present invention. Figure 5 As shown, the process includes the following steps:

[0094] Step S501: when a write request is received, based on the free bits of the cache address, an address free bit query is performed on the RDMA Cache module to obtain the remaining space in the RDMA Cache module.

[0095] Furthermore, when the RDMA Cache module receives a write request, this embodiment first performs an address free bit query on the RDMA Cache module based on the free bits of each cache address in the RDMA Cache module (i.e., the bits marking whether the address has been used) to determine whether there is any remaining space in the RDMA Cache module for storing the write information of this write request.

[0096] Step S502: If there is remaining space, the write information of the write request is written into the target free address of the RDMA Cache module, and the free bit corresponding to the target free address is updated, and the queue pair number and the unfinished pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written into the host memory module.

[0097] Furthermore, step S502 includes:

[0098] If there is remaining space in the RDMA Cache module, a target free address is selected from the free address bits of the RDMA Cache module;

[0099] Writing the write information of the write request into the target idle address, and updating the address valid position of the target idle address to a non-idle state;

[0100] The queue pair number and the incomplete pointer corresponding to the write request are recorded and associated with the target idle address.

[0101] Furthermore, if there is remaining space in the SRAM static random access memory of the RDMA Cache module, a target free address is selected from the free bits of the RDMA Cache module address. These addresses have never been occupied before, or have been released after being occupied, and can now be used to store new data. The write control unit in the RDMA Cache module writes the write information of the write request (i.e., the data to be stored) to the selected target free address. After the write operation is completed, the on-chip address mapping management unit in the RDMA Cache module updates the address valid bit (or free bit) of the target free address to a non-free state to indicate that the address is now occupied, and records the queue pair number and the incomplete pointer corresponding to the current write request, and associates them with the target free address. The queue pair number is used to identify a specific request queue, and the incomplete pointer is used to track the unfinished operations in the request queue. If there is no remaining space in the RDMA Cache module, the write control unit in the RDMA Cache module will not write data to the RDMA Cache module. Instead, it will write the write information of the write request directly to the host memory module to avoid data loss or overwriting and ensure that the data can be correctly accessed when needed. The address free bit is an important data structure used in the on-chip address mapping management unit of the RDMA Cache module to track the occupancy status of the SRAM static random memory. The system needs to update these bits regularly to ensure that they reflect the actual status of the SRAM static random memory. The queue pair number allows the system to identify a specific data transmission queue, and the incomplete pointer helps the system track the operations that have not been completed in the queue, thereby ensuring the correctness and integrity of the data.

[0102] For further information, see Figure 6The flowchart of the write operation implementation method shown in the figure shows that after the RDMACache module receives a write request, if there is remaining space inside the Cache of the RDMACache module (i.e., SRAM static random access memory), then by querying the address free bits, one of the free addresses is selected, and the information to be written is written to the found free address, and the address valid position of the corresponding bit is updated to non-space "i.e., 0", and the corresponding QPN and Outptr are recorded; if there is no remaining space inside the Cache, the information to be written is written to the host memory module. Whether the current write request can be written to the Cache depends only on whether there is remaining space inside the Cache, and is not affected by whether the previous write request was written to the Cache, thereby maximizing the use of the internal resources of the Cache and avoiding access to the main memory module as much as possible. That is, after receiving a write request, the RDMA Cache module first checks whether there is free space inside the RDMA Cache module. If there is free space inside the Cache (i.e., SRAM), the address free bits of the Cache are queried to find available free addresses, and a target free address is selected from the free bits for writing data. The information to be written is written to this free address, and the address valid bit of the corresponding free address is set to a non-free state (usually set to 0), indicating that the address is occupied, and the corresponding queue pair number (QPN) and incomplete pointer (Outptr) are recorded so that the data can be tracked and accessed in the future. If there is no free space inside the Cache, the data cannot be written to the Cache, so the data needs to be written directly to the host memory. Whether the current write request can be written to the Cache depends only on whether there is free space inside the Cache, and is not affected by whether the previous write request was written to the Cache. That is, each write request is considered independently, so that the cache resources can be maximized.

[0103] Step S503, when a read request is received, extract the queue pair number and the incomplete pointer carried by the read request; determine whether the queue pair number and the incomplete pointer carried by the read request match the historical records corresponding to the target cache address in the RDMACache module, and at the same time determine whether the target cache address is in a non-idle state.

[0104] Furthermore, when the RDMA Cache module receives a read request, the read control unit extracts the queue pair number (QPN) and the incomplete pointer (Outptr) carried in the request, and checks whether the queue pair number (QPN) and the incomplete pointer (Outptr) match the historical record of a target cache address stored in the RDMA Cache module. At the same time, it also checks whether the target cache address is in a non-free state, that is, whether the address has been occupied and stored with data.

[0105] Step S504: If there is a match, and the matched target cache address is in a non-idle state, it is determined that a cache hit occurs, and the storage data corresponding to the read request is read from the target cache address.

[0106] Furthermore, if the information in the read request matches the historical record of a target cache address in the RDMA Cache, and the target cache address is in a non-idle state, the read control unit determines that it is a cache hit. In this case, the read control unit will directly read the storage data corresponding to the read request from the target cache address without accessing the host memory module.

[0107] Step S505, if there is no match, or the matched target cache address is in an idle state, it is determined that the cache does not hit, and a read request is initiated to the host memory module to read the storage data corresponding to the read request; while waiting for the host memory module to respond, the next read request is processed to realize parallel processing of multiple read requests.

[0108] Furthermore, if the information in the read request does not match the historical record of any cache address in the RDMA Cache module, or the matched target cache address is in an idle state, it is determined as a cache miss. In the case of a cache miss, the read control unit needs to initiate a new read request to the host memory module to read the storage data corresponding to the read request. While waiting for the host memory module to respond, in order to improve efficiency, the read control unit can process the next read request in parallel. This method of parallel processing of multiple read requests can significantly reduce the total waiting time and improve the system throughput.

[0109] For further information, see Figure 7The flowchart of the read operation implementation method shown in the figure shows that after receiving the read request, the RDMACache module determines whether the queue pair number QPN and the incomplete pointer Outptr provided by the read initiation module match the information stored at a certain address inside the Cache, and at the same time determines whether the corresponding address is non-space. If there is an address match and the corresponding address is non-free, that is, the Cache hits, the corresponding address is recorded; otherwise, that is, the Cache misses, a read request is initiated to the host, and the query miss information is stored in the read direction record FIFO, and then the next query is continued. That is, when the RDMACache module receives a read request, the read request usually contains queue pair number (QPN, Queue PairNumber) and incomplete pointer (Outptr). The RDMA Cache module then checks whether the QPN and Outptr in the read request match the information stored at a certain address inside the Cache. At the same time, the RDMA Cache module also checks whether the corresponding address is non-space, that is, whether the address is occupied by valid data. If a matching address is found and the address is non-space, it is considered that the Cache hits. At this time, the RDMA Cache module will record the corresponding cache address so that data can be read from this address later. If no matching address is found, or the found address is free (that is, not occupied), then the cache is considered to be a miss. In this case, the read control unit in the RDMA Cache module needs to initiate a read request to the host to obtain the required data from the host memory module.

[0110] Step S506, after each matching query, the query hit result is recorded in the read direction record FIFO of the RDMA Cache module; when the read direction record FIFO is not empty, a data reading path is selected according to the record information in the read direction record FIFO; the data reading path includes reading the storage data corresponding to the read request from the RDMA Cache module and reading the storage data corresponding to the read request from the host memory module.

[0111] Further, such as Figure 7As shown, when the read direction record FIFO is not empty, according to the previously recorded cache hit information, it is selected whether to read the SRAM according to the address recorded in the "SRAM read address FIFO" or read the "read host memory data cache FIFO", and finally the selected data is output to the read initiation module, and the processes such as judging whether the queue pair number QPN and the unfinished pointer Outptr match, reading the SRAM and initiating a read request to the host all support outstanding. In other words, regardless of whether the cache hits or not, the RDMA Cache module will store the query result (whether it hits or not) in a read direction record FIFO (FirstIn First Out). The read direction record FIFO is used to record the results of each query so that the data source from which to read data can be determined based on these results later. When the read direction record FIFO is not empty, the RDMACache module will decide the next operation based on the previously recorded cache hit information. If the cache hits, the RDMACache module will read the previously recorded cache address from the "SRAM read address FIFO" and read data from the address (that is, the storage data corresponding to the read request is read from the RDMACache module above). If the cache does not hit, the RDMACache module will read data from the "read host memory data cache FIFO" (that is, the storage data corresponding to the read request is read from the host memory module above).

[0112] Furthermore, this embodiment adopts a method of combining the queue pair number with the unfinished pointer on the host side (implemented by a mapping table in the on-chip address mapping management unit, the mapping table includes a mapping relationship between the cache address, the queue pair number and the unfinished pointer) to map the cache internal storage address, that is, the cache address where the request queue is stored, so as to realize that multiple QPs share the cache internal resources. The method of combining the queue pair number with the unfinished pointer on the host side means that each QP in this embodiment has an unfinished pointer associated with it, and the unfinished pointer points to the location of the current operation of the QP in the host memory module. The RDMA Cache module uses the combination of the queue pair number and the unfinished pointer as a key value to map to the storage address inside the cache. The implementation method is as follows: when a QP initiates a write operation, its queue pair number and unfinished pointer will be used to determine a target free address in the RDMACache module. The written data will be stored in this target free address of the RDMA Cache module, and the state of the target free address will be updated to a non-free state. When another QP initiates a read operation, its queue pair number and unfinished pointer will also be used to find the corresponding address in the RDMACache module.

[0113] In summary, this embodiment associates the queue pair number (QPN) in the RDMA network card with the unfinished pointer on the host side. By mapping the queue pair number and the unfinished pointer to the internal storage address of the Cache, multiple request queues can be effectively managed, thereby realizing that multiple QPs in the RDMA network card share the internal resources of the Cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the Cache. In addition, this embodiment avoids the defects of the traditional linked list management method that may cause performance bottlenecks and resource waste through the optimized data structure of the direct mapping mechanism, improves data access efficiency, and enables the Cache to respond to requests more efficiently. In addition, this embodiment processes read requests through outstanding. When the on-chip Cache does not hit, it immediately initiates a read request to the host memory module. While waiting for the host memory module to respond, it processes the next read request to achieve parallel processing. By processing read requests in parallel, the waiting time is reduced, the read throughput of the Cache is improved, and the overall delay caused by waiting for a single read request to be completed is reduced. This embodiment achieves efficient resource utilization by sharing cache resources and avoiding linked list management, improves cache read performance and overall throughput by outstandingly processing read requests, reduces management complexity and overhead, and improves system stability and reliability.

[0114] See also Figure 8 , Figure 8 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 8 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0115] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0116] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0117] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0118] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0119] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0120] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0121] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0122] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. A method for implementing an RDMA network card request queue, characterized in that: The method is applied to an RDMACache module in an implementation system of an RDMA network card request queue, the system further comprising a host memory module connected to the RDMA Cache module, the RDMA Cache module managing a cache address stored in the request queue, a free bit of the cache address, a queue pair number and an unfinished pointer, and the method comprises: When receiving a write request, checking whether there is any remaining space inside the RDMACache module; If there is remaining space, the write information of the write request is written into the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated, and the queue pair number and the unfinished pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written into the host memory module; When a read request is received, checking whether the queue pair number and the incomplete pointer carried by the read request match the historical records in the RDMACache module; If there is a match, the storage data corresponding to the read request is read from the RDMACache module; if there is no match, the storage data corresponding to the read request is read from the host memory module.

2. The method according to claim 1, characterized in that When receiving a write request, checking whether there is any remaining space inside the RDMACache module includes: When a write request is received, an address free bit query is performed on the RDMA Cache module based on the free bits of the Cache address to obtain the remaining space in the RDMA Cache module.

3. The method according to claim 2, characterized in that If there is remaining space, the write information of the write request is written into the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated, and the queue pair number and the unfinished pointer corresponding to the write request are recorded, including: If there is remaining space in the RDMA Cache module, selecting a target free address from the free address bits of the RDMA Cache module; Writing the write information of the write request into the target idle address, and updating the address valid position of the target idle address to a non-idle state; The queue pair number and the incomplete pointer corresponding to the write request are recorded and associated with the target idle address.

4. The method according to claim 3, characterized in that When receiving a read request, checking whether the queue pair number and the incomplete pointer carried by the read request match the historical records in the RDMACache module includes: When a read request is received, extracting the queue pair number and the unfinished pointer carried by the read request; It is determined whether the queue pair number and the incomplete pointer carried by the read request match the historical record corresponding to the target cache address in the RDMACache module, and at the same time it is determined whether the target cache address is in a non-idle state.

5. The method according to claim 4, characterized in that If there is a match, reading the storage data corresponding to the read request from the RDMA Cache module includes: If there is a match, and the matched target cache address is in a non-idle state, a cache hit is determined, and the storage data corresponding to the read request is read from the target cache address.

6. The method according to claim 5, characterized in that If there is no match, reading the storage data corresponding to the read request from the host memory module, including: If there is no match, or the matched target Cache address is in an idle state, it is determined that the Cache does not hit, and a read request is initiated to the host memory module to read the storage data corresponding to the read request; While waiting for the host memory module to respond, the next read request is processed to achieve parallel processing of multiple read requests.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: After each matching query, the query hit result is recorded in the read direction record FIFO of the RDMACache module; When the read direction record FIFO is not empty, a data reading path is selected according to the record information in the read direction record FIFO; the data reading path includes reading the storage data corresponding to the read request from the RDMACache module and reading the storage data corresponding to the read request from the host memory module.

8. A system for implementing an RDMA network card request queue, characterized in that: The system comprises: an RDMACache module and a host memory module connected to each other, wherein the RDMACache module manages the cache address stored in the request queue, the free bit of the cache address, the queue pair number and the unfinished pointer; The RDMACache module is used to execute the method for implementing an RDMA network card request queue according to any one of claims 1 to 7.

9. The system according to claim 8, characterized in that The RDMACache module includes a control unit and an on-chip address mapping management unit, a first end of the control unit is connected to the on-chip address mapping management unit, a second end of the control unit is also connected to the host memory module, and the control unit includes a read control unit and a write control unit; The write control unit is used to receive a write request and control a write operation, and the read control unit is used to receive a read request and control a read operation; The on-chip address mapping management unit is used to manage the cache address, free bits of the cache address, queue pair number and incomplete pointer stored in the request queue, as well as the mapping relationship between the cache address, the queue pair number and the incomplete pointer, and is also used to store write information written to the RDMA Cache module.

10. The system according to claim 9, characterized in that The system further comprises a read initiation module and a write initiation module; the read initiation module is connected to the input end of the read control unit via a read interface, and the write initiation module is connected to the input end of the write control unit via a write interface; The read initiation module is used to start a read operation and send a read request to the read control unit; the write initiation module is used to start a write operation and send a write request to the write control unit.

11. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method for implementing an RDMA network card request queue according to any one of claims 1 to 7 by executing the computer instructions.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute a method for implementing an RDMA network card request queue as described in any one of claims 1 to 7.

13. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute a method for implementing an RDMA network card request queue according to any one of claims 1 to 7.

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