High-dielectric-coefficient super-junction MOSFET structure optimization method

Abstract

The invention belongs to the technical field of power semiconductor devices, and particularly provides a method for optimizing a high-dielectric-coefficient super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. Firstly, a coordinate system is established, a Poisson equation and boundary conditions are listed, Taylor expansion potential is used at the boundary, electric field expressions of a semiconductor region and a high-dielectric-coefficient insulating medium region are solved, and an optimization objective function and constraint conditions are constructed with the depth-to-width ratio and the dielectric coefficient ratio as optimization parameters and the minimum ratio on resistance as the target; then, according to the constraint condition, obtaining a numerical solution of the target function by adopting a dimension reduction method, and obtaining a polynomial fitting expression through polynomial fitting; and finally, according to a polynomial fitting expression of the target function, calculating to obtain an optimal value of the depth-to-width ratio. On the basis of the depth-to-width ratio, the dielectric coefficient entering the high-dielectric-coefficient insulating medium serves as a design parameter, a fitting empirical expression is provided, the optimization method of the Hk super junction structure is effectively simplified, the calculation amount is reduced, and the efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and specifically provides a method for optimizing a high dielectric constant super junction MOSFET structure. Background Art

[0002] In power semiconductor devices, the superjunction structure breaks through the silicon limit problem (R on,sp ∝BV 2.5 ). Traditional superjunction structures such as Figure 1 As shown in (a), the charge neutralization effect generated by the alternation of p-pillars and n-pillars is used to absorb the electric field laterally, so that part of the electric field lines that originally entered the channel longitudinally through the n-pillars are changed to enter the p-pillars laterally and then return to the channel, thereby reducing the longitudinal component of the electric field and reducing the peak intensity of the electric field. Therefore, under the same breakdown voltage (Breakdown Voltage, BV), compared with the traditional voltage-resistant layer, the superjunction structure can obtain a lower specific on-resistance (Specific ON-Resistor, Ron, sp) by increasing the doping concentration. However, it is difficult to achieve a perfect doping balance between the n-pillar and the p-pillar in the superjunction structure in actual manufacturing. There are also other obvious problems, mainly the JFET (Junction-Field-Effect Transitor) effect. The JFET effect is due to the formation of a depletion layer at the junction of the n-pillar and the p-pillar, which leads to a depletion region of a certain width in the n-pillar, reducing the effective conduction area.

[0003] In view of the above problems, the literature "X. Chen and M. Huang, "A Vertical Power MOSFET With an Interdigitated Drift Region Using High-k Insulator", IEEE Transactions on Electron Devices, vol. 59, no. 9, pp. 2430–2437, Sep. 2012" proposed a high dielectric constant insulating dielectric superjunction structure, such as Figure 1As shown in (b), this structure replaces the p-column in the traditional superjunction with a high dielectric constant insulating material, which can also achieve the purpose of lateral absorption of the electric field and solve the problems that arise in the traditional superjunction. Furthermore, the literature "H. Huang et al., "Optimization and Comparison of Drift Region Specific ON-Resistance for Vertical Power Hk MOSFETs and SJ MOSFETs With Identical Aspect Ratio," IEEE Transactions on Electron Devices, vol. 67, no. 6, pp. 2463–2470, Jun. 2020." first used the aspect ratio (AR) as a design parameter and proposed a Matlab-based on-resistance optimization method; however, in the prior art, the optimization process is relatively cumbersome, and the dielectric constant ratio (K r ) as optimization design parameters and provide empirical expressions to guide the optimization design. Summary of the invention

[0004] The purpose of the present invention is to provide a high dielectric constant super structure optimization method, based on the aspect ratio (AR), the dielectric constant of the high dielectric constant insulating medium is introduced as a design parameter to obtain the dielectric constant ratio (K r ), providing specific on-resistance with respect to aspect ratio (AR) and dielectric constant ratio (K r ) is fitted with an empirical expression, which effectively simplifies the optimization method of the Hk superjunction structure, reduces the amount of calculation and improves efficiency.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] A high dielectric constant super structure optimization method, characterized by comprising the following steps:

[0007] Step 1. Establish a coordinate system and list the Poisson equation and boundary conditions. Use Taylor expansion potential at the boundary to solve the electric field expression of the semiconductor region and the high dielectric constant insulating medium region.

[0008] Step 2. Based on the electric field expressions of the semiconductor region and the high dielectric constant insulating dielectric region, the aspect ratio (AR) and dielectric constant ratio (K r ) is the optimization parameter, and the optimization objective function and constraint conditions are constructed with the goal of minimizing the specific on-resistance;

[0009] Step 3. According to the constraints, the dimensionality reduction method is used to obtain the numerical solution of the objective function;

[0010] Step 4. Perform polynomial fitting on the numerical solution of the objective function to obtain a polynomial fitting expression of the objective function;

[0011] Step 5. According to the polynomial fitting expression of the objective function, the optimized value of the aspect ratio and the dielectric constant ratio is calculated.

[0012] Furthermore, in step 1, the electric field expression E in the semiconductor region is Sy (x,y) is:

[0013]

[0014] The electric field expression E in the high dielectric constant insulating medium region Iy (x,y) is:

[0015]

[0016] Where (x, y) represents the coordinates, a is the width of the n-type semiconductor region, W is the depth of the drift region, and BV is the reverse breakdown voltage;

[0017] V e , T c , T d , T e is the parameter symbol, K r is the dielectric constant ratio; q is the unit charge, N D is the impurity doping concentration of the n-type semiconductor region, ε S is the dielectric constant of silicon, b is the width of the high dielectric constant dielectric region, ε I is the dielectric constant of the insulating medium region;

[0018]

[0019] Furthermore, in step 2, the objective function is:

[0020]

[0021] Among them, R on,sp (AR,K r ) represents the ratio of AR and K r is the design parameter of on-resistance, AR represents the aspect ratio, K r Indicates the dielectric constant ratio; W(AR,K r ) represents the ratio of AR and K r is the drift zone depth of the design parameter, N D (AR,K r ) is based on AR and K ris the doping concentration of the n-type semiconductor region of the design parameter, μ n (AR,K r ) represents the ratio of AR and K r is the electron mobility of the design parameter; q represents the unit charge, and a is the width of the n-type semiconductor region.

[0022] Furthermore, in step 2, the first constraint condition is critical exhaustion, which is specifically expressed as:

[0023] E Sy (x,y)=0,x=-a,y=0

[0024] Among them, (x, y) represents the coordinates, E Sy (x, y) represents the electric field in the y direction of the semiconductor region, and a is the width of the n-type semiconductor region;

[0025] The second constraint is critical breakdown, which is specifically expressed as:

[0026]

[0027] Among them, I n represents the ionization integral, α n With α p represent the impact ionization rates of electrons and holes, respectively.

[0028] Furthermore, in step 3, the specific process of the dimensionality reduction method is:

[0029] At the symmetry axis of the semiconductor region, the electric field strength is simplified as:

[0030] E Sy (x,y)=f1(BV,K r ,a,AR,b,W,N D ,y),x=-a

[0031] Among them, (x, y) represents the coordinates, E Sy (x, y) represents the electric field in the y direction of the semiconductor region, a is the width of the n-type semiconductor region; BV is the reverse breakdown voltage; K r is the dielectric constant ratio, a and b are the widths of the semiconductor region and the high dielectric constant insulating medium region, AR is the aspect ratio, W is the depth of the drift region, N D is the doping concentration of the semiconductor region;

[0032] according to The above electric field strength expression is reduced to:

[0033] E Sy (x,y)=f2(BV,K r ,a,AR,W,N D ,y),x=-a

[0034] Using exhaustive method to give BV, K r , a and AR, the above electric field intensity expression is reduced to:

[0035] E Sy (x,y)=f3(W,N D ,y),x=-a

[0036] According to the first constraint, E Sy (x,y)=f3(W,N D ,0)=0,x=-a; use Newton iteration method to solve, and change the doping concentration N D The drift zone depth W is expressed as N D =g(W); It should be noted that f1, f2, f3, and g all represent function symbols in the dimensionality reduction process;

[0037] According to the second constraint, I n (W) = 1, I n (W) represents the ionization integral along the symmetry line of the semiconductor region; Newton iteration method is used to solve the optimized drift region depth W (opt) ;

[0038] According to N D = g(W), to obtain the optimized doping concentration According to the Caughey Thomas model, the optimized electron mobility is obtained Then the optimized specific on-resistance R is calculated. on,sp(opt) :

[0039]

[0040] Furthermore, in step 4, the polynomial fitting expression of the objective function is:

[0041] γ(σ,θ)=p 00 +p 10 σ+p 01 θ+p 20 σ 2 +p 11 σθ+p 02 θ 2 +p 30 σ 3 +p 21 σ 2 θ+p 12 σθ 2 +p 03 θ 3 +p 31 σ 3 θ+p 22 σ2 θ 2 +p 13 σθ 3 +p 04 θ 4

[0042] Where, σ = logAR, θ = logK r ,γ=logR on,sp(opt) , R on,sp(opt) is the numerical solution of the objective function, AR is the aspect ratio, K r is the dielectric constant ratio; p ij are polynomial coefficients, i represents the power of σ, and j represents the power of θ.

[0043] Furthermore, in step 5, the specific process is:

[0044] Derivative the polynomial fitting expression of the objective function:

[0045]

[0046] The dielectric constant ratio K is calculated based on the selected high dielectric constant insulating medium r ,Depend on The optimal value of σ obtained by calculation is the optimal value of the aspect ratio AR.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] The present invention provides a highly efficient optimization method for Hk superjunction structure, which is applicable to such superjunction structure under any application conditions and can be extended to multiple design parameters; the present invention obtains all optimized design parameters through an objective function and two constraints, solves the electric field expression through Taylor series expansion, greatly reduces the amount of calculation, and optimizes the design parameters of the same amount of data, and the time consumption is only 12.69% of the traditional Fourier series electric field expression; and the present invention is aimed at the aspect ratio AR and the dielectric constant K r By giving a specific polynomial empirical expression, the local design merit and the most appropriate K for AR can be quickly obtained. r Get the value. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Schematic diagram of the super junction MOSFET structure, where (a) is the traditional super junction structure, (b) is the Hk super junction structure, and (c) is the half-unit structure of the Hk super junction.

[0050] Figure 2 Result diagram of the electric field intensity component in the y direction distributed along AA' in the half-unit structure of the Hk super junction in an embodiment of the present invention.

[0051] Figure 3 1 is a diagram showing an error in the y-direction electric field intensity component along AA′ in a half-unit structure of an Hk super junction according to an embodiment of the present invention.

[0052] Figure 4 1 is a graph showing the relationship between the maximum error of the electric field intensity component in the y direction distributed along AA′ and the width a of the semiconductor region in the half-unit structure of the Hk super junction in an embodiment of the present invention.

[0053] Figure 5 is the R of the Hk super junction structure in the embodiment of the present invention on,sp(opt) (AR,K r )Result graph.

[0054] Figure 6 is the R of the Hk super junction structure in the embodiment of the present invention on,sp(opt) (AR,K r ) Polynomial fit to three-dimensional graph.

[0055] Figure 7 is the R of the Hk super junction structure in the embodiment of the present invention on,sp(opt) (AR)Relationship diagram.

[0056] Figure 8 is the R of the Hk super junction structure in the embodiment of the present invention on,sp(opt) (K r )relationship diagram.

[0057] Fig. 9 This is a diagram of AR optimization results obtained when the Hk super junction structure in an embodiment of the present invention is given a high dielectric constant insulating medium. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0059] This embodiment provides a high dielectric constant super junction structure optimization method, comprising the following steps:

[0060] Step 1. Establish a coordinate system and list the Poisson equation and boundary conditions. Use Taylor expansion potential at the boundary to solve the electric field expression of the semiconductor region and the high dielectric constant insulating medium region.

[0061] Step 1.1 Establish a coordinate system and list the Poisson equation and boundary conditions for the n-type semiconductor region and the high dielectric constant insulating medium region respectively;

[0062] Establish as Figure 1 In the coordinate system shown in (c), the y-axis is established at the junction of the n-type semiconductor region and the high-k dielectric region, and the x-axis is established at the junction of the n-type semiconductor region, the high-k dielectric region and the drain heavily doped N-type region; the Poisson equation is listed as:

[0063] n-type semiconductor region:

[0064] High dielectric constant insulating medium area:

[0065] Among them, V S and V I are the potential distribution functions of the n-type semiconductor region and the high dielectric constant insulating medium region, respectively. The subscript S represents semiconductor, and the subscript I represents insulator; N D is the impurity doping concentration of the n-type semiconductor region, q is the unit charge, ε S is the dielectric constant of silicon; x and y are coordinate variables;

[0066] The boundary conditions are:

[0067] 1) BV is the reverse breakdown voltage; the present invention defines the potential of the bottom plane as BV / 2, and the n region is completely depleted under the reverse bias voltage BV;

[0068] 2) W is the depth of the drift region; the top plane is an equipotential surface, the reverse bias voltage applied between the bottom plane and the top plane is BV, and the potential of the bottom plane is BV / 2;

[0069] 3) a is the width of the n-type semiconductor region, and b is the width of the high-k dielectric region; Figure 1 (c) shows a half-unit structure of a Hk superjunction, where x=-a and x=b correspond to two symmetry lines in the actual structure;

[0070] 4) V S (x=0)=V I (x=0), taking a differential unit as an example, that is, Figure 1 Using Stokes' theorem around the edge of the inserted rectangle in (c), we can see that E Sy Δy-E Iy Δy+E x (y+Δy)-E x (y)Δx=0, E is the electric field, subscripts x and y represent the components along the x-axis and y-axis respectively, subscripts S and I refer to the semiconductor region and the insulator region respectively, Δx and Δy represent the differential units along the x-axis and y-axis respectively; assuming that Δy is a first-order infinitesimal value and Δx is a second-order infinitesimal value, that is, Δy→0 and Δx<<Δy; E x The relevant terms of and can be omitted; therefore, we can get E Sy =EIy , E Sy and E Iy The integrals from the bottom along x = 0 show that V S (x=0)=V I (x=0);

[0071] 5) ε I is the dielectric constant of the insulating medium region; using Gauss’s theorem on the closed loop formed by the differential unit, we can get D Ix Δy-D Sx Δy+D y (y+Δy)Δx-D y (y)Δx=Q SS Δy, D is the electrical mobility, Q SS is the charge density of the interface state; assuming Δ<<Δy, we can get D Ix -D Sx =Q SS ; Q is ignored in the present invention SS , because D Ix =ε I E Ix ,D Sx =ε S E Sx , we can get the boundary condition

[0072] Step 1.2 Taylor expands the electric potential at the boundary of the half-unit structure to obtain the electric potential expression between the n-type semiconductor region and the high dielectric constant insulating medium region;

[0073] For an n-type semiconductor region, the Taylor expansion of the potential at x = -a is:

[0074]

[0075] For the high dielectric constant insulating medium region, the Taylor expansion of the potential at x = b is:

[0076]

[0077] Step 1.3 solves the electric potential expression of the n-type semiconductor region and the high dielectric constant insulating medium region by the substitution method, and then calculates the y-direction electric field analytical expression of the n-type semiconductor region and the high dielectric constant insulating medium region;

[0078] By using the substitution method, the potential of the semiconductor region is solved as follows:

[0079]

[0080] Then the electric field in the semiconductor region in the y direction is:

[0081]

[0082] High dielectric constant insulating dielectric region potential:

[0083]

[0084] Then the electric field in the y direction of the high dielectric constant insulating medium region is:

[0085]

[0086] Where BV is the reverse breakdown voltage; a and b are the widths of the semiconductor region and the high-k dielectric region, respectively; V e , T c , T d , T e is the parameter symbol,

[0087] Since only AA' is considered when optimizing the specific on-resistance, the present invention proposes a further approximately optimized semiconductor region y-direction electric field at AA':

[0088]

[0089] In order to demonstrate the accuracy of the above electric field analytical expression in the present invention, this embodiment compares the simulation results, the calculation results of the traditional method and the calculation results of this embodiment; when BV = 1000V, K r =100, AR=20, a=b=2μm, N D =1×10 16 cm -3 When the electric field intensity component in the y direction along AA' is obtained, Figure 2 shown; according to The error between the calculated and simulated results, E Sy,precise The y-direction electric field intensity component of the distribution along AA' obtained by the Fourier series method is relatively accurate; the results show that the maximum error of the y-direction electric field intensity component of the distribution along AA' obtained by the present invention is less than 4%; the maximum error after further approximate optimization is less than 3%, such as Figure 3 As shown, it is shown that the feasibility and accuracy of the method based on Taylor expansion of the present invention;

[0090] Furthermore, the width a of the n-type semiconductor region is set as a variable, and the error result of the electric field intensity component in the y direction along the distribution of AA' is as follows: Figure 4As shown, the variation range of a is 1 to 10 μm (the typical value of a is 3 to 5 μm). The results show that the maximum error between the present invention and the traditional method is only about 6.7% when a is 10 μm, while in the typical values, the error is less than 5%; the maximum error of the Taylor series solution after further approximation optimization within 1 to 10 μm is less than 5%, indicating that the present invention has a wide range of application;

[0091] Step 2: Based on the electric field expressions of the semiconductor region and the high dielectric constant insulating dielectric region, the aspect ratio (AR) and dielectric constant ratio (K r ) is the optimization parameter, and the optimization objective function and constraint conditions are constructed with the goal of minimizing the specific on-resistance;

[0092] Step 2.1 construct the objective function;

[0093] The present invention is arranged to obtain a smaller specific on-resistance R at a given breakdown voltage BV. on,sp To optimize the target, the aspect ratio AR and dielectric constant ratio K r As the parameters of the optimization design, they are used to characterize the process difficulty during production and the selection of high dielectric constant insulating medium materials. Based on the above conditions, the following objective function is constructed:

[0094]

[0095] Among them, R on,sp (AR,K r ) represents the ratio of AR and K r is the design parameter of on-resistance, AR represents the aspect ratio, K r Indicates the dielectric constant ratio; W(AR,K r ) represents the ratio of AR and K r is the depth of the drift region of the design parameter (i.e., the depth of the n column and the Hk column in the Hk super junction structure), n D (AR,K r ) is based on AR and K r is the doping concentration of the n-type semiconductor region of the design parameter, μ n (AR,K r ) represents the ratio of AR and K r is the electron mobility of the design parameter; q represents the unit charge, a is the width of the n-type semiconductor region, and b is the width of the high dielectric constant dielectric region;

[0096] Step 2.2: Construct the first constraint: critical exhaustion;

[0097] According to the depletion process of the Hk superjunction as the voltage increases when the reverse bias voltage is applied, it can be known that A' is the last depletion point in the entire Hk superjunction device; assuming that the device is critically depleted when the reverse bias voltage BV is applied, then:

[0098] E Sy (x,y)=0,x=-a,y=0

[0099] Step 2.3 construct the second constraint: critical breakdown;

[0100] AA' is the path most prone to breakdown. The more accurate Chynoweth model in avalanche breakdown is considered to calculate the impact ionization integral. The formula is as follows:

[0101]

[0102] Among them, I n represents the ionization integral (subscript n represents electrons), α n and α p denote the impact ionization rates of electrons and holes, respectively (the subscripts n and p represent electrons and holes, respectively), and W and y are independent variables;

[0103]

[0104] Among them, a n and b n is the coefficient in the electron impact ionization rate, a n =7.03×105cm -1 , b n =9.566×105cm -1 ; a p and b p is the coefficient in the hole impact ionization rate, a p =1.528×106cm -1 , b p =1.582×106cm -1 ;

[0105] Step 3. According to the constraints, the dimensionality reduction method is used to obtain the numerical solution of the objective function;

[0106] The design parameters of the Hk superjunction device are known to include BV, K r ,a,AR,b,W,N D , R on ; BV is the breakdown voltage; K r is the ratio of the dielectric constants of the high-k dielectric to the dielectric constants of the semiconductor region; a and b are the widths of the semiconductor region and the high-k dielectric region, respectively; AR is the aspect ratio; W is the depth of the drift region; N D is the impurity doping concentration of the semiconductor region; R on is the specific on-resistance of the Hk super junction device;

[0107] At AA', the electric field strength relationship can be expressed as: E Sy(-a,y)=f1(BV,K r ,a,AR,b,W,N D ,y), since there is a known relationship between the three parameters AR, W and b, that is, Knowing two of them, we can find the other one, so the electric field relationship can be simplified to E Sy (-a,y)=f2(BV,K r ,a,AR,W,N D ,y); using exhaustive method to give BV, K r , a and AR (that is, they are known), the electric field relationship is only related to W, N D Related to y, it can be expressed as E Sy (-a,y)=f3(W,N D ,y);

[0108] At this time, according to the first constraint, the n-column drift region is critically depleted, and the electric field strength at A' is 0. Sy (-a,0)=f3(W,N D ,0)=0; use Matlab built-in fzero function (Newton iteration method) to solve; thus, the doping concentration N D The drift zone depth W is used to represent the relationship N D = g(W);

[0109] According to the second constraint, the impact ionization integral along AA' is 1, that is, I n (W) = 1, use Matlab's built-in fzero function (Newton iteration method) to solve the optimized drift zone depth W (opt) ; In the solution process, the minimum depth W under the most ideal electric field distribution (rectangular electric field) can be considered min The maximum depth W obtained under the worst electric field distribution (triangular electric field) pp , using W min and W pp Provide upper and lower limits for the fzero function evaluation interval to make calculations faster;

[0110] The W (opt) Back-carry N D = g(W), to obtain the optimized doping concentration At this time, according to R on With W, N D The optimized specific on-resistance is calculated based on the known relationship of Among them, μ n The CaugheyThomas model is used for accurate calculation, namely:

[0111]

[0112] Among them, μ max represents the maximum mobility within the concentration range considered, μ max =55.24cm 2 ·V -1 ·s -1 ;μ min represents the minimum mobility within the concentration range considered, μ min =1429.23cm 2 ·V -1 ·s -1 ; N ref The reference doping concentration for the intermediate mobility, N ref =1.072×10 17 cm -3 ; β represents the doping dependence coefficient of mobility, β = 0.73;

[0113] Get the optimized specific on-resistance:

[0114] According to the optimized specific on-resistance obtained above, the aspect ratio AR and dielectric constant ratio K r Set as an independent variable, and you can get the constructed objective function R on,sp(opt) (AR,K r ); Set BV = 1000V, a = 1μm, AR range is 1 to 70, K r When the range is 10 to 500, the R on,sp(opt) (AR,K r )like Figure 5 As shown; similarly, the breakdown voltage BV and the semiconductor region width a can also be set as independent variables to obtain relevant optimization results;

[0115] Step 4. Perform polynomial fitting on the numerical solution of the objective function to obtain a polynomial fitting expression of the objective function;

[0116] Step 4.1 Logarithmic dimensionality reduction of parameters

[0117] Since the optimization process involves complex calculation processes such as collision ionization integration, the obtained relationship has a complex power function relationship. In order to facilitate fitting, all parameters are taken logarithmically, that is: σ=logAR, θ=logK r ,γ=logR on,sp(opt) , ω=logW (opt) , where R on,sp(opt) , and W (opt) The units are mΩ·cm 2 、cm -3and μm; therefore, the optimization design objective function R on,sp(opt) (AR,K r ) is transformed into γ(σ,θ) through dimensionality reduction, that is, logR on,sp(opt) (logAR,logK r );

[0118] Similarly, we can also fit and W (opt) (AR,K r ), which are ν(σ,θ) and ω(σ,θ), respectively. This method is also applicable to parameters such as breakdown voltage BV and semiconductor region width a as fitting variables;

[0119] Step 4.2 polynomial surface fitting;

[0120] Use the least squares method to obtain R on,sp(opt) (AR,K r ), and the surface was fitted using a bivariate polynomial, with a goodness of fit R of 0.9999. The fitted image is shown in Figure 6 As shown, the obtained polynomial expression is:

[0121] γ(σ,θ)=p 00 +p 10 σ+p 01 θ+p 20 σ 2 +p 11 σθ+p 02 θ 2 +p 30 σ 3 +p 21 σ 2 θ+p 12 σθ 2 +p 03 θ 3 +p 31 σ 3 θ+p 22 σ 2 θ 2 +p 13 σθ 3 +p 04 θ 4

[0122] Among them, the highest power of σ is 3, the highest power of θ is 4, and p ij is the coefficient, i represents the power of σ in this term, j represents the power of θ in this term, and there are 14 coefficients in total; at the same time, ν(σ,θ) and ω(σ,θ) can also be fitted using the above polynomial expressions; the fitting coefficients are shown in the following table:

[0123]

[0124] like Figure 7 As shown, the dielectric constant ratio K r The R obtained when is 50, 100, 200 on,sp(opt) (AR) fitting curve; Figure 8 As shown in the figure, the R obtained when the aspect ratio AR is 10, 20, and 40 on,sp(opt) (K r ), it can be found that the fitting result is highly consistent with the Taylor series solution, which verifies the feasibility of the fitting method in the present invention;

[0125] Step 5. Calculate the optimal value of the aspect ratio AR according to the polynomial fitting expression of the objective function;

[0126] By observing the optimized specific on-resistance results, the present invention finds that there is an optimal value for the aspect ratio AR. By taking the derivative of the fitting function, the optimal value of the specific on-resistance can be obtained, which guides the design of the optimal structure under corresponding conditions during the manufacturing process.

[0127] Derivative the polynomial fitting expression of the objective function:

[0128]

[0129] according to Get the optimal value of σ;

[0130] Under the conditions of BV = 1000V and a = 1μm, the optimal value of the aspect ratio AR is as follows: Fig. 9 As shown, at each dielectric constant ratio K r Under this condition, the aspect ratio AR has a unique optimal value, such as Fig. 9 As shown by the white dot in the middle; in practical applications, when a high dielectric constant insulating medium is selected, that is, the dielectric constant is higher than K r Given, the optimal value of the aspect ratio AR can be obtained, and then the optimized Hk super junction structure can be designed.

[0131] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A high dielectric constant super junction MOSFET structure optimization method, characterized in that: The following steps are involved: Step 1. Establish a coordinate system and list the Poisson equation and boundary conditions. Use Taylor expansion potential at the boundary to solve the electric field expression of the semiconductor region and the high dielectric constant insulating medium region. Step 2. Based on the electric field expressions of the semiconductor region and the high dielectric constant insulating dielectric region, the aspect ratio (AR) and dielectric constant ratio (K r ) is the optimization parameter, and the optimization objective function and constraint conditions are constructed with the goal of minimizing the specific on-resistance; Step 3. According to the constraints, the dimensionality reduction method is used to obtain the numerical solution of the objective function; Step 4. Perform polynomial fitting on the numerical solution of the objective function to obtain a polynomial fitting expression of the objective function; Step 5. According to the polynomial fitting expression of the objective function, the optimized value of the aspect ratio and the dielectric constant ratio is calculated.

2. The high dielectric constant super junction MOSFET structure optimization method according to claim 1, characterized in that: In step 1, the electric field expression E in the semiconductor region is Sy (x, y) is: The electric field expression E in the high dielectric constant insulating medium region Iy (x, y) is: Wherein, (x, y) represents the coordinates, a is the width of the n-type semiconductor region, W is the depth of the drift region, and BV is the reverse breakdown voltage; V e , T c , T d , T e is the parameter symbol, K r is the dielectric constant ratio; q is the unit charge, N D is the impurity doping concentration of the n-type semiconductor region, ε S is the dielectric constant of silicon, b is the width of the high dielectric constant dielectric region, ε I is the dielectric constant of the insulating medium region; 3. The high dielectric constant super junction MOSFET structure optimization method according to claim 1, characterized in that: In step 2, the objective function is: Among them, R on,sp (AR, K r ) represents the ratio of AR and K r is the design parameter of on-resistance, AR represents the aspect ratio, K r Indicates the dielectric constant ratio; W(AR, K r ) represents the ratio of AR and K r is the drift zone depth of the design parameter, N D (AR, K r ) is based on AR and K r is the doping concentration of the n-type semiconductor region of the design parameter, μ n (AR, K r ) represents the ratio of AR and K r is the electron mobility of the design parameter; g represents the unit charge, and a is the width of the n-type semiconductor region.

4. The high dielectric constant super junction MOSFET structure optimization method according to claim 1, characterized in that: In step 2, the first constraint is critical exhaustion, which is specifically expressed as: AND Sy (x, y) = 0, x = a, y = 0 Where (x, y) represents the coordinates, E Sy (x, y) represents the electric field in the y direction of the semiconductor region, and a is the width of the n-type semiconductor region; The second constraint is critical breakdown, which is specifically expressed as: I n (W)=∫0 W α n exp[∫0 y (α p -α n )dy′]to=1 Among them, I n represents the ionization integral, α n With α p represent the impact ionization rates of electrons and holes, respectively.

5. The high dielectric constant super junction MOSFET structure optimization method according to claim 1, characterized in that: In step 3, the specific process of dimensionality reduction is: At the symmetry axis of the semiconductor region, the electric field strength is simplified as: E Sy (x,y)=f1(BV,K r ,a,AR,b,W,N D ,y),x=-a Where (x, y) represents the coordinates, E Sy (x, y) represents the electric field in the y direction of the semiconductor region, a is the width of the n-type semiconductor region; BV is the reverse breakdown voltage; K r is the dielectric constant ratio, a and b are the widths of the semiconductor region and the high dielectric constant insulating medium region, AR is the aspect ratio, W is the depth of the drift region, N D is the doping concentration of the semiconductor region; according to The above electric field strength expression is reduced to: E Sy (x,y)=f2(BV,K r ,a,AR,W,N D ,y),x=-a Using exhaustive method to give BV, K r , a and AR, the above electric field intensity expression is reduced to: E Sy (x,y)=f3(W,N D ,y),x=-a According to the first constraint, E Sy (x, y) = f3(W, N D , 0) = 0, x = -a; use Newton iteration method to solve, and change the doping concentration N D The drift zone depth W is expressed as N D =g(W); It should be noted that f1, f2, f3, and g all represent function symbols in the dimensionality reduction process; According to the second constraint, I n (W) = 1, I n (W) represents the ionization integral along the symmetry line of the semiconductor region; Newton iteration method is used to solve the optimized drift region depth W (opt) ; According to N D = g(W), to obtain the optimized doping concentration According to the Caughey Thomas model, the optimized electron mobility is obtained Then the optimized specific on-resistance R is calculated. on，sp(opt) :

6. The high dielectric constant super junction MOSFET structure optimization method according to claim 1, characterized in that: In step 4, the polynomial fitting expression of the objective function is: γ(σ,θ)=p 00 +p 10 s+p 01 θ+p 20 s 2 +p 11 sth+p 02 i 2 +p 30 s 3 +p 21 s 2 θ+p 12 th 2 +p 03 i 3 +p 31 s 3 θ+p 22 s 2 θ2+p 13 th 3 +p 04 i 4 Among them, σ=log AR, θ=log K r ,γ=log R onJsp(opt) , R on，sp(opt) is the numerical solution of the objective function, AR is the aspect ratio, K r is the dielectric constant ratio; p ij are polynomial coefficients, i represents the power of σ, and j represents the power of θ.

7. The high dielectric constant super junction MOSFET structure optimization method according to claim 6, characterized in that: In step 5, the specific process is: Derivative the polynomial fitting expression of the objective function: The dielectric constant ratio K is calculated based on the selected high dielectric constant insulating medium r ,Depend on The optimal value of σ obtained by calculation is the optimal value of the aspect ratio AR.

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