Circuit simulation method and device, computer equipment and storage medium

Abstract

The invention relates to a circuit simulation method and device, computer equipment and a storage medium. The method comprises the following steps: acquiring a circuit netlist file and a test vector file; generating a fault list according to the analysis result of the to-be-simulated circuit; sorting the plurality of target test vector groups in the test vector file according to a preset sorting scheme to obtain a grouping sorting result; performing logic simulation or fault simulation on the to-be-simulated circuit according to the target test vector groups in the grouping and sorting result by utilizing a plurality of threads of different kernels to obtain a logic simulation result and a fault simulation result corresponding to each target test vector; and outputting a circuit simulation result according to the logic simulation result and the fault simulation result. And logic simulation or fault simulation is carried out on the to-be-simulated circuit by utilizing a plurality of threads of different kernels and utilizing different target test vector groups, so that the problems of long time consumption and low efficiency in a simulation process of an existing circuit simulation method are solved.

Description

Technical Field

[0001] The present application relates to the field of electronic design automation technology, and in particular to a circuit simulation method, device, computer equipment and storage medium. Background Art

[0002] In modern integrated circuit design, the verification stage is a key link. Traditional serial simulation methods are inefficient when dealing with large-scale circuit designs and are unable to meet the growing design complexity and rapid iteration requirements. Existing EDA tools and simulation technologies are mainly based on single-core processing, resulting in a time-consuming and inefficient simulation process. Summary of the invention

[0003] The present application provides a circuit simulation method, apparatus, computer equipment and storage medium to solve the problem that the simulation process of the existing circuit simulation method is time-consuming and inefficient.

[0004] In a first aspect, the present application provides a circuit simulation method, the method comprising:

[0005] Obtaining a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes a plurality of test vector groups, each test vector group includes a plurality of test vectors, and each test vector is used to simulate an input state;

[0006] Generate a fault list according to the analysis result of the circuit to be simulated, wherein the fault list includes a plurality of predicted fault points;

[0007] Sorting the multiple target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors;

[0008] Using multiple threads of different cores to perform logic simulation on the circuit to be simulated according to the target test vector groups in the grouping and sorting results, and obtaining logic simulation results corresponding to each target test vector;

[0009] Using multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, to obtain a fault simulation result corresponding to each target test vector;

[0010] The circuit simulation results are output according to the logic simulation results corresponding to each target test vector and the fault simulation results corresponding to each target test vector.

[0011] In a second aspect, the present application provides a circuit simulation device, the device comprising:

[0012] An acquisition module, used for acquiring a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes a plurality of test vector groups, each test vector group includes a plurality of test vectors, and each test vector is used for simulating an input state;

[0013] An analysis module, used for generating a fault list according to the analysis result of the circuit to be simulated, wherein the fault list includes a plurality of predicted fault points;

[0014] A sorting module, used to sort the multiple target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors;

[0015] A logic simulation module, used to use multiple threads of different cores to perform logic simulation on the circuit to be simulated according to the target test vector groups in the grouping and sorting results, and obtain logic simulation results corresponding to each target test vector;

[0016] A fault simulation module, used to use multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, and obtain a fault simulation result corresponding to each target test vector;

[0017] The output module is used to output the circuit simulation results according to the logic simulation results corresponding to each target test vector and the fault simulation results corresponding to each target test vector.

[0018] In a third aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned circuit simulation method when executing the computer program.

[0019] In a fourth aspect, the present application also provides a computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the above-mentioned circuit simulation method.

[0020] The above technical solution provided by the embodiment of the present application has the following advantages over the prior art: the method provided by the embodiment of the present application obtains a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes multiple test vector groups, each test vector group includes multiple test vectors, and each test vector is used to simulate an input state; a fault list is generated according to the analysis result of the circuit to be simulated, wherein the fault list includes multiple predicted fault points; multiple target test vector groups in the test vector file are sorted according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors; multiple threads of different cores are used to perform logic simulation on the circuit to be simulated according to the target test vector group in the group sorting result, and obtain logic simulation results corresponding to each target test vector; multiple threads of different cores are used to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the group sorting result, and obtain fault simulation results corresponding to each target test vector; circuit simulation results are output according to the logic simulation results corresponding to each target test vector and the fault simulation results corresponding to each target test vector.

[0021] Based on the above method, multiple threads of different cores are used to perform logic simulation or fault simulation on the circuit to be simulated using different target test vector groups, which can improve the circuit simulation efficiency and shorten the simulation time, thereby solving the problem of long simulation process and low efficiency of existing circuit simulation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0024] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0025] Figure 1 A schematic diagram of a flow chart of a circuit simulation method provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a flow chart of a circuit simulation method provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of a flow chart of a circuit simulation method provided in an embodiment of the present application;

[0028] Figure 4 A structural block diagram of a circuit simulation device provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of the internal structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0032] In one embodiment, Figure 1 FIG. 1 is a flow chart of a circuit simulation method in an embodiment, referring to FIG. Figure 1 , a circuit simulation method is provided. This embodiment mainly uses the method applied to a server as an example, and the circuit simulation method specifically includes the following steps:

[0033] Step S210, obtaining a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes multiple test vector groups, each test vector group includes multiple test vectors, and each test vector is used to simulate an input state.

[0034] Specifically, the circuit netlist file and the test vector file are read as files imported into the server in advance for circuit simulation. Figure 2 and Figure 3It can be seen that before this, the process library file is imported into the system, the data in the process library is parsed, and the key parameters and rules are extracted to provide support for subsequent circuit analysis and simulation.

[0035] Step S220: generating a fault list according to the analysis result of the circuit to be simulated, wherein the fault list includes a plurality of predicted fault points.

[0036] Specifically, refer to Figure 2 and Figure 3 , the analysis result of the circuit to be simulated can be obtained by analyzing the circuit to be simulated. The analysis result includes the module hierarchy of the circuit to be simulated, the connection relationship diagram, the input and output ports of each module, and multiple predicted fault points identified based on the circuit structure. The multiple predicted fault points identified based on the circuit structure form a fault list. The predicted fault point can be a single fault point or multiple fault points, and the predicted fault points in the fault list are the fault points that have been deduplicated.

[0037] Step S230, sorting the multiple target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group.

[0038] Specifically, corresponding to Figure 2 In the vector parsing step, the preset sorting scheme includes a variety of different sorting indicators, and the multiple target test vector groups in the test vector file are sorted by at least one sorting indicator. The sorting indicator can specifically be vector characteristic information or the difference between vectors. All target test vectors in the target test vector group are part of the test vectors or all the test vectors in the corresponding test vector group, that is, the target test vector group is a subset of the corresponding target test vector group or the corresponding target test vector group. The target test vector that is ranked higher in the group sorting result can provide more information and the corresponding fault detection probability is higher. According to the sorting order of each target test vector in the group sorting result, each target test vector is used in turn to perform circuit simulation on the circuit to be simulated. The circuit simulation includes logic simulation and fault simulation.

[0039] Step S240 , using multiple threads of different cores to perform logic simulation on the circuit to be simulated according to the target test vector groups in the grouping and sorting results, to obtain logic simulation results corresponding to the target test vectors.

[0040] Specifically, logic simulation is used to verify the logical correctness of the circuit, and multiple threads of multiple cores are used in parallel to perform logic simulation on the circuit to be simulated using different target test vector groups in the grouping and sorting results, that is, multiple threads of different cores use a target test vector group to perform logic simulation on the circuit to be simulated, but the number of threads that can be created by multiple cores is limited, and it may not be possible to perform logic simulation on all target test vector groups in the grouping and sorting results in parallel. Therefore, each thread of each core sequentially pulls the target test vector group that has not been circuit simulated according to the grouping and sorting results, that is, after the thread completes the logic simulation on the circuit to be simulated using the current target test vector group, it will pull the first target test vector that has not been circuit simulated from the grouping and sorting results to continue to perform logic simulation on the circuit to be simulated. By performing logic simulation in parallel with multiple threads of multiple cores, the efficiency of logic simulation can be improved and the time consumption of logic simulation can be shortened.

[0041] In this embodiment, a single core uses a first number of multiple threads to perform logic simulation tasks in parallel. The first number can be 30, 31, 32, etc. Here it is 32, that is, 32 threads are used to perform logic simulation tasks in parallel. The logic simulation task is to use a target test vector group to perform logic simulation on the circuit to be simulated.

[0042] Step S250, using multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, to obtain a fault simulation result corresponding to each target test vector.

[0043] Specifically, fault simulation is used to detect the behavior when there is a fault in the circuit. Since the predicted fault points are divided into single fault points and multiple fault points, fault simulation is also divided into single fault simulation and multiple fault simulation. Multiple threads of multiple cores are used to perform fault simulation on the circuit to be simulated using different target test vector groups in the grouping and sorting results in parallel, that is, multiple threads of different cores use a target test vector group to perform fault simulation on the circuit to be simulated, but the number of threads that can be created by multiple cores is limited, and it may not be possible to perform fault simulation on all target test vector groups in the grouping and sorting results in parallel. Therefore, each thread of each core sequentially pulls the target test vector group that has not been simulated according to the grouping and sorting results, that is, after the thread uses the current target test vector group to perform fault simulation on the circuit to be simulated, it will pull the first target test vector that has not been simulated from the grouping and sorting results to continue to perform fault simulation on the circuit to be simulated. By performing fault simulation in parallel with multiple threads of multiple cores, the efficiency of fault simulation can be improved and the time consumption of fault simulation can be shortened.

[0044] Since fault simulation occupies a higher memory space than logic simulation, a single core uses a second number of multiple threads to perform fault simulation tasks in parallel, and the second number is less than the first number, that is, a smaller number of threads are used to perform fault simulation tasks, and the second number is 30, that is, 30 threads are used to perform fault simulation tasks in parallel. The fault simulation task is to use a target test vector group to perform fault simulation on the predicted fault points in the circuit to be simulated. The fault simulation results include undetectable results (Undetectable Faults, UD) and detectable results (Detectable Faults, DT). Undetectable results refer to fault points that cannot be detected by test vectors, and detectable results refer to fault points that can be detected by test vectors.

[0045] Whether it is used to implement multiple threads of logic simulation or fault simulation, in order to ensure data consistency and accuracy in parallel execution, lock-free data structures and atomic operations are used. This reduces the use of locks, improves the efficiency of concurrent access, and ensures that access to shared data is safe, avoiding race conditions and data conflicts.

[0046] Step S260: outputting circuit simulation results according to logic simulation results corresponding to each target test vector and fault simulation results corresponding to each target test vector.

[0047] Specifically, the circuit simulation result is formed by integrating the logic simulation result and the fault simulation result. Based on the above method, multiple threads of different cores are used to perform logic simulation or fault simulation on the circuit to be simulated using different target test vector groups, which can improve the circuit simulation efficiency and shorten the simulation time, thereby solving the problem of long simulation time and low efficiency of the existing circuit simulation method.

[0048] In one embodiment, before sorting the multiple target test vector groups in the test vector file according to the preset sorting scheme to obtain the group sorting result, the method further includes:

[0049] Determining the dependency relationship between different test vectors in all test vector groups according to the parsing result of the test vector file;

[0050] The test vectors without dependency relationship are determined as target test vectors, and the test vector group to which the target test vectors belong is determined as the target test vector group.

[0051] Specifically, before sorting the target test vector group, it is necessary to first determine the target test vector and the target test vector group in multiple test vector groups, and based on the dependency relationship between each test vector in the same test vector group, screen out the test vectors without dependency relationship as the target test vector, and use the test vector group to which the target test vector belongs as the target test vector group, that is, only sort the test vectors without dependency relationship, and sort them according to the amount of information provided by each target test vector and the corresponding fault detection probability, so as to facilitate the subsequent priority use of those target test vectors that can provide the maximum amount of information and the highest fault detection probability.

[0052] In one embodiment, the step of sorting the plurality of target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result includes:

[0053] According to the characteristic analysis results of each target test vector group and / or the difference between different target test vectors in each target test vector group, each target test vector group is sorted to obtain a group sorting result.

[0054] Specifically, the target test vectors in each target test vector group are subjected to characteristic analysis to obtain characteristic analysis results, which specifically include the number of vector bits of the test vector, the circuit state coverage rate, and the historical fault detection rate. The difference between different target test vectors in each target test vector group is analyzed to obtain the difference between different target test vectors in the same target test vector group. The difference is calculated by the Euclidean distance algorithm, the Hamming distance algorithm, or the cosine similarity algorithm. The Euclidean distance algorithm is used to calculate the Euclidean distance between different target test vectors, which reflects the straight-line distance between different test vectors in multidimensional space; the Hamming distance algorithm is used to calculate the Hamming distance between different target test vectors, which reflects the number of difference bits between binary vectors. The larger the difference calculated based on the Hamming distance algorithm, the greater the input change between the compared test vectors, which may cover more circuit states; the cosine similarity algorithm is used to reflect their similarity by calculating the cosine value of the angle between two test vectors. The larger the difference calculated based on the cosine similarity algorithm, the greater the direction difference between the compared test vectors in the vector space, which means that there is a subject to explore different states of the circuit.

[0055] Each target test vector group can be sorted only according to the characteristic analysis result of the target test vector group, or only according to the difference between different target test vectors in each target test vector group, or each target test vector group can be sorted by combining the characteristic analysis result of the target test vector group and the difference between different target test vectors in the target test vector group.

[0056] If the target test vector group is sorted only based on the characteristic analysis result of the target test vector group, it includes: performing characteristic analysis on each target test vector to determine the characteristic information of each target test vector, wherein the characteristic information includes the number of vector bits, circuit state coverage, and historical fault detection rate; performing weighted summation on the number of vector bits, circuit state coverage, and historical fault detection rate of each target test vector to obtain the characteristic value of each target test vector, wherein the weighting coefficient corresponding to the historical fault detection rate is greater than the sum of the weighting coefficient corresponding to the number of vector bits and the weighting coefficient corresponding to the circuit state coverage, that is, the sorting result depends mainly on the historical fault detection rate; summing the characteristic values ​​of each target test vector in the same target test vector group to obtain the total characteristic value of the target test vector group, that is, the characteristic analysis result includes the characteristic value of the target test vector and the total characteristic value of the target test vector group; sorting each target test vector group in descending order of the total characteristic value to obtain a group sorting result.

[0057] If the target test vector group is sorted only according to the difference between different target test vectors in the target test vector group, it includes: sorting each target test vector in the same target test vector group according to the difference between each target test vector in the same target test vector group, and obtaining a sorted vector group corresponding to each target test vector group; the difference between different target test vectors in the sorted vector group can be represented by a similarity matrix, and the difference between each target test vector in the sorted vector group is summed up, that is, all values ​​in the similarity matrix are summed up to obtain the total difference value of the sorted vector group; sorting each sorted vector group in descending order of the total difference value to obtain a group sorting result.

[0058] In one embodiment, each target test vector group is sorted according to the characteristic analysis result of each target test vector group and the difference between different target test vectors in each target test vector group to obtain a group sorting result, including:

[0059] Performing characteristic analysis on each target test vector to determine characteristic information of each target test vector, wherein the characteristic information includes the number of vector bits, circuit state coverage, and historical fault detection rate;

[0060] Perform weighted summation on the number of vector bits, circuit state coverage, and historical fault detection rate of each target test vector to obtain the characteristic value of each target test vector;

[0061] Sorting the target test vectors in the same target test vector group according to the differences between the target test vectors in the same target test vector group to obtain sorted vector groups corresponding to the target test vector groups;

[0062] Performing a weighted summation of the differences between the characteristic value of each target test vector and other target test vectors in the same sorting vector group to obtain a comprehensive value of each target test vector;

[0063] summing the comprehensive values ​​of each target test vector in the same sorting vector group to determine the comprehensive total value of each sorting vector group;

[0064] Each sorting vector group is sorted in descending order of the comprehensive total value to obtain a group sorting result.

[0065] Specifically, characteristic analysis is performed on each target test vector to determine the characteristic information of the target test vector, which includes the number of vector bits, circuit state coverage, and historical fault detection rate. The number of vector bits is the length of the vector, which indicates the complexity of the input signal; the circuit state coverage indicates the range of circuit states that the test vector can cover; and the historical fault detection rate indicates the situation in which the test vector detected faults in previous simulations. The three characteristic parameter values ​​are weighted and summed to obtain the characteristic value of the target test vector, where the weight coefficient corresponding to the historical fault detection rate is greater than the sum of the weight coefficient corresponding to the number of vector bits and the weight coefficient corresponding to the circuit state coverage, which amplifies the influence of the historical fault detection rate on the sorting result.

[0066] The difference degree of each target test vector in the same target test vector group is calculated, and then the difference degree between different target test vectors is sorted within the group to obtain a sorted sorted vector group. The difference degree indicates the degree of difference between different target test vectors. The greater the difference degree, the greater the difference between the two compared target test vectors. The difference degree between different target test vectors in the sorted vector group can be represented by a similarity matrix. Each difference degree in the similarity matrix is ​​weighted and summed with the characteristic value of the corresponding target test vector to obtain a comprehensive value of the target test vector. The weight coefficient of the difference degree and the characteristic value can be customized according to the application scenario.

[0067] By adding up the comprehensive values ​​of all target test vectors in the sorting vector group, the comprehensive total value of the sorting vector group can be obtained. The sorting vector groups are sorted in descending order of the comprehensive total value to obtain a group sorting result, that is, the group sorting result not only includes the sorting results between different target test vector groups, but also includes the sorting results between different target test vectors within the target test vector group. Circuit simulation is performed according to the group sorting result, thereby limiting the execution order of the target test vector group and the target test vector within the target test vector group.

[0068] In one embodiment, sorting the target test vectors in the same target test vector group according to the difference between the target test vectors in the same target test vector group to obtain sorted vector groups corresponding to the target test vector groups includes:

[0069] The first target test vector in the target test vectors is used as the current sorting vector, and the target test vector with the largest difference from the current sorting vector is selected as the next sorting vector adjacent to the current sorting vector;

[0070] The next sorting vector is used as the new current sorting vector, and the target test vector with the largest difference from the current sorting vector is selected as the next sorting vector to be sorted adjacent to the current sorting vector, until there is no target test vector to be sorted in the target test vector.

[0071] Specifically, when sorting the target test vectors in the target test vector group within the group, first determine the target test vector ranked first, and use the target test vector originally ranked first in the target test vector group as the first target test vector in the sorted vector group, that is, select the original first target test vector to continue to be ranked first, and then select the target test vector with the largest difference from the first target test vector from the remaining target test vectors and rank it next to the current sorted vector, that is, the second. Taking this as an example, after each time the ranking order of a target test vector is determined, select the target test vector with the largest difference from the current sorted vector from the remaining unsorted target test vectors and rank it next to the current sorted vector, until there are no target test vectors to be sorted in the target test vector group, thereby completing the intra-group sorting of the target test vector group, thereby obtaining the sorted sorted vector group, and performing circuit simulation on each target test vector according to the intra-group sorting order of the sorted vector group, which can cover more circuit states, thereby improving the circuit state coverage and fault coverage of the circuit simulation.

[0072] In one embodiment, in the process of performing logic simulation on the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, or in the process of performing fault simulation on each predicted fault point in the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, the method further includes:

[0073] Get the whole machine load information;

[0074] When the whole machine load information indicates a first load state, stop delivering the target test vector group that has not undergone simulation to each thread;

[0075] When the whole machine load information indicates a second load state, the number of threads is reduced and the number of memory accesses during the simulation process is reduced, wherein the load amount corresponding to the second load state is greater than the load amount corresponding to the first load state.

[0076] Specifically, whether in the process of logic simulation or fault simulation, it is necessary to monitor the load of the whole machine in real time, that is, the load information of the whole machine refers to the load of the server for circuit simulation. The load information of the whole machine is the weighted sum of computing intensity, data dependency and CPU core resource occupancy rate. The computing intensity is used to indicate the CPU resource occupancy of the circuit simulation task. The circuit simulation task includes logic simulation task and fault simulation task. Data dependency refers to the dependency of each target test vector in the same sorting vector group on the same execution thread, that is, whether each target test vector in the same sorting vector group must be executed in the same thread. The CPU core resource occupancy rate reflects the CPU load status. The whole machine load information indicates the first load state, which means that the CPU load is heavy. At this time, it is necessary to prevent the CPU from continuing to increase the load, so stop sending the target test vector group that has not been simulated to each thread; if the whole machine load information indicates the second load state, it means that the CPU is about to run at full load. At this time, the CPU needs to be unloaded, so the number of threads participating in the circuit simulation is reduced and the number of memory accesses during the simulation process is reduced. Specifically, the number of threads can be reduced for the core with the heaviest load, or the number of threads can be reduced by the same number for each core, thereby reducing the whole machine load. In this way, the load state is dynamically adjusted to ensure the reasonable allocation of computing resources and optimize the simulation efficiency.

[0077] In one embodiment, in the process of performing logic simulation on the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, or in the process of performing fault simulation on each predicted fault point in the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, the method further includes:

[0078] Get the core load information of each core;

[0079] When there are threads in an idle state in the core load information of the first core, and the core load information of the second core indicates that all threads of the second core are in a busy state, the tasks to be simulated of the second core are assigned to the threads in the idle state in the first core, wherein the first core and the second core are different cores, and the tasks to be simulated include logic simulation tasks that perform logic simulation on the circuit to be simulated using an unsimulated target test vector group, and fault simulation tasks that perform fault simulation on the circuit to be simulated using an unsimulated target test vector group.

[0080] Specifically, the core load information is used to indicate the load status of each thread of the core. If there are threads in an idle state in the core load information of the first core, and all threads of the second core are in a busy state, the tasks to be simulated of the second core are allocated to the threads in the idle state in the first core. In this way, when a thread of a core completes its own simulation task, it can steal some unfinished tasks to be simulated from threads of other cores, thereby realizing workload redistribution and balancing, ensuring that the computing resources of all CPU cores are fully utilized, and avoiding the situation where some cores are overloaded while other cores are idle.

[0081] Figure 1 FIG. 1 is a flow chart of a circuit simulation method in one embodiment. It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0082] In one embodiment, Figure 4 As shown, a circuit simulation device is provided, comprising:

[0083] An acquisition module 310 is used to acquire a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes a plurality of test vector groups, each test vector group includes a plurality of test vectors, and each test vector is used to simulate an input state;

[0084] The analysis module 320 is used to generate a fault list according to the analysis result of the circuit to be simulated, wherein the fault list includes a plurality of predicted fault points;

[0085] A sorting module 330 is used to sort the multiple target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors;

[0086] A logic simulation module 340 is used to use multiple threads of different cores to perform logic simulation on the circuit to be simulated according to the target test vector groups in the grouping and sorting results, and obtain logic simulation results corresponding to each target test vector;

[0087] A fault simulation module 350 is used to use multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, and obtain a fault simulation result corresponding to each target test vector;

[0088] The output module 360 ​​is used to output the circuit simulation result according to the logic simulation result corresponding to each target test vector and the fault simulation result corresponding to each target test vector.

[0089] In one embodiment, the parsing module 320 is further configured to:

[0090] Determining the dependency relationship between different test vectors in all test vector groups according to the parsing result of the test vector file;

[0091] The test vectors without dependency relationship are determined as target test vectors, and the test vector group to which the target test vectors belong is determined as the target test vector group.

[0092] In one embodiment, the sorting module 330 is further configured to:

[0093] According to the characteristic analysis results of each target test vector group and / or the difference between different target test vectors in each target test vector group, each target test vector group is sorted to obtain a group sorting result.

[0094] In one embodiment, the sorting module 330 is further configured to:

[0095] Performing characteristic analysis on each target test vector to determine characteristic information of each target test vector, wherein the characteristic information includes the number of vector bits, circuit state coverage, and historical fault detection rate;

[0096] Perform weighted summation on the number of vector bits, circuit state coverage, and historical fault detection rate of each target test vector to obtain the characteristic value of each target test vector;

[0097] Sorting the target test vectors in the same target test vector group according to the differences between the target test vectors in the same target test vector group to obtain sorted vector groups corresponding to the target test vector groups;

[0098] Performing a weighted summation of the differences between the characteristic value of each target test vector and other target test vectors in the same sorting vector group to obtain a comprehensive value of each target test vector;

[0099] summing the comprehensive values ​​of each target test vector in the same sorting vector group to determine the comprehensive total value of each sorting vector group;

[0100] Each sorting vector group is sorted in descending order of the comprehensive total value to obtain a group sorting result.

[0101] In one embodiment, the sorting module 330 is further configured to:

[0102] The first target test vector in the target test vectors is used as the current sorting vector, and the target test vector with the largest difference from the current sorting vector is selected as the next sorting vector adjacent to the current sorting vector;

[0103] The next sorting vector is used as the new current sorting vector, and the target test vector with the largest difference from the current sorting vector is selected as the next sorting vector to be sorted adjacent to the current sorting vector, until there is no target test vector to be sorted in the target test vector.

[0104] In one embodiment, the device further includes a load balancing module, configured to:

[0105] Get the whole machine load information;

[0106] When the whole machine load information indicates a first load state, stop delivering the target test vector group that has not undergone simulation to each thread;

[0107] When the whole machine load information indicates a second load state, the number of threads is reduced and the number of memory accesses during the simulation process is reduced, wherein the load amount corresponding to the second load state is greater than the load amount corresponding to the first load state.

[0108] In one embodiment, the load balancing module is further used to:

[0109] Get the core load information of each core;

[0110] When there are threads in an idle state in the core load information of the first core, and the core load information of the second core indicates that all threads of the second core are in a busy state, the tasks to be simulated of the second core are assigned to the threads in the idle state in the first core, wherein the first core and the second core are different cores, and the tasks to be simulated include logic simulation tasks that perform logic simulation on the circuit to be simulated using an unsimulated target test vector group, and fault simulation tasks that perform fault simulation on the circuit to be simulated using an unsimulated target test vector group.

[0111] like Figure 5 As shown, an embodiment of the present application provides a computer device, including a processor 711, a communication interface 712, a memory 713 and a communication bus 714, wherein the processor 711, the communication interface 712, and the memory 713 communicate with each other through the communication bus 714;

[0112] Memory 713, used for storing computer programs;

[0113] The processor 711 is used to implement the circuit simulation method provided by any one of the aforementioned method embodiments when executing the program stored in the memory 713.

[0114] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0115] In one embodiment, the circuit simulation device provided by the present application can be implemented in the form of a computer program. The computer program can be Figure 5 The computer device shown in the figure is run. The memory of the computer device can store various program modules constituting the circuit simulation device, such as: Figure 4 The acquisition module 310, analysis module 320, sorting module 330, logic simulation module 340, fault simulation module 350 and output module 360 ​​are shown. The computer program composed of various program modules enables the processor to execute the circuit simulation method of each embodiment of the present application described in this specification.

[0116] Figure 5 The computer device shown can be Figure 4The acquisition module 310 in the circuit simulation device shown in the figure executes to acquire a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes multiple test vector groups, each test vector group includes multiple test vectors, and each test vector is used to simulate an input state. The computer device can generate a fault list according to the analysis result of the circuit to be simulated through the analysis module 320, wherein the fault list includes multiple predicted fault points. The computer device can execute the sorting of multiple target test vector groups in the test vector file according to a preset sorting scheme through the sorting module 330 to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors. The computer device can execute the logic simulation of the circuit to be simulated according to the target test vector group in the group sorting result using multiple threads of different cores through the logic simulation module 340, and obtain the logic simulation results corresponding to each target test vector. The computer device can use the fault simulation module 350 to execute multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, and obtain the fault simulation result corresponding to each target test vector. The computer device can use the output module 360 ​​to execute the logic simulation result corresponding to each target test vector and the fault simulation result corresponding to each target test vector, and output the circuit simulation result.

[0117] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the circuit simulation method provided by any of the aforementioned method embodiments is implemented.

[0118] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0120] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative can be used.

[0121] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A circuit simulation method, characterized in that: The method comprises: Obtaining a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes a plurality of test vector groups, each test vector group includes a plurality of test vectors, and each test vector is used to simulate an input state; Generate a fault list according to the analysis result of the circuit to be simulated, wherein the fault list includes a plurality of predicted fault points; Sorting the multiple target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors; Using multiple threads of different cores to perform logic simulation on the circuit to be simulated according to the target test vector groups in the grouping and sorting results, respectively, to obtain logic simulation results corresponding to each target test vector; Using multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, to obtain a fault simulation result corresponding to each target test vector; The circuit simulation results are output according to the logic simulation results corresponding to each target test vector and the fault simulation results corresponding to each target test vector.

2. The method according to claim 1, characterized in that Before sorting the multiple target test vector groups in the test vector file according to the preset sorting scheme to obtain the group sorting result, the method further includes: Determining the dependency relationship between different test vectors in all test vector groups according to the parsing result of the test vector file; The test vectors without dependency relationship are determined as target test vectors, and the test vector group to which the target test vectors belong is determined as the target test vector group.

3. The method according to claim 1, characterized in that: The step of sorting the plurality of target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result includes: According to the characteristic analysis results of each target test vector group and / or the difference between different target test vectors in each target test vector group, each target test vector group is sorted to obtain a group sorting result.

4. The method according to claim 3, characterized in that According to the characteristic analysis results of each target test vector group and the difference between different target test vectors in each target test vector group, each target test vector group is sorted to obtain a group sorting result, including: Performing characteristic analysis on each target test vector to determine characteristic information of each target test vector, wherein the characteristic information includes the number of vector bits, circuit state coverage, and historical fault detection rate; Perform weighted summation on the number of vector bits, circuit state coverage, and historical fault detection rate of each target test vector to obtain the characteristic value of each target test vector; Sorting the target test vectors in the same target test vector group according to the differences between the target test vectors in the same target test vector group to obtain sorted vector groups corresponding to the target test vector groups; Performing a weighted summation of the differences between the characteristic value of each target test vector and other target test vectors in the same sorting vector group to obtain a comprehensive value of each target test vector; summing the comprehensive values ​​of each target test vector in the same sorting vector group to determine the comprehensive total value of each sorting vector group; Each sorting vector group is sorted in descending order of the comprehensive total value to obtain a group sorting result.

5. The method according to claim 4, characterized in that The step of sorting the target test vectors in the same target test vector group according to the differences between the target test vectors in the same target test vector group to obtain sorted vector groups corresponding to the target test vector groups includes: The first target test vector in the target test vectors is used as the current sorting vector, and the target test vector with the largest difference from the current sorting vector is selected as the next sorting vector adjacent to the current sorting vector; The next sorting vector is used as the new current sorting vector, and the target test vector with the largest difference from the current sorting vector is selected as the next sorting vector to be sorted adjacent to the current sorting vector, until there is no target test vector to be sorted in the target test vector.

6. The method according to claim 1, characterized in that In the process of performing logic simulation on the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, or in the process of performing fault simulation on each predicted fault point in the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, the method further includes: Get the whole machine load information; When the whole machine load information indicates a first load state, stop delivering the target test vector group that has not undergone simulation to each thread; When the whole machine load information indicates a second load state, the number of threads is reduced and the number of memory accesses during the simulation process is reduced, wherein the load amount corresponding to the second load state is greater than the load amount corresponding to the first load state.

7. The method according to claim 1, characterized in that In the process of performing logic simulation on the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, or in the process of performing fault simulation on each predicted fault point in the circuit to be simulated using multiple threads of different cores according to the target test vector group in the group sorting result, the method further includes: Get the core load information of each core; When there are threads in an idle state in the core load information of the first core, and the core load information of the second core indicates that all threads of the second core are in a busy state, the tasks to be simulated of the second core are assigned to the threads in the idle state in the first core, wherein the first core and the second core are different cores, and the tasks to be simulated include logic simulation tasks that perform logic simulation on the circuit to be simulated using an unsimulated target test vector group, and fault simulation tasks that perform fault simulation on the circuit to be simulated using an unsimulated target test vector group.

8. A circuit simulation device, characterized in that: The device comprises: An acquisition module, used for acquiring a circuit netlist file and a test vector file, wherein the circuit netlist file includes a circuit to be simulated, and the test vector file includes a plurality of test vector groups, each test vector group includes a plurality of test vectors, and each test vector is used for simulating an input state; An analysis module, used for generating a fault list according to the analysis result of the circuit to be simulated, wherein the fault list includes a plurality of predicted fault points; A sorting module, used to sort the multiple target test vector groups in the test vector file according to a preset sorting scheme to obtain a group sorting result, wherein the test vector group corresponding to the target test vector group includes the target test vector group, and the target test vector group includes multiple target test vectors; A logic simulation module, used to use multiple threads of different cores to perform logic simulation on the circuit to be simulated according to the target test vector groups in the grouping and sorting results, and obtain logic simulation results corresponding to each target test vector; A fault simulation module, used to use multiple threads of different cores to perform fault simulation on each predicted fault point in the circuit to be simulated according to the target test vector group in the grouping and sorting result, and obtain a fault simulation result corresponding to each target test vector; The output module is used to output the circuit simulation results according to the logic simulation results corresponding to each target test vector and the fault simulation results corresponding to each target test vector.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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