Timing constraint automation generation method

Abstract

The invention relates to the technical field of chip design, in particular to a timing constraint automation generation method. According to the method, the actual demand of the clock needing to be created is determined based on the design document, and then the clock list is generated based on the actual demand; the content of the clock list comprises a PLL source, a clock type, a clock name, a source path, a main clock name, a main clock source path, a frequency, a main clock duty ratio, a derivative clock duty ratio, a frequency division coefficient, whether the clock has a cross-clock requirement or not, and the mutual relation between the created clocks; executing the script in a clock list which needs to be read by the configuration script and the specified script; and traversing all options in the clock list by the script, generating a time sequence constraint, and automatically finishing GCA check. According to the method, timing constraint compiling and checking can be automatically achieved through the script only by completing output of the clock list, and the method for compiling the timing constraint is accurate and easy to maintain.

Description

Technical Field

[0001] The invention relates to the technical field of chip design, and in particular to a method for automatically generating timing constraints. Background Art

[0002] In modern chip design, the writing of timing constraints is a key link to ensure design performance and reliability. With the advancement of integrated circuit (IC) technology, the complexity of chip design has increased dramatically. Modern chips usually contain billions of transistors and multiple clock domains, which makes the definition and management of timing constraints more complicated. In order to ensure that these complex designs can work properly at the specified clock frequency, timing constraints must be accurately written and managed; at the same time, modern chips often involve multiple clock domains, each with different clock frequencies and phases. This design increases the complexity of timing constraints because it is necessary to ensure that data transmission and interaction between different clock domains do not cause timing errors. Often in large-scale designs, manual writing and adjustment of timing constraints may not be efficient enough, so it is necessary to study automated tools and methods to achieve timing closure; secondly, the complexity of design rules also needs to be considered, because with the increasing complexity of design rules (such as timing constraints, static timing analysis, etc.), this requires the design team to not only be familiar with basic constraint writing, but also need to understand various rules and restrictions in order to accurately define and manage timing constraints; finally, the needs of verification and testing must also be met, because in order to ensure the reliability and performance of the design, verification and testing of timing constraints become necessary steps. An important direction of current research is to study how to effectively verify timing constraints and ensure that the design will not have problems in actual operation. In general, the writing of timing constraints in chip design needs to face increasingly complex design challenges.

[0003] In the prior art, the writing of timing constraints generally includes the following two methods.

[0004] 1. Manual writing: 1) Based on the clock tree structure, define the properties of all clock signals. This includes clock frequency, phase, duty cycle, etc.; 2) For multi-clock systems, it is often necessary to define clock groups and specify which clock signals are related in order to correctly handle data transmission between clocks; 3) Define clocks across clock domains; 4) Set input / output delays; 5) For situations where data paths require multiple clock cycles to complete transmission, it is also necessary to define multi-cycle path constraints; 6) Set false paths; 7) After completing the manual writing of timing constraints above, you also need to use the GCA (Galaxy Constraint Analyzer) tool to check whether these constraints are correct. If they are wrong, you still need to manually adjust them until the chip design requirements are met; Current technology is insufficient: This method can meet the requirements of timing constraint writing to a certain extent, but its shortcomings are self-evident in the face of the sharp increase in chip design complexity. The first is a lot of time consumption: mainly the cumbersome writing, maintenance and iteration. Because manually writing timing constraints requires a lot of time and effort, especially when the design complexity is high or the design changes are frequent, in addition, the timing constraints need to be rechecked and adjusted after each design change, which may make the design iteration cumbersome; secondly, spelling errors, logical errors or omissions are prone to occur during the manual writing process, which may cause timing problems or design failures; at the same time, for large or multi-clock domain designs, manual management and writing of timing constraints may become very complex and difficult. Constraints involving multiple clock domains are also difficult because the timing relationship between different clock domains needs to be accurately managed; finally, version maintenance is also difficult because in multiple versions of the design, manual maintenance of timing constraints may lead to inconsistencies between versions, increasing the difficulty of management and maintenance.

[0005] 2. EDA tool support: Use EDA tools (such as Synopsys Design Compiler, Cadence Innovus, Mentor Graphics, etc.) to automatically analyze timing. The tool can generate preliminary timing constraints to help designers identify and correct potential timing problems. EDA tools can automatically generate and optimize timing constraints, saving time for manual writing and reducing human errors. At the same time, they support rapid modification and regeneration of constraints, helping designers to quickly respond to design changes or optimization requirements.

[0006] Current technology is insufficient: However, it is convenient but also comes with many disadvantages. For example, the complexity of the tool often requires designers to spend a certain amount of time to learn and master the use of the tool. At the same time, the high cost and maintenance cost make some small design companies discouraged. Finally, the accuracy and readability of constraint generation (black box problem) are still a point that needs attention, because the automatically generated constraints may not fully meet the specific design requirements and still need to be verified and adjusted by the designer. In addition, the poor readability makes it possible for chip design engineers to not fully understand the optimization process and results within the tool. In summary, in chip design, timing constraints are a part that chip design engineers pay close attention to during the design and verification process. Timing constraints not only ensure the correct implementation of functions in chip design, but also optimize design performance, reduce verification time, and support complex design requirements and physical design processes. Reasonable timing constraints are crucial to the successful design and efficient production of chips.

[0007] At the same time, from the perspective of existing technologies, manually writing constraints often takes a lot of time and experience. At the same time, facing the increasing complexity of chip design, the difficulty and error rate of writing constraints have also increased significantly. Although EDA tools can quickly output timing constraints, they cannot meet all design requirements and will also bring high purchase and maintenance costs. Therefore, it is urgent to develop an accurate and easy-to-maintain method for writing timing constraints. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a method for automatically generating timing constraints. It only needs to complete the output of the clock list to automatically realize the writing and checking of timing constraints through scripts. It is an accurate and easy-to-maintain method for writing timing constraints.

[0009] In order to solve the technical problem, the technical solution adopted by the present invention is: a method for automatically generating timing constraints, comprising the following steps: S01) Determine the actual requirements for creating a clock based on the design document; S02) Generate a clock list based on actual needs. The contents of the clock list include PLL source, clock type, clock name, source path, master clock name, master clock source path, frequency, master clock duty cycle, derived clock duty cycle, frequency division coefficient, whether there is a cross-clock requirement, and the relationship between the created clocks; S03), configure the script, specify the clock list that the script needs to read, and execute the script; S04) The script traverses all options in the clock list, generates timing constraints, and automatically completes the GCA check.

[0010] Furthermore, clock types include master clocks and derived clocks. A derived clock is always a clock generated from a master clock. The master clock and the derived clock are represented by different symbols in the clock list.

[0011] Furthermore, when the clock type is the main clock, the corresponding derived clock duty cycle and frequency division coefficient are empty.

[0012] Furthermore, when the clock type is a derived clock, the corresponding master clock duty cycle is empty.

[0013] Furthermore, when there is a need for cross-clock domain clocks, cross-clock domain clocks of derived clocks are created synchronously.

[0014] Furthermore, the relationship between the created clocks includes whether the clocks are in the same group. The clocks in the same group are synchronized, and the clocks in different groups are asynchronous.

[0015] The present invention also discloses an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the above-mentioned automatic generation method of timing constraints when executing the program stored in the memory.

[0016] The present invention further discloses a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for automatically generating timing constraints as described above is implemented.

[0017] Beneficial effects of the present invention: The present invention can automatically complete the automatic writing of timing constraints and the automatic checking of constraints through scripts. It greatly improves the work efficiency of code designers and back-end personnel and reduces design risks. It avoids the problems of slow manual writing of timing constraints, easy errors, and difficult maintenance and modification, improves the inheritance and readability of timing constraints, and reduces the difficulty of management and maintenance. At the same time, it also avoids high maintenance costs to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] Example 1 This embodiment discloses a method for automatically generating timing constraints, such as Figure 1 As shown, the following steps are included: Determine the number of PLLs and their corresponding names in the actual design of the project, confirm the master clocks that need to be created in each PLL and the clocks generated from the master clocks based on the design documents, distinguish them with Port and Pin respectively, and confirm the source path corresponding to each clock, where the clocks generated from the master clocks must first confirm their own source paths and the source paths of the corresponding master clocks. Then, based on the design requirements, confirm the frequency and Waveform of each created master clock, confirm the frequency / frequency division coefficient and clock duty cycle of each created generated clock, confirm whether the created clock has a cross-clock domain requirement, and if so, synchronously create a cross-clock domain clock (CDC clock) for the generated clock. Then confirm the synchronous or asynchronous relationship between each clock, and finally output the clock List; configure and execute the script according to the requirements, traverse all the options in the list according to the determined information of the clock List, generate timing constraints, and automatically complete the GCA check. The present invention only needs to complete the output of the clock List to automatically implement the writing and checking of timing constraints through the script, which is an accurate and easy-to-maintain method for writing timing constraints.

[0021] S01) Based on the design documents, determine the actual requirements for creating clocks. First, determine the number of PLLs in the actual design of the project and their corresponding names. Based on the design documents, confirm the master clock and derived clocks (clocks generated from the master clock) that need to be created in each PLL, and confirm the source path corresponding to each clock. The derived clock must confirm both its own source path and the source path of the corresponding master clock. Then, based on the design requirements, determine the frequency and duty cycle of each master clock, confirm the frequency / division coefficient and duty cycle of each derived clock, confirm whether the derived clock has the requirement to cross the clock domain, confirm the synchronous or asynchronous relationship between each clock, and finally output the clock list.

[0022] S02) Output a clock list based on actual needs. The contents of the clock list include PLL source, clock type, clock name, source path, master clock name, master clock source path, frequency, master clock duty cycle, derived clock duty cycle, division factor, whether there is a cross-clock requirement, and the relationship between the created clocks.

[0023] In this embodiment, two PLL sources are determined based on the design document, namely MPLL and NPLL. In the clock list, type is used to represent the clock type, including the main clock (represented by Port) and the derived clock (represented by Pin), Clock name is used to represent the clock name, PCLK is used to represent the main clock, GCLK is used to represent the derived clock, and Source path is used to represent the source path. The two columns Masterclock name and Master clock source path represent the master clock corresponding to the delayed clock and the source path of the corresponding master clock respectively. Frequency represents the clock frequency corresponding to the clock. The default unit is MHz. The Waveform column represents the relationship between the rising edge and the falling edge of the defined master clock, that is, the duty cycle of the master clock. EDGE represents the relationship between the rising edge and the falling edge of the GCLK clock, that is, the duty cycle of the derived clock. The Divider column represents the frequency division coefficient of the GCLK corresponding to its master clock. It should be noted that when the Clock name column is the master clock, the EDGE and Divider columns should be filled in with NA. Otherwise, when the Clock name column is GCLK, the Waveform column should be filled in with NA. The CDC column represents whether the corresponding clock has a cross-clock check requirement. Y represents a requirement, otherwise N represents no requirement. The Clock group column represents the relationship between the created clocks.

[0024] In this embodiment, the clock type includes a master clock and a derived clock. A derived clock is a clock generated from a master clock. The master clock and the derived clock are represented by different symbols in the clock list. When the clock type is a master clock, the duty cycle and frequency division coefficient of the corresponding derived clock are empty. When the clock type is a derived clock, the duty cycle of the corresponding master clock is empty.

[0025] When there is a need for cross-clock domain clocks, the cross-clock domain clocks of the derived clocks are created synchronously.

[0026] The relationship between the created clocks includes whether the clocks are in the same group. The clocks in the same group are synchronous, and the clocks in different groups are asynchronous.

[0027] S03), configure the script, specify the clock list that the script needs to read, and execute the script; S04) The script traverses all options in the clock list, generates timing constraints, and automatically completes the GCA check.

[0028] In this embodiment, the generated clock list is shown in the following table: The explanation of this table is: The clock name is PCLK_M1 and the type is Port, indicating that it is the created master clock. The source of its PLL is MPLL, and the corresponding Source path is U_CLKC / MPLL / M1. Its frequency is 2000MHz and the waveform is 0-0.25, indicating that the clock duty cycle is 50%. There is no need to create a CDC clock.

[0029] The clock name is GCLK_m1 and the type is Pin, indicating that it is a generated clock. The source of its PLL is MPLL, and the corresponding source path is U_CLKC / MPLL / m1 / Q. Its master clock name and masterclock source path are PCLK_M1 and U_CLKC / MPLL / M1 respectively. Its frequency is 2000MHz. EDGE is 1 2 3, indicating that its clock duty cycle is 50%. Divider is 1, indicating that the division factor of GCLK corresponding to its master clock is 1. CDC is Y, indicating that a CDC clock needs to be created.

[0030] The clock name is GCLK_m2 and the type is Pin, indicating that it is a generated clock. The source of its PLL is MPLL, and the corresponding source path is U_CLKC / MPLL / m2 / Q. Its master clock name and masterclock source path are PCLK_M1 and U_CLKC / MPLL / M1 respectively. Its frequency is 1000MHz. EDGE is 1 3 5, indicating that its clock duty cycle is 50%. Divider is 2, indicating that the division factor of GCLK corresponding to its master clock is 2. CDC is Y, indicating that a CDC clock needs to be created.

[0031] The clock name is GCLK_m4 and the type is Pin, which means it is a generated clock. The source of its PLL is MPLL, and the corresponding source path is U_CLKC / MPLL / m4 / Q. Its master clock name and masterclock source path are PCLK_M1 and U_CLKC / MPLL / M1 respectively. Its frequency is 500MHz. EDGE is 1 5 9, which means its clock duty cycle is 50%. Divider is 4, which means the division factor of GCLK corresponding to its master clock is 4. CDC is Y, which means that a CDC clock needs to be created.

[0032] The clock name is GCLK_m3 and the type is Pin, which means it is a generated clock. The source of its PLL is MPLL, and the corresponding source path is U_CLKC / MPLL / m3 / Q. Its master clock name and masterclock source path are PCLK_M1 and U_CLKC / MPLL / M1 respectively. Its frequency is 500MHz. EDGE is 1 2 5, which means its clock duty cycle is 1:3. Divider is 2, which means the division factor of GCLK corresponding to its master clock is 2. CDC is N, which means that there is no need to create a CDC clock.

[0033] The clock name is PCLK_N1 and the type is Port, indicating that it is the created master clock. The source of its PLL is NPLL, and the corresponding Source path is U_CLKC / NPLL / N1. Its frequency is 1000MHz, and the waveform is 0-0.5, indicating that the clock duty cycle is 50%. CDC is N, indicating that there is no need to create a CDC clock.

[0034] The clock name is GCLK_n2 and the type is Pin, indicating that it is a generated clock. The source of its PLL is NPLL, and the corresponding source path is U_CLKC / NPLL / n2 / Q. Its master clock name and masterclock source path are PCLK_N1 and U_CLKC / NPLL / N1 respectively. Its frequency is 500MHz. EDGE is 1 3 5, indicating that its clock duty cycle is 50%. Divider is 2, indicating that the division factor of GCLK corresponding to its master clock is 2. CDC is Y, indicating that a CDC clock needs to be created.

[0035] The clock name is GCLK_n8 and the type is Pin, which means it is a generated clock. The source of its PLL is NPLL, and the corresponding source path is U_CLKC / NPLL / n8 / Q. Its master clock name and masterclock source path are PCLK_N1 and U_CLKC / NPLL / N1 respectively. Its frequency is 125MHz. EDGE is 1 9 17, which means its clock duty cycle is 50%. Divider is 8, which means the division factor of GCLK corresponding to its master clock is 8. CDC is Y, which means that a CDC clock needs to be created.

[0036] The clock name is GCLK_n3 and the type is Pin, which means it is a generated clock. The source of its PLL is NPLL, and the corresponding source path is U_CLKC / NPLL / n3 / Q. Its master clock name and masterclock source path are PCLK_N1 and U_CLKC / NPLL / N1 respectively. Its frequency is 333.3MHz. EDGE is 1 4 7, which means its clock duty cycle is 50%. Divider is 3, which means the division factor of GCLK corresponding to its master clock is 3. CDC is Y, which means that a CDC clock needs to be created.

[0037] The last column in the table represents the synchronous or asynchronous relationship between the generated clocks. The explanation is as follows. For example, M means that all clocks in the MPLL are in a large group, which can be further subdivided. M11 represents a separate group, and M21 represents an asynchronous relationship with M11. Correspondingly, N means that all clocks in the NPLL are in a large group, which can be further subdivided. N11 represents a separate group, and N21 represents an asynchronous relationship with N11. The generated clock relationship constraints are as follows: set_clock_groups –asynchronous –group { PCLK_M1 GCLK_m1 GCLK_m2 GCLK_m3 GCLK_m4} –group { PCLK_N1 GCLK_n1 GCLK_n2 GCLK_n3 GCLK_n4}, set_clock_groups –asynchronous –group { GCLK_m1 GCLK_m4} –group {GCLK_m2 GCLK_m3}, set_clock_groups –asynchronous –group { GCLK_n1 GCLK_n2} –group {GCLK_n3 GCLK_n8}.

[0038] As mentioned above, by identifying the table, we can generate the timing constraints we need.

[0039] Example 2 This embodiment discloses an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the method for automatically generating timing constraints as described in Example 1 when executing a program stored in the memory.

[0040] Example 3 This embodiment discloses a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for automatically generating timing constraints as described in Embodiment 1 is implemented.

[0041] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A method for automatically generating timing constraints, characterized in that: The following steps are involved: S01) Determine the actual requirements for creating a clock based on the design document; S02) Generate a clock list based on actual needs. The contents of the clock list include PLL source, clock type, clock name, source path, master clock name, master clock source path, frequency, master clock duty cycle, derived clock duty cycle, frequency division coefficient, whether there is a cross-clock requirement, and the relationship between the created clocks; S03), configure the script, specify the clock list that the script needs to read, and execute the script; S04) The script traverses all options in the clock list, generates timing constraints, and automatically completes the GCA check.

2. The method for automatically generating timing constraints according to claim 1, characterized in that: Clock types include master clocks and derived clocks. A derived clock is always a clock generated from a master clock. The master clock and derived clock are represented by different symbols in the clock list.

3. The method for automatically generating timing constraints according to claim 2, characterized in that: When the clock type is the main clock, the corresponding derived clock duty cycle and frequency division coefficient are empty.

4. The method for automatically generating timing constraints according to claim 2, characterized in that: When the clock type is a derived clock, the corresponding main clock duty cycle is empty.

5. The method for automatically generating timing constraints according to claim 1, characterized in that: When there is a need for cross-clock domain clocks, the cross-clock domain clocks of the derived clocks are created synchronously.

6. The method for automatically generating timing constraints according to claim 1, characterized in that: The relationship between the created clocks includes whether the clocks are in the same group. The clocks in the same group are synchronized, and the clocks in different groups are asynchronous.

7. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, and the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing the method for automatically generating timing constraints as described in any one of claims 1 to 6 when executing a program stored in a memory.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for automatically generating timing constraints according to any one of claims 1 to 6 is implemented.

Images