Generation method of circuit simulation model, electronic equipment and storage medium

Abstract

The embodiment of the invention relates to a circuit simulation model generation method, electronic equipment and a storage medium. The generation method comprises the steps that simulation optimization is carried out on preset model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values of target parameters related to the preset model parameters, and the semiconductor process devices have different sizes; in response to the fact that the simulation values of the target parameters meet the preset standard, the models corresponding to the simulation values meeting the preset standard are determined as corresponding optimization models; arranging the grid points representing the optimization models into a matrix based on the size of each semiconductor process device; and based on the relationship between the model parameters of the optimization model represented by each lattice point in the matrix and the corresponding size of the semiconductor process device, determining a circuit simulation model used for simulating the semiconductor process device of each size. According to the technical scheme, the circuit simulation models of the semiconductor process devices of various sizes can be efficiently generated.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuits, and more particularly, to a method for generating a circuit simulation model, an electronic device, and a storage medium. Background Art

[0002] Design Technology Co-Optimization (DTCO) is gaining more and more attention in the industry during the development of new processes. Usually, when developing new processes, semiconductor process device simulation (Technology Computer Aided Design, TCAD) is used to simulate processes and devices to obtain the electrical characteristics of the devices.

[0003] The finite element method used by TCAD requires the generation of a large number of grids to solve discrete equations, which makes it impractical to simulate large-scale circuits. Therefore, it is necessary to fit the electrical simulation results of TCAD through the Simulation Program with Integrated Circuit Emphasis (SPICE) model to obtain the SPICE model for PPA (performance, process, area) simulation verification or even circuit-level simulation verification. In other words, TCAD is used for early process simulation to obtain device characteristics, and SPICE-level circuit simulation is required in the later stage. How to achieve the link from TCAD to SPICE has become a problem that plagues the industry. Summary of the invention

[0004] According to an example embodiment of the present disclosure, a circuit simulation model generation scheme is provided to at least partially overcome the above or other potential drawbacks.

[0005] According to one aspect of the present disclosure, a method for generating a circuit simulation model is provided, the method comprising: simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, the plurality of semiconductor process devices having different sizes respectively; in response to the simulation values ​​of the target parameters satisfying predetermined standards, respectively determining models corresponding to the simulation values ​​satisfying the predetermined standards as corresponding optimization models; arranging grid points representing the respective optimization models into a matrix based on the sizes of the respective semiconductor process devices; and determining a circuit simulation model for simulating semiconductor process devices of respective sizes based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the sizes of the corresponding semiconductor process devices.

[0006] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform an action when executed by the processor, the action including: performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes; in response to the simulation values ​​of the target parameters satisfying predetermined standards, respectively determining the models corresponding to the simulation values ​​satisfying the predetermined standards as corresponding optimization models; arranging the grid points representing the respective optimization models into a matrix based on the sizes of the respective semiconductor process devices; and determining the circuit simulation model for simulating semiconductor process devices of respective sizes based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the sizes of the corresponding semiconductor process devices.

[0007] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of multiple semiconductor process devices includes: taking a curve representing the electrical characteristics of the semiconductor process device obtained from semiconductor process device simulation TCAD or from wafer acceptance test WAT measurement as an optimization target; and simulation optimization of predetermined model parameters related to the target parameters corresponding to the points on the curve, so that the difference between the simulation value corresponding to the target parameter and the target value represented by the point on the curve becomes smaller during the iterative simulation process.

[0008] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of multiple semiconductor process devices includes: taking given values ​​of predetermined electrical parameters of the semiconductor process devices as optimization targets; and simulation optimization of predetermined model parameters related to the predetermined electrical parameters so that the difference between the simulation value and the given value of the predetermined electrical parameters becomes smaller during the iterative simulation process.

[0009] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of multiple semiconductor process devices includes: constructing a Jacobian matrix of each predetermined model parameter, wherein each predetermined model parameter serves as an input variable of a loss function in the Jacobian matrix, and the loss function is a function of the difference between a simulation value of a target parameter and a target value represented by a point on a curve, or a function of the difference between a simulation value of a predetermined electrical parameter and a given value; and iteratively optimizing the predetermined model parameters in response to changes in the value of the loss function to obtain optimized model parameters.

[0010] In some embodiments, the simulation value of the target parameter is determined to meet a predetermined criterion based on any one of the following: the value of the loss function during the simulation process is less than a predetermined threshold; the ratio of the simulation values ​​of two iterations before and after the simulation process is less than a predetermined threshold; and the number of iterations or the iteration time during the simulation process reaches a predetermined threshold.

[0011] In some embodiments, arranging grid points representing various optimization models into a matrix based on the size of various semiconductor process devices includes: arranging rows of grid points along a first direction based on first size parameters of various semiconductor process devices; and arranging columns of grid points along a second direction based on second size parameters of various semiconductor process devices.

[0012] In some embodiments, based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, determining the circuit simulation model for simulating semiconductor process devices of various sizes includes: determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix; and determining the combination of each arbitrary model and each optimization model corresponding to each grid point as the circuit simulation model.

[0013] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix includes: performing interpolation processing between the grid points in the matrix to determine the model corresponding to any position within the range corresponding to the matrix except for the grid points.

[0014] In some embodiments, interpolation processing is performed between each grid point in the matrix to determine the model corresponding to any position within the range corresponding to the matrix except for each grid point, including: constructing a set of equations based on a predetermined number of adjacent grid points within a predetermined range in the matrix, wherein each equation in the set of equations respectively represents the relationship between parameters related to the size characteristics of each semiconductor process device and the model parameters of the model represented by each grid point; solving characteristic parameters that characterize the commonality of the optimization models represented by each grid point in the matrix based on the set of equations; and determining the model corresponding to a point at any position in the matrix based on the characteristic parameters and the coordinates of the point at any position within the predetermined range.

[0015] In some embodiments, the parameters related to the characteristics of each semiconductor process device include at least the following items: a base parameter, which is a common parameter of each equation in the set of equations; a first size parameter; and a second size parameter.

[0016] In some embodiments, the semiconductor process device is a fin field effect transistor, the first size parameter is the length of the fin field effect transistor, the second size parameter is the number of fins of the fin field effect transistor, and wherein the parameters related to the characteristics of the semiconductor process device also include a third parameter, which is the product of the length and the number of fins.

[0017] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix includes: selecting a square corresponding to the size of the semiconductor process device from the matrix based on the first size parameter, the second size parameter, and the third size parameter corresponding to the semiconductor process device at any position; and constructing a set of equations based on the model parameters and size parameters of the optimized model corresponding to the grid points of the selected squares; and solving the set of equations to determine the model parameters of the model corresponding to any point, so as to determine any model corresponding to the point at any position.

[0018] In some embodiments, before simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices, the method further includes: configuring a strategy for optimizing the model parameters and / or a strategy for secondary optimization of key target parameters in a target file; and selecting model parameters to be optimized based on the strategy for optimizing the model parameters.

[0019] In some embodiments, after the simulation value of the predetermined model parameter meets the predetermined standard, it also includes: based on the optimization flag indication, determining to perform secondary optimization on the key target parameter to generate a further optimized model.

[0020] In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0021] It will be understood from the following description that the technical solution of the present disclosure can efficiently generate circuit simulation models of semiconductor process devices of various sizes.

[0022] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the DTCO process is shown; Figure 2 A schematic diagram showing an example environment in which embodiments of the present disclosure can be implemented; Figure 3 A flow chart showing a method for generating a circuit simulation model according to some embodiments of the present disclosure is shown; Figure 4 A schematic diagram showing a fitting curve according to some embodiments of the present disclosure; Figure 5 A schematic diagram showing a fitting curve according to some embodiments of the present disclosure; Figure 6 A schematic diagram showing a fitting curve according to some embodiments of the present disclosure; Figure 7 A schematic diagram showing a fitting curve according to some embodiments of the present disclosure; Figure 8 A schematic diagram showing the difference between a simulated value and a target value of a target parameter according to some embodiments of the present disclosure; Fig. 9 A schematic structural diagram of a fin field effect transistor according to some embodiments of the present disclosure is shown; Fig.10 A schematic diagram of a grid matrix according to some embodiments of the present disclosure is shown; Fig.11 A schematic diagram showing a grid point according to some embodiments of the present disclosure; Fig.12 A schematic diagram showing a data structure of a target file according to some embodiments of the present disclosure; Fig.13 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown.

[0024] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0025] The principles of the present disclosure will be described below with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals may be used in the figures where feasible, and similar or identical reference numerals may represent similar or identical functions. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods described herein may be adopted without departing from the principles of the present invention described herein.

[0026] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0027] SPICE is a language simulator software used for circuit description and simulation. It is used to detect the integrity of circuit connections and functions, as well as to predict the behavior of circuits. In order to perform SPICE simulation, a device-level SPICE model must be established first, such as the SPICE model of MOS devices, so that there is a specific mathematical model in the simulation program to describe the corresponding components. The SPICE model of components is closely related to the semiconductor manufacturing process, and the corresponding device characteristics can be simulated through the SPICE model of components.

[0028] SPICE models usually consist of two parts: model equations and model parameters. When modeling, SPICE modeling engineers are usually required to manually change the values ​​of model parameters in the model equations, and then compare the test data with the simulation data until the value of the model parameter that is closest to the test data and the simulation data is found. This method requires repeated changes in the values ​​of model parameters, and each change requires comparison of test data with simulation data, which is time-consuming and labor-intensive, and requires a lot of manpower for modeling work. It is also impossible to respond quickly to adjustments to device process parameters.

[0029] Taking the MOS tube as an example, the initial SPICE model of the MOS tube has a model equation for characterizing the DC characteristics of the MOS device, a model equation for characterizing the AC characteristics of the MOS tube, and a model equation for characterizing other characteristics of the MOS tube (temperature characteristics, noise characteristics, layout characteristics, etc.), each model equation may include at least one equation, and each equation may include at least one model parameter. The model parameters in the initial SPICE model can be used to characterize the electrical characteristics of the target device, such as the model parameters for characterizing the saturation current Idsat, linear current Idlin, off current Idoff, linear threshold voltage Vtlin, and saturation threshold voltage Vtsat of the MOS tube; accordingly, the model parameters in the initial SPICE model can also be used to characterize the physical characteristics of the target device, such as the model parameters for characterizing the channel length, channel width, and gate oxide thickness of the MOS tube, etc.

[0030] Usually, the process design package that designers get is called PDK (Process Design Kit), which is a process simulation package provided by the wafer foundry to the design company. Designers use the process device package in PDK to simulate and design circuits. SPICE model is an important part of DK. Design companies use simulation software (HSPICE) to call model cards and implement device simulation and design in various situations by adding stimulus conditions. Models are generally abstract mathematical formulas, and model cards record the coefficients of abstract formulas in text files, such as forming model cards.

[0031] At present, the SPICE models in the process industry are all based on the Berkeley BSIM model. Among them, the planar model is mainly based on BSIM3 and 4; the model for FINFET is the Berkeley Short-channel IGFET Model – CommonMulti-Gate, referred to as BSIMCMG. The BSIM model can accurately describe the electrical characteristics of the device at various voltages and temperatures in an analytical way through a series of mathematical and physical formulas. Due to the numerous parameters and complex formulas of these models, the current practice in the industry is that EDA companies incorporate these complex mathematical models into the simulation software. Wafer foundries only need a card that provides model coefficients, that is, a model card. Users use SPICE simulation software to call the model card for circuit simulation. According to the type of model card, it can be divided into: point model of a single size (Point Model), global model of multiple sizes (Global Model) and BIN model (BIN Model). As the process window of advanced processes narrows, designers have high requirements for the accuracy of FINFET SPICE Models, usually compared with the target, vt~ (<1mv), id~ (<1%), that is, the gate voltage corresponding to a certain fixed value of current on the IV (current-voltage) curve, and the current corresponding to a certain fixed value of gate and drain. The traditional global model method can no longer meet the accuracy requirements.

[0032] For point models, one model card corresponds to a device of fixed size; for global models, one model card can cover devices of different sizes; BIN models integrate many point model cards into one model card. Electrical characteristics are usually integrated in the simulator, and the parameter coefficients that need to be adjusted are placed in the text file of the model card. The model card after parameter adjustment is obtained by adjusting the parameters and TCAD curve fitting.

[0033] The FINFET industry currently uses a model card in the form of a BIN model. The BIN model is a SPICE model. The model card records information such as the model parameters / IV / CV characteristics of the simulated device. At present, wafer foundries usually extract SPICE models based on existing silicon data or TCAD simulation data; or on the basis of the previous generation of technology nodes, reconstruct vt and id (Retarget, modify key indicator parameters) to obtain the model of the new node. However, for the early stage, wafer foundries usually use TCAD to establish a virtual FAB to obtain early simulation data. Whether it is based on the reconstruction of the existing model or the extraction of a new model, the parameters need to be constantly adjusted to make the simulation results of the model consistent with the target. Extracting SPICE models requires engineers to have certain relevant experience and be familiar with the response direction of each parameter. Even engineers with more experienced SPICE Mode need to spend a lot of time iterating back and forth to get a more satisfactory result, which has become one of the important factors restricting the DTCO development cycle.

[0034] From the perspective of advanced process research and development, the entire process from TCAD to SPICE has become an important part of DTCO for each wafer foundry. Domestic model extraction software such as BSIMPro Plus is still mostly in the manual parameter adjustment stage, and there is no data interface with TCAD. Manual parameter adjustment is to manually adjust the parameters according to the curve or the target value of vt_lin, vt_sat, idlin, idsat. Each time a parameter model is manually adjusted, a new set of data will be simulated. By comparing the simulation results with the curve and with vt_lin, vt_sat, idlin, idsat, the direction of the parameters to be adjusted is manually judged, and better results are gradually fitted. The parameters to be optimized are selected from the model card. For example, if the model card has 100 parameters, 10 parameters can be selected as parameters to be manually adjusted.

[0035] The targets or sweep curves for different technology nodes may vary greatly (a sweep curve refers to a series of continuous curves, such as voltage, current, or capacitor-voltage curves, etc.). Often, one set of strategies cannot be used to deal with all process situations. Therefore, it is usually necessary to make certain modifications to the optimization strategy for a certain process or project in order to achieve better optimization results.

[0036] In view of this, the present disclosure provides an improved solution.

[0037] The embodiment of the present disclosure provides an improved method for generating a circuit simulation model. The method includes: simulating and optimizing predetermined model parameters of respective initial models of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes respectively; in response to the simulation values ​​of the target parameters satisfying predetermined standards, respectively determining the models corresponding to the simulation values ​​satisfying the predetermined standards as corresponding optimization models; arranging the grid points representing the respective optimization models into a matrix based on the sizes of the respective semiconductor process devices; and determining the circuit simulation model for simulating semiconductor process devices of various sizes based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the sizes of the corresponding semiconductor process devices.

[0038] Some embodiments of the present disclosure obtain simulation models of devices of different sizes (eg, representative sizes) and quickly construct a model covering devices of all sizes based on the association between models of various sizes.

[0039] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 The basic process of DTCO is known in the industry and is briefly described below.

[0041] At block 102, a new technical standard is provided.

[0042] At block 104 , TCAD simulation is performed, which includes simulation of transistors and interconnects or connection relationships, and can output, for example, a curve of device characteristics.

[0043] At block 106 , a PDK is shown, which includes DR (design rules), standard cells, and models. The models include compact models and RC (resistance and capacitance).

[0044] At block 108 , a SPICE simulation of the circuit is shown being performed.

[0045] At block 110 , the output from the circuit simulation of block 108 is fed back to block 102 for co-optimization.

[0046] Figure 2 2 is a schematic diagram of an example environment 200 in which embodiments according to the present disclosure can be implemented. Figure 2 As shown, the example environment 200 includes a computing device 210 and a client 220 .

[0047] In some embodiments, the computing device 210 may interact with the client 220. For example, the computing device 210 may receive an input message from the client 220 and output a feedback message to the client 220. In some embodiments, the input message from the client 220 may be data of a semiconductor process device. The computing device 210 may perform corresponding mathematical operations on the data of the semiconductor process device and output corresponding operation results to the client 220.

[0048] In some embodiments, computing device 210 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant (PDA), a media player, etc.), consumer electronics, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0049] It should be understood that the structure and function of the example environment 200 are described for exemplary purposes only and are not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. The environment is merely illustrative and is not intended to limit the application environment of the embodiments of the present disclosure.

[0050] In order to explain the principle of the disclosed solution more clearly, the following will refer to Figure 4 Let's describe it in more detail.

[0051] Figure 3 A flow chart of a method 300 for generating a simulation model (eg, a SPICE model) according to some embodiments of the present disclosure is shown.

[0052] At block 302 , simulation optimization is performed on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes.

[0053] In some embodiments, models of semiconductor process devices of different sizes may be obtained, so as to construct a model covering devices of various sizes by using the models of devices of these different sizes (for example, devices of representative sizes may be selected as needed).

[0054] In some embodiments, before simulation, a strategy for optimizing model parameters is configured in the target file, and a strategy for secondary optimization of key target parameters may also be configured. Model parameters to be optimized may be selected based on the strategy for optimizing model parameters. The target file is described in detail later.

[0055] In some embodiments of the present disclosure, a data structure is designed based on the json data format. The data structure can be used in the target file. The data structure makes the program for reading the data interface simple. The above data structure has the advantages of convenient definition, simple format, and easy later code maintenance and upgrade.

[0056] The sweep curve can be named according to the file name of sweep_curve_x.json, where "x" is an integer greater than or equal to 0. It is read and parsed through the load interface of ttspro (TCAD TO SPICE Pro) and forms a tree structure on the GUI. By clicking the name of the curve in the tree structure, the information of each curve can be accessed and displayed in the drawing area of ​​the Graphical User Interface (GUI).

[0057] The data structure of the object file consists of the following parts (referred to as part 1):

[0058] The data structure of the target file first defines parameters, namely parameters, which represent the policy information that needs to be filled in. The parameters include: "columns", regions, parameters, value, scale, factor, and format.

[0059] Columns includes region1 to region5. Regions includes the column array after region1 to region5, for example, [0, 0.25].

[0060] It should be understood that the various parameters included in the data structure shown in the embodiment of the present disclosure are illustrative and are not intended to limit the scope of the present disclosure. Various changes can be made to the various parameters therein according to actual needs, such as addition, deletion, change, etc.

[0061] In some embodiments, the target file can be used to configure the optimization strategy. Specifically, the target file can be used to configure the simulation conditions and the optimization strategy. The target file can also define the settings of the parameters for manual parameter adjustment and drawing. The target file can be imported into the simulation model through the target loading interface on the GUI.

[0062] The second parameters in the data structure (part 1) shown above represent the model parameters that need to be optimized. For example, phig, cdsc, Uθ, ua, etc. Regions represent the x-axis range of the IV (current-voltage) curve and the CV (capacitance-voltage) curve.

[0063] For Step 1 shown in the data structure, the first step is to optimize the drain current curve of id_vg1.

[0064] The meaning of each parameter is as follows: Phig: Gate work function, which has a linear relationship with vt_lin. When phig increases, vt_lin increases, and when phig decreases, vt_lin decreases. Cdsc: coupling capacitance between S / D and channel; Uθ: low field mobility; Ua: phonon / surface roughness scattering parameter (phonon / surface roughness scattering parameter); Eu: phonon / surface roughness scattering parameter (phonon / surface roughness scattering parameter); Etamob: effective field parameter; In some embodiments, a strategy for performing secondary optimization on key target parameters is also configured in the target file, and the model parameters can be secondary optimized based on the strategy to obtain a further optimized model. See the following data structure (referred to as part 2):

[0065] The data structure shown here shows the settings for secondary optimization of key indicators (key target parameters).

[0066] att_flag: indicates whether to enable attribute (performance) optimization; att_mod: mode; att_param: parameter; attribute: optimized parameter; att_scale: data scaling factor; att_target: target; vt_lin: linear threshold voltage; vt_sat: saturation threshold voltage Idlin: linear current; idsat: saturation current; para_bounds: bounds of the optimization parameters.

[0067] For example, you can select specific parameters to modify (optimize) specific vt_lin, vt_sast, idlin, idsat. For example: ; That is, use Phig to correct vt_lin; ; That is, use U0 to correct idlin; ; That is, use Dvtp0 to correct vt_sat.

[0068] In addition, it should be understood that if the electrical parameters shown in the present disclosure are not described in detail or their Chinese names are not given, they can be understood according to the common understanding in the electrical field.

[0069] In some embodiments, the information to be optimized can be imported into a newly created project in the software in text format, and the corresponding "run" button can be clicked to perform automatic calibration on the parameters, and the calibration results can be saved in a folder. Automatic calibration is to automatically optimize the parameters to be optimized. For example, the target value of vt_sat is 100mv, the vt_sat of the model before optimization is 50mv, and after optimization it is 99mv.

[0070] The information that needs to be optimized refers to which curve: id_vg1, id_vg2, id_vd, etc. and which attribute target vt_lin, vt_sat, idlin, idsat, etc. need to be optimized. For the data structure (part 1), the information that needs to be optimized is the content after the step character, which can be defined by the operator.

[0071] To optimize a device with a scan curve, you can first optimize the curve of the device according to the settings in the target file. For example, you can optimize the current, voltage, etc. of each curve, and automatically optimize according to the bias conditions set in the target file.

[0072] In some embodiments, after the simulation value of the predetermined model parameter meets the predetermined standard, it can be determined based on the optimization flag indication to perform secondary optimization on the key target parameters to generate a further optimized model. For example, after the curve is fitted to the expected standard, it is determined whether to perform secondary optimization on key targets (key target parameters) such as vt_lin, vt_sat, idlin, idsat, swing_lin, etc. according to the optimization flag set by the user.

[0073] In some embodiments, the curve is a TCAD simulation curve or a wafer acceptance test (WAT) curve. If the scan curve is used as the optimization target value, then the point on the curve represents the target.

[0074] In some embodiments, the RMS can be calculated to determine whether the curve fits the expected standard. Specifically, the size of the RMS can be used to determine whether the curve meets the expected standard.

[0075]

[0076] where y mi is the value of the i-th point of the model, y ti is the simulation value of the i-th point of the target, n and N are positive integers, and they are equal in this formula, both representing the number of points.

[0077] The model card is usually a text file ending with "xx_yy.mod". "xx" is an arbitrary string and "yy" is an integer greater than or equal to 0. Through the load mode (load mod) interface on the GUI, the model to be optimized is imported into the project, and the adjustable model parameters are displayed in the parameter adjustment area of ​​the GUI through GUI analysis; at the same time, the parameters can be adjusted manually.

[0078] In some embodiments, a trust region reflective curve fitting algorithm (TRF) may be used. In some embodiments, since the optimized parameters have limits (the limits can be set in the target file), when the parameters are not within a reasonable range, the optimization results will be very different from the target, making it impossible to proceed with the subsequent optimization, resulting in optimization failure. This algorithm can be used to solve the boundary problem of parameters. For example, after setting the range, the parameters can only be adjusted within the set range during optimization, and cannot exceed this range.

[0079] In addition to the trust region reflection curve fitting algorithm mentioned above, in some embodiments of the present disclosure, the Levenberg-Marquardt (LM for short) algorithm can also be used. The LM algorithm is one of the optimization algorithms. Optimization is to find the parameter vector that minimizes the function value. Specifically, the algorithm is an estimation method for least squares estimation of regression parameters in nonlinear regression. This method is a method that combines the steepest descent method and the linearization method (Taylor series). Because the steepest descent method is applicable to the situation where the parameter estimate is far from the optimal value at the beginning of the iteration, and the linearization method, that is, the Gauss-Newton method, is applicable to the later stage of the iteration, when the parameter estimate is close to the optimal value. The combination of the two methods can find the optimal value more quickly.

[0080] In some embodiments, a sweep curve or an attribute value set in a target file may be used as an optimization target value, and a parameter to be optimized may be selected as an input value.

[0081] In some embodiments, a curve representing the electrical characteristics of a semiconductor process device obtained from semiconductor process device simulation TCAD or from wafer acceptance test WAT measurement can be used as an optimization target; predetermined model parameters related to the target parameters corresponding to the points on the curve are simulated and optimized so that the difference between the simulation value corresponding to the target parameter and the target value represented by the point on the curve becomes smaller during the iterative simulation process.

[0082] In some embodiments, a given value of a predetermined electrical parameter of a semiconductor process device can be used as an optimization target; and a predetermined model parameter related to the predetermined electrical parameter can be simulated and optimized so that the difference between the simulation value and the given value of the predetermined electrical parameter during the iterative simulation process becomes smaller.

[0083] The implementation of the optimization algorithm is described in detail below.

[0084] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of a plurality of semiconductor process devices may include: constructing a Jacobian matrix of each predetermined model parameter, wherein each predetermined model parameter serves as an input variable of a cost function in the Jacobian matrix, and the cost function is a function representing the difference between a simulated value of a target parameter and a target value represented by a point on a curve, or a function representing the difference between a simulated value of a predetermined electrical parameter and a given value; iteratively optimizing the predetermined model parameters based on changes in the value of the loss function to obtain optimized model parameters.

[0085] In some embodiments, a simulator is used to perform simulation, construct a Jacobian matrix J(x), make a difference between the target value and the simulation result, and calculate the square sum of the difference as the right-hand side term f(x) of equation (1). The final optimization result is obtained by setting the number of iterations.

[0086]

[0087] Where x is the parameter in the model to be optimized as the input value mentioned above (may be called model parameter), for example, Phig; Indicates the amount of parameter change required for optimization each time, that is, the difference between the two fitting x values. If the input parameter is Phig, then It represents the change of Phig each time during the optimization process; f(x) is the defined loss function, which is used to indicate the difference between the target value and the simulation value. Specifically, it is to calculate the square sum of the difference between the target value and the simulation value of each point.

[0088] where the Jacobian matrix can take the following form:

[0089]

[0090] Among them, x1 to x n They represent the first parameter to be optimized to the nth parameter to be optimized; f m Represents the mth point on a curve; y1 to y m The specific calculation method of the Jacobian matrix itself is well known and will not be described here.

[0091] At block 304 , in response to the simulation values ​​of the target parameters satisfying predetermined criteria, the models corresponding to the simulation values ​​satisfying the predetermined criteria are respectively determined as corresponding optimization models.

[0092] In some embodiments, it can be determined that the simulation value of the target parameter meets the predetermined criteria based on any one of the following: the value of the loss function during the simulation process is less than a predetermined threshold; the ratio of the simulation values ​​of two iterations before and after the simulation process is less than a predetermined threshold; the number of iterations or the iteration time during the simulation process reaches a predetermined threshold.

[0093] The final optimization results obtained through simulation optimization can be used for SPICE simulation. After optimization, optimized models of devices of various sizes can be generated. By further processing these models, SPICE models for circuit-level simulation can be realized.

[0094] During the optimization process, whether the model parameter (such as Phig) is optimized is determined by comparing the target value of the target parameter (such as vt_lin) with the simulation value. For example, if the difference between the two is less than the predetermined threshold, it is considered that the curve fitting meets the expected requirements. It can be seen that the optimization of the parameter Phig to be optimized is measured by whether the simulation value of another quantity vt_lin related to Phig meets expectations. As mentioned earlier, Phig and vt_lin are linearly related. If phig increases, vt_lin increases, and if phig decreases, vt_lin decreases. Therefore, the optimization of the model parameter (such as Phig) can be achieved by comparing the target value of the target parameter (vt_lin) with the simulation value.

[0095] Refer to the following Figure 4 Give a description. Figure 4 A schematic diagram of a fitting curve according to some embodiments of the present disclosure is shown. Figure 4 The curve of fitting Vt_lin as the target parameter is shown in FIG. vt_lin is usually the x-coordinate value corresponding to a point on the curve, which is used to measure whether the fitting at this point is accurate. Figure 4 As shown, find the point with a value of 1e-7*w / L from the curve, and then find the corresponding x-coordinate value, which can indirectly measure whether the curve fitting is accurate.

[0096] Figure 5 Schematic diagram of a fitting curve according to some embodiments of the present disclosure is shown. Specifically, Figure 5 The schematic diagram of the fitting curve of ID-VG is shown in FIG. The horizontal axis is vgs and the vertical axis is id. The fitting result of id_vg at vd of 0.05V is obtained by optimization. Among them, vd represents the drain terminal voltage and id represents the drain current.

[0097] Figure 6 Schematic diagram showing a fitting curve according to some embodiments of the present disclosure. Specifically, Figure 6 The schematic diagram of the fitting curve of ID-VG is shown in Figure 1. Its horizontal axis is vgs and its vertical axis is log(id). The fitting result of id_vg at vd of 0.05V is obtained by optimization.

[0098] Figure 7 A schematic diagram of a fitting curve according to some embodiments of the present disclosure is shown. Figure 7 A schematic diagram of the fitting curve of ID-VG is shown in FIG. The horizontal axis is vgs, and the vertical axis is the derivative form of id and Vgs. The fitting result of id_vg at vd of 0.05V is obtained by optimization.

[0099] pass Figures 5 to 7The three forms in can be used to view the fitting results in multiple dimensions. When the data is relatively small, it is necessary to take the logarithm. By checking whether the curve after derivation is consistent, the fitting results can be further understood. W and L can represent the width and length of the MOS transistor respectively, and T represents the temperature. -09 and -08 are used as exponents in the upper right corner of e, which is a scientific expression of numbers.

[0100] Figure 8 Schematic diagram showing the difference between the simulated value and the target value of the target parameter according to some embodiments of the present disclosure. Figure 8 As shown, the error between the simulation result and the target is shown. The target here refers to the key parameter indicators: vt_lin, vt_sat, idling, idat, etc. The fitting accuracy can be determined based on the error, and then it can be judged whether the model is optimized to meet expectations.

[0101] Fig. 9 The structure diagram of a fin field effect transistor 900 according to some embodiments of the present disclosure is shown. The fin field effect transistor (Fin Field-Effect Transistor, FinFET for short) 900 is a complementary metal oxide semiconductor transistor, which includes a substrate 902, a gate 906 and a silicon dioxide (which is a shallow trench isolation region) 904. Fig. 9 As can be seen in FIG. 9 , the fin field effect transistor 900 has three fins. The present disclosure does not limit this, and the solution of the embodiments of the present disclosure is applicable to fin field effect transistors with any number of fins. In some embodiments of the present disclosure, the method for determining the circuit simulation model will be described by taking the fin field effect transistor as an example.

[0102] Back to Figure 3 At block 306 , the grid points representing each optimization model are arranged into a matrix based on the size of each semiconductor process device.

[0103] In some embodiments, the rows of grid points may be arranged along a first direction based on a first size parameter of each semiconductor process device, and the columns of grid points may be arranged along a second direction based on a second size parameter of each semiconductor process device. The first size parameter may be the length of the device, the second size parameter may be the width of the device, and the second size parameter may also be, for example, for a fin FET, the second size parameter may also be nfin, i.e., the number of fins.

[0104] SPICE models usually need to cover different sizes. It is usually unrealistic to establish multiple sets of corresponding model cards through many size curves or target information. Therefore, many parameters in the BSIM model are related to length (length), number of fins (nfin) and length*nfin. For two-dimensional devices, the length and width are generally continuous, and the electrical characteristics are monotonous or smooth in the length and width directions, so the global model can achieve a better fitting effect. For three-dimensional devices, such as FINFET, the length and NFIN are discrete and the electrical characteristics vary greatly, and the accuracy of the SPICE model is high. Therefore, the global model cannot meet the fitting results of all FINFET size information. Therefore, the BIN model is particularly important.

[0105] In some embodiments of the present disclosure, the BIN model is to first fit the M*N grid size one by one, and then fit the obtained model card according to Fig.10 In other words, each model card is arranged as a grid point. This forms a binning-like structure, where M*N corresponds to L and NFIN respectively.

[0106] In some embodiments of the present disclosure, model cards of each size can be automatically extracted and then automatically merged into a Bin model. For each small unit BIN in the Bin model, the corresponding model parameters such as vsat are solved by equations (2)-(5) in the following text to establish the relationship between the parameters in each BIN and the size in the BIN. One model card can accurately express the information of models of all sizes. This is described in detail later.

[0107] Usually, the SPICE model is extracted together with multiple devices. For example, a complete SPICE model of a 6T structure of a static random access memory (SRAM) needs to extract 6 devices to form a model card. Due to the symmetry of SRAM itself, only three devices need to be extracted (PD, PG, PU). For logic devices, the target number of devices is usually large and interpolation simulation is generally performed, that is, the size that is not in the target is interpolated. Therefore, it is often unrealistic to obtain the model card of all matrices through point models. On the other hand, due to the discreteness of the length (Length) and NIFN of FINFET, the traditional global model cannot meet the accuracy requirements. However, it is precisely because of the discreteness of FINFET size that some representative size models can be obtained first, and then the problem of internal interpolation of FINFET (for example, length, nfin) can be solved through the BIN model.

[0108] In some embodiments, the number of point models that need to be established in the BIN model needs to be a matrix distribution of M*N, where M and N are both integers greater than or equal to 2. M can be the number of Fins or the number of Lengths. In some embodiments, the defined BIN Map (which can be called a grid map) can be based on Fig.10 Defined in the manner shown.

[0109] See also Fig.10 , Fig.10 A schematic diagram of a grid matrix according to some embodiments of the present disclosure is shown. Fig.10 In the grid matrix shown, there are 9 bins, which can be called squares in this article, and the squares are numbered from 1 to 9. In addition, a total of 16 grid points are shown in the matrix. Each grid point corresponds to a model of a device of a certain size. In other words, the devices corresponding to the 16 grid points have different sizes. The horizontal axis LG represents the length of the device, and the lengths of the devices corresponding to each grid point are 0.009um, 0.016um, 0.032um, and 0.072um respectively. The vertical axis NFIN represents the number of fins. As shown Fig.10 As shown, 2, 3, 4, 6 are shown, that is, the number of fins is 2, 3, 4, 6 respectively. Figure 2 The matrix is ​​arranged and numbered 1, 2, 3, 4, 5, 6, 7, 8, 9. In this way, each grid point corresponds to a model, or corresponds to a model card of a model, where the model card records information such as the model parameters of the model.

[0110] The following is an example of the position of the first BIN (i.e., bin numbered 1): the coordinates of the four vertices of the bin are (0.009, 2), (0.009, 3), (0.016, 2), and (0.016, 3). The following BINs follow the order from right to left. It should be understood that the arrangement of the grid points shown here is schematic, and the present disclosure is not limited to this, and the arrangement can be modified as needed.

[0111] Fig.11 A schematic diagram of a grid point according to some embodiments of the present disclosure is shown. The P parameter of bin1 in the smallest unit of BIN is shown, that is, points P1, P2, P3 and P4, which are the values ​​of a parameter in the model corresponding to each grid point. For a given model, its various parameters are known.

[0112] Back to Figure 3At block 308, based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, a circuit simulation model for simulating semiconductor process devices of various sizes is determined.

[0113] In some embodiments, based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, determining the circuit simulation model for simulating semiconductor process devices of various sizes may include: determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix; and determining the combination of each arbitrary model and each optimization model corresponding to each grid point as the circuit simulation model. In other words, by determining the model corresponding to a point at any position between each grid point and combining it with the known model of each grid point, a model for circuit simulation of devices of various sizes can be obtained.

[0114] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix may include: performing interpolation processing between the grid points in the matrix; and determining the model corresponding to any position within the range corresponding to the matrix except for the grid points through interpolation processing.

[0115] In some embodiments, interpolation processing is performed between each grid point in the matrix to determine the model corresponding to any position other than each grid point within the range corresponding to the matrix, which may include: constructing a set of equations based on a predetermined number of adjacent grid points within a predetermined range in the matrix, wherein each equation in the set of equations respectively represents the relationship between parameters related to the size characteristics of each semiconductor process device and model parameters of the model represented by each grid point; solving characteristic parameters representing the commonality of the optimization model represented by each grid point in the matrix based on the set of equations; in addition, determining the model corresponding to a point at any position in the matrix based on the characteristic parameters, parameters related to the size characteristics corresponding to the adjacent grid points, and the coordinates of the point at any position within the predetermined range. For example, the model parameters of the model corresponding to any position in a square grid can be solved based on the size parameters of the model corresponding to the position in the square grid and the parameter information of the model corresponding to each grid point of the square grid.

[0116] In some embodiments, the parameters related to the characteristics of each semiconductor process device may include at least the following items: a base parameter, which is a common parameter of each equation in the set of equations; a first size parameter; and a second size parameter. For example, if the semiconductor process device is a MOS tube, the first size parameter is its length L, and the second size parameter is its width W. It should be understood that the present disclosure is not limited to this, and the characteristic-related parameters may also be other parameters according to different device types.

[0117] In some embodiments, the semiconductor process device is a fin field effect transistor. In this case, the first size parameter is the length of the fin field effect transistor, the second size parameter is the number of fins of the fin field effect transistor, and the parameters related to the characteristics of the semiconductor process device also include a third parameter, which is the product of the length and the number of fins.

[0118] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix may include: selecting a square corresponding to the size of the semiconductor process device from the matrix based on the first size parameter, the second size parameter, and the third size parameter of the semiconductor process device corresponding to any position; and constructing a set of equations based on the model parameters and size parameters of the optimization model corresponding to the grid points of the selected square; solving the set of equations to determine the model parameters of the model corresponding to any point, so as to determine any model corresponding to the point at any position. In short, the model parameters of the model to be determined are determined by selecting a square where a model with a size feature close to that of the model to be determined is located.

[0119] Please refer to the attached Fig.10 This is further described. Fig.10 The grid matrix shown in , the parameters on the four grid points of each BIN satisfy the following relationship:

[0120]

[0121]

[0122]

[0123] Base has no physical meaning, only mathematical meaning. A Bin has four grid points, and four unknown parameters are required to determine the unique solution. X, Y, and Z represent three dimensions, namely the three parameters in the X / L direction, the Y / NFIN direction, and the Z / (L*NFIN) direction. L1 represents the length in the LG direction. Par1 is the value corresponding to a parameter in the model card corresponding to grid point 1. Taking phig=0.5 as an example, par1=0.5; par2, par3, and par4 are the values ​​corresponding to the phig parameters of the model cards of the other three grid points. All Binnable parameters in the model card (phig, u0, vsat, etc.) should satisfy the above relationship.

[0124] As is known in the industry, MOS has only two dimensions, namely length and width. Specifically, if there are two MOS, the Lg*NFIN are 5*5 and 6*8 respectively. So when put into the above formula, the size values ​​of L1 and L2 are 5 and 6 respectively. After solving the Base, X, Y, and Z equations through four MOS parameters (par1, par2, par3, par4) and size (L1*NFIN1, L2*NFIN2, L3*NFIN3, L4*NFIN4), X and Y are equivalent to the coordinates of a point in a bin (Z is not reflected in the bin diagram). In this way, for any point (X, Y) in the Bin, the corresponding parameter Par can be obtained by putting it into the above equation, or other equations in the equation group, that is, the model parameters in the model card are obtained. It is equivalent to being able to obtain the corresponding parameters in the model card for devices of any size. In other words, in this way, the model of the device of the corresponding size corresponding to the point at any position can be obtained. In the embodiments of the present disclosure, by adjusting the coefficients of the weight functions of these parameters (such as Base, X, Y, and Z), the extracted SPICE model can be completed with one model card at various sizes.

[0125] Regarding the calculation of Base, X, Y, and Z, take the first BIN as an example: Substitute the parameters and size information (length, nfin) of the model card corresponding to the four grid points of the BIN into (2)-(5), and you can get a set of four-variable linear equations. Solving them can get a model card of the BIN, and the parameter values ​​of the four grid points at the vertex are consistent with the parameter values ​​corresponding to the points of the synthetic BIN.

[0126] The BIN numbers can be moved in sequence according to the previously defined rules to construct a set of four-variable linear equations. In this way, the parameter relationships of all the divided BINs can be expressed by the set of equations in the form of (2)-(5). Finally, all the BIN models (coefficients in the model) are combined into a model card. By defining a selection function, the corresponding BIN can be selected at any size.

[0127] In some embodiments, the following selection function may be constructed according to the characteristics of the BIN structure:

[0128]

[0129]

[0130]

[0131]

[0132] The BIN number can be accurately matched to the model size through equations (6)-(10).

[0133] Formula (6) is a constructed selection function used to select a value in different size ranges. For example, when NFIN=2, is the device length less than l1? If it is less than l1, ( Fig.10 It can be seen that if it falls outside the matrix, the selected value is 1; if it is greater than l1 and less than l2, the selected value in the LG direction is 1; if it is greater than l2 and less than l3, the selected value in the LG direction is 2; if it is greater than l3 and less than l4, the selected value in the LG direction is 3. The last 3 in formula (6) means that when the value is greater than l4, it is 3. Similarly, the selected value in the NFIN direction also meets the above rules.

[0134] Formula (7) is a function for constructing a selection function to select a bin number under different bin numbers; it is used to determine which bin to select in the Y direction, i.e., the direction of NFIN, according to the number of fins of the device. For example, for a device with three fins, the third bin is selected in the Y direction. The last 10000 in formula (7) indicates that the default value is used when the value exceeds the limit.

[0135] Formula (8) is used to select bin_x of different sizes in the LG direction.

[0136] Formula (9) is used for the selection of bin_y in the NFIN direction.

[0137] Formula (10) is a combination of (8) and (9) to obtain the corresponding Bins under different sizes. Specifically, formula (10) is a function constructed based on the corresponding relationship between the selection function select4 and Bin, where the coefficient 3 can change according to the change of the actual number of sizes, for example Fig.10 In the illustrated embodiment, the number of bins in the x-direction is 3, which means that if the number of bins in the y-direction is moved by an integer +1, the bin number increases by 3. Accordingly, if the number of bins in the x-direction is 4, then if the number of bins in the y-direction is moved by an integer +1, the bin number increases by 4, and so on.

[0138] By defining a selection function, the corresponding bin can be selected at any size, so that a set of equations can be constructed based on the grid points of the selected bin and solved, thereby obtaining the model (model parameters) corresponding to any point.

[0139] In the above embodiments, FINFET is used as an example for explanation. It should be understood that the embodiments of the present disclosure are not limited thereto. In addition to FINFET, other devices may also apply the method of the embodiments of the present disclosure, such as IGBT, BJT, diode, resistor, MOS tube, etc. For these components, as mentioned above, the size parameters may include only length and width.

[0140] Some embodiments of the present disclosure provide a method for generating a circuit simulation model. It should be understood that the embodiments shown above are only for schematically illustrating the solutions of some embodiments of the present disclosure and are not intended to limit the present disclosure. The embodiments of the present disclosure may also have various other forms.

[0141] An electronic device is also disclosed in an embodiment of the present disclosure. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, and when the instructions are executed by the processor, the device performs an action, the action including: performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes respectively; in response to the simulation values ​​of the target parameters satisfying predetermined standards, respectively determining the models corresponding to the simulation values ​​satisfying the predetermined standards as corresponding optimization models; arranging the grid points representing the respective optimization models into a matrix based on the size of each semiconductor process device; and determining the circuit simulation model for simulating semiconductor process devices of various sizes based on the relationship between the model parameters of the optimization models represented by each grid point in the matrix and the size of the corresponding semiconductor process device.

[0142] The embodiment of the present disclosure also discloses a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method for generating a circuit simulation model according to the embodiment of the present disclosure is implemented.

[0143] The solutions of some embodiments of the present disclosure implement a method for automatic modeling of SPICE models, greatly shorten the modeling time, and have high accuracy. Provide powerful software and method support for DTCO. In addition, the method is applicable to the extraction of all SPICE models and is not restricted by the type of device (such as MOS type).

[0144] The BIN model establishment method proposed in some embodiments of the present disclosure can solve the problem of establishing a full matrix model under existing size conditions for SPICE models. The model card method is simple and can be used as a standard extraction (generation) process for SPICE models in wafer foundries.

[0145] In some embodiments of the present disclosure, a new model extraction concept is designed based on the TCAD+ platform for the extraction of TCAD to SPICE models, which can realize automatic extraction. For example, by configuring a target file combined with an optimization algorithm, the optimization effect can be automatically achieved, which greatly improves the process speed of DTCO and shortens the extraction time of SPICE models by more than 2 / 3.

[0146] Fig.12 A schematic diagram showing a data structure of a target file according to some embodiments of the present disclosure. Fig.12 The optimized data structure mentioned above is included in the figure, and the related parameters and specific parameter setting information are also shown. The specific content will not be described in detail here.

[0147] Fig.13 A schematic block diagram of an electronic device according to some exemplary embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0148] like Fig.13 As shown, the device 1300 includes a CPU 1301, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1302 or a computer program loaded from a storage unit 1308 into a random access memory (RAM) 1303. In the RAM 1303, various programs and data required for the operation of the device 1300 can also be stored. The CPU 1301, the ROM 1302, and the RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0149] Multiple components in the device 1300 are connected to the I / O interface 1305, including: an input unit 1306, such as a keyboard, a mouse, etc.; an output unit 1307, such as various types of displays, speakers, etc.; a storage unit 1308, such as a disk, an optical disk, etc.; and a communication unit 1309, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1309 allows the device 1300 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0150] The various processes and processing described above, such as method 300, may be executed by CPU 1301. For example, in some embodiments, method 300 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 1308. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1300 via ROM 1302 and / or communication unit 1309. When the computer program is loaded into RAM 1303 and executed by CPU 1301, one or more steps in method 300 described above may be performed.

[0151] The scheme according to the embodiment of the present disclosure may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing various aspects of the present disclosure are loaded. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network and / or a wireless network.

[0152] Various embodiments of the present disclosure have been described above, and the above descriptions are exemplary and are only optional embodiments of the present disclosure, not exhaustive, and are not intended to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel features or any novel combination of features disclosed herein, whether or not it relates to the same scheme in any claim currently claimed for protection. The applicant hereby informs that new claims may be formulated into these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0153] The terms used in this article are selected to best explain the principles of each embodiment, practical application or technical improvement in the market, or to enable other ordinary technicians in the field to understand the embodiments disclosed herein. For those skilled in the art, the present disclosure may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for generating a circuit simulation model, comprising: Performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, the plurality of semiconductor process devices having different sizes respectively; In response to the simulation value of the target parameter satisfying a predetermined standard, respectively determining the models corresponding to the simulation value satisfying the predetermined standard as corresponding optimization models; Arranging the grid points representing each of the optimization models into a matrix based on the size of each of the semiconductor process devices; as well as Based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, a circuit simulation model for simulating semiconductor process devices of various sizes is determined.

2. The method according to claim 1, wherein simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices comprises: Taking the curves of electrical characteristics of the plurality of semiconductor process devices as optimization targets; as well as The predetermined model parameters related to the target parameters corresponding to the points on the curve are simulated and optimized so that the difference between the simulation value corresponding to the target parameters and the target values ​​represented by the points on the curve becomes smaller during the iterative simulation process.

3. The method according to claim 1, wherein simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices comprises: Taking a given value of a predetermined electrical parameter of the semiconductor process device as an optimization target; as well as The predetermined model parameter related to the predetermined electrical parameter is simulated and optimized so that the difference between the simulation value of the predetermined electrical parameter and the given value becomes smaller during the iterative simulation process.

4. The method according to claim 2 or 3, wherein simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices comprises: Constructing a Jacobian matrix of each of the predetermined model parameters, wherein each of the predetermined model parameters serves as an input variable of a loss function in the Jacobian matrix, wherein the loss function is a function representing a difference between a simulated value of the target parameter and a target value represented by a point on the curve or a function representing a difference between a simulated value of the predetermined electrical parameter and the given value; as well as The predetermined model parameters are iteratively optimized in response to changes in the value of the loss function to obtain optimized model parameters.

5. The method according to claim 4, wherein determining that the simulated value of the target parameter meets a predetermined criterion is based on any one of the following: During the simulation, the value of the loss function is less than a predetermined threshold; During the simulation process, the ratio of the simulation values ​​of the two previous and subsequent iterations is less than a predetermined threshold; as well as The number of iterations or the iteration time during the simulation process reaches a predetermined threshold.

6. The method according to claim 1, wherein arranging the grid points representing each of the optimization models into a matrix based on the size of each semiconductor process device comprises: Arranging rows of the grid points along a first direction based on first size parameters of each of the semiconductor process devices; as well as The columns of the grid points are arranged along a second direction based on a second size parameter of each of the semiconductor process devices.

7. The method according to claim 1, wherein determining a circuit simulation model for simulating semiconductor process devices of various sizes based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device comprises: Determining any model corresponding to a point at any position within a range corresponding to the matrix based on the grid points of each square in the matrix; and A combination of each of the any one models and each of the optimization models corresponding to each of the grid points is determined as the circuit simulation model.

8. The method according to claim 7, wherein determining any model corresponding to a point at any position within a range corresponding to the matrix based on the grid points of each square in the matrix comprises: Interpolation processing is performed between the grid points in the matrix to determine the model corresponding to any position within the range corresponding to the matrix except the grid points.

9. The method according to claim 8, wherein performing interpolation processing between the grid points in the matrix to determine the model corresponding to any position other than the grid points within the range corresponding to the matrix comprises: Constructing a set of equations based on a predetermined number of adjacent grid points within a predetermined range in the matrix, wherein each equation in the set of equations respectively represents a relationship between a parameter related to a size feature of each semiconductor process device and a model parameter of a model represented by each grid point; Solving the common characteristic parameters of the optimization model represented by each grid point in the matrix based on the equation group; as well as Based on the characteristic parameters, the parameters related to the size characteristics corresponding to the adjacent grid points, and the coordinates of the points at any position within the predetermined range, the model corresponding to the point at any position in the matrix is ​​determined.

10. The method according to claim 9, wherein the parameters related to the characteristics of each semiconductor process device include at least the following: Basis parameters, which are common parameters of each equation in the system of equations; the first size parameter; and The second size parameter.

11. The method according to claim 10, wherein the semiconductor process device is a fin field effect transistor, the first size parameter is the length of the fin field effect transistor, the second size parameter is the number of fins of the fin field effect transistor, and wherein, The parameters related to the characteristics of the semiconductor process device further include a third parameter, which is the product of the length and the number of the fins.

12. The method according to claim 11, wherein determining any model corresponding to a point at any position within a range corresponding to the matrix based on the grid points of each square in the matrix comprises: Selecting a square corresponding to the size of the semiconductor process device from the matrix based on the first size parameter, the second size parameter, and the third size parameter of the semiconductor process device corresponding to any one of the positions; Constructing the set of equations based on the model parameters and size parameters of the optimization model corresponding to the grid points of the selected grid; as well as The equation group is solved to determine the model parameters of the model corresponding to any point, thereby determining any model corresponding to the point at any position.

13. The method according to claim 1, wherein before performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices, the method further comprises: Configuring in the target file a strategy for optimizing the model parameters and / or a strategy for secondary optimization of key target parameters; as well as The model parameters to be optimized are selected based on a strategy for optimizing the model parameters.

14. The method according to claim 13, wherein after the simulation value of the predetermined model parameter meets the predetermined standard, it further comprises: Based on the optimization flag indication, it is determined to perform the secondary optimization on the key target parameters to generate a further optimized model.

15. An electronic device, comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions comprising: Performing simulation optimization on predetermined model parameters of respective initial models of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes respectively; In response to the simulation value of the target parameter satisfying a predetermined standard, respectively determining the models corresponding to the simulation value satisfying the predetermined standard as corresponding optimization models; Arranging the grid points representing each of the optimization models into a matrix based on the size of each of the semiconductor process devices; and Based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, a circuit simulation model for simulating semiconductor process devices of various sizes is determined.

16. A computer-readable storage medium having machine-executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the method according to any one of claims 1 to 14.

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