Pixel circuit and display device

Abstract

The invention relates to a pixel circuit and a display device. The pixel circuit includes: a first transistor including a control electrode connected to a second node, a first electrode receiving a first power supply voltage, and a second electrode connected to a third node; a second transistor including a control electrode receiving a write signal, a first electrode connected to the data line, and a second electrode connected to the first node; a third transistor including a control electrode receiving the compensation signal, a first electrode connected to the second node, and a second electrode connected to a third node; a fourth transistor including a control electrode receiving an initialization signal, a first electrode receiving an initialization voltage, and a second electrode connected to a fourth node; a fifth transistor including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and a light emitting element including a first electrode connected to the fourth node.

Description

Technical Field

[0001] The present inventive concept relates to a display device and more particularly to a pixel circuit and a display device including the pixel circuit. Background Art

[0002] Typically, a display device may include a display panel and a display panel driver. The display panel may include a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver configured to provide a gate signal to the gate line, a data driver configured to provide a data voltage to the data line, an emission driver configured to provide an emission signal to the emission line, and a drive controller configured to control the gate driver, the data driver, and the emission driver.

[0003] Conventional pixel circuits may include seven or more transistors. Therefore, due to integration limitations, it may be difficult to apply conventional pixel circuits to ultra-high-resolution display devices. Summary of the invention

[0004] Embodiments of the inventive concept provide a pixel circuit having a small number of transistors.

[0005] Embodiments of the inventive concept also provide a display device including the pixel circuit.

[0006] In an embodiment according to the concept of the present invention, a pixel circuit includes: a first transistor, including a control electrode connected to a second node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a third node; a second transistor, including a control electrode configured to receive a write signal, a first electrode connected to a data line, and a second electrode connected to the first node; a third transistor, including a control electrode configured to receive a compensation signal, a first electrode connected to the second node, and a second electrode connected to the third node; a fourth transistor, including a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node; a fifth transistor, including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and a light-emitting element, including a first electrode connected to the fourth node and a second electrode receiving a second power supply voltage.

[0007] In an embodiment, the pixel circuit may further include: a first capacitor comprising a first electrode configured to receive a first power supply voltage and a second electrode connected to a second node; a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; and a third capacitor comprising a first electrode connected to a control electrode of a fourth transistor and a second electrode connected to the second node.

[0008] In an embodiment, a frame period of a pixel circuit may include: a first period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; a second period, in which the initialization signal changes from invalid to valid, the compensation signal is invalid, and the write signal is valid; a third period, in which the initialization signal is valid, the compensation signal is valid, and the write signal is valid; a fourth period, in which the initialization signal changes from valid to invalid, the compensation signal is invalid, and the write signal is valid; and a fifth period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

[0009] In an embodiment, in the first period, the second transistor may be in a turned-on state in response to a write signal, a reference voltage of the data line may be applied to the control electrode of the fifth transistor, and a voltage of the second node may be initialized.

[0010] In an embodiment, in the second period, the fourth transistor may be in a turned-on state in response to an initialization signal, an initialization voltage may be applied to the fourth node, the fifth transistor may be in a turned-off state, and the first transistor is in a turned-on state in response to a coupling operation of the third capacitor.

[0011] In an embodiment, in the third period, the third transistor may be in a turned-on state in response to the compensation signal, and a threshold voltage of the first transistor may be stored between the first electrode of the first capacitor and the second electrode of the first capacitor.

[0012] In an embodiment, in a fourth period, the third transistor may be in a cut-off state in response to an invalid state of the compensation signal, the second transistor may transmit the data voltage of the data line to the first node in response to a valid state of the write signal, and the data voltage of the first node may be applied to the second node in response to a coupling operation of the second capacitor.

[0013] In an embodiment, in the fifth period, the second transistor may be in a turn-off state in response to the compensation signal, and the fifth transistor may be turned on based on the voltage of the first node.

[0014] In an embodiment, a frame period of a pixel circuit may include: a first period, in which the initialization signal is valid, the compensation signal is invalid, and the write signal is invalid; a second period, in which the initialization signal is valid, the compensation signal is invalid, and the write signal is valid; a third period, in which the initialization signal is valid, the compensation signal is valid, and the write signal is valid; a fourth period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; and a fifth period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

[0015] In an embodiment, a frame period of a pixel circuit may include: a first time period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; a second time period, in which the initialization signal changes from invalid to valid, the compensation signal is invalid, and the write signal is valid; a third time period, in which the initialization signal is valid, the compensation signal is invalid, and the write signal is invalid; a fourth time period, in which the initialization signal is valid, the compensation signal is valid, and the write signal is invalid; a fifth time period, in which the initialization signal changes from valid to invalid, the compensation signal is invalid, and the write signal changes from invalid to valid; and a sixth time period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

[0016] In an embodiment, the initialization voltage may be a second power supply voltage.

[0017] In an embodiment, the pixel circuit may further include: a first capacitor including a first electrode configured to receive a first power supply voltage and a second electrode connected to a second node; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and a third capacitor including a first electrode configured to receive a compensation signal and a second electrode connected to the second node.

[0018] In an embodiment, the pixel circuit may further include: a first capacitor including a first electrode configured to receive a first power supply voltage and a second electrode connected to a second node; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a third capacitor including a first electrode connected to a control electrode of a fourth transistor and a second electrode connected to the second node; a fourth capacitor including a first electrode connected to the control electrode of the third transistor and a second electrode connected to the second node; a fifth capacitor including a first electrode configured to receive a first power supply voltage and a second electrode connected to the first node; a sixth capacitor including a first electrode connected to the fourth node and a second electrode connected to the control electrode of the second transistor. The initialization signal may be a next-level write signal of a next level.

[0019] In one embodiment, the frame period of the pixel circuit may include: a first period, in which the write signal changes from invalid to valid, the next level write signal is invalid, and the compensation signal is invalid; a second period, in which the write signal is valid, the next level write signal is invalid, and the compensation signal is invalid; a third period, in which the write signal changes from valid to invalid, the next level write signal changes from invalid to valid, and the compensation signal is invalid; a fourth period, in which the write signal changes from invalid to valid, the next level write signal changes from valid to invalid, and the compensation signal changes from invalid to valid; a fifth period, in which the write signal is valid , the next level write signal is invalid, and the compensation signal is; a sixth time period, in the sixth time period, the write signal is valid, the next level write signal changes from invalid to valid, and the compensation signal changes from valid to invalid; a seventh time period, in the seventh time period, the write signal is valid, the next level write signal is valid, and the compensation signal is invalid; an eighth time period, in the eighth time period, the write signal changes from valid to invalid, the next level write signal is valid, and the compensation signal is invalid; a ninth time period, in which the write signal is invalid, the next level write signal changes from valid to invalid, and the compensation signal is invalid; and a tenth time period, in which the write signal is invalid, the next level write signal is invalid, and the compensation signal is invalid.

[0020] In an embodiment, in a ninth period, the third transistor is in a cut-off state in response to the compensation signal, a coupling voltage may be applied to the second node in response to a coupling operation of the third capacitor, and a voltage of the second node may have a final compensation voltage.

[0021] In an embodiment, in the tenth period, the data voltage of the data line may be applied to the control electrode of the fifth transistor, and the data voltage is lower than the sum of the first power voltage and the threshold voltage of the fifth transistor, so that the fifth transistor may be in a turned-on state.

[0022] In one embodiment, the frame period of the pixel circuit may include: a first time period, in which the write signal changes from invalid to valid, the next level write signal is invalid, and the compensation signal is invalid; a second time period, in which the write signal is valid, the next level write signal is invalid, and the compensation signal is invalid; a third time period, in which the write signal changes from valid to invalid, the next level write signal changes from invalid to valid, and the compensation signal is invalid; a fourth time period, in which the write signal changes from invalid to valid, the next level write signal changes from valid to invalid, and the compensation signal changes from invalid to valid, a fifth time period, in which the write signal is valid, the next level write signal is invalid, and the compensation signal is valid, a sixth time period, in which the write signal changes from valid to invalid, the next level write signal changes from invalid to valid, and the compensation signal changes from valid to invalid; a seventh time period, in which the write signal is invalid, the next level write signal changes from valid to invalid, and the compensation signal is invalid; and an eighth time period, in which the write signal is invalid, the next level write signal is invalid, and the compensation signal is invalid.

[0023] In an embodiment according to the concept of the present invention, a display device may include a display panel, a gate driver and a data driver. The display panel may include a pixel circuit. The gate driver may apply a write signal, a compensation signal and an initialization signal to the pixel circuit. The data driver may apply a data voltage or a reference voltage to the pixel circuit. The pixel circuit may include: a first transistor including a control electrode connected to a second node, a first electrode configured to receive a first power supply voltage and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a write signal, a first electrode connected to a data line and a second electrode connected to a first node; a third transistor including a control electrode configured to receive a compensation signal, a first electrode connected to a second node and a second electrode connected to a third node; a fourth transistor including a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage and a second electrode connected to a fourth node; a fifth transistor including a control electrode connected to a first node, a first electrode connected to a third node and a second electrode connected to a fourth node; and a light emitting element including a first electrode connected to a fourth node and a second electrode configured to receive a second power supply voltage.

[0024] In an embodiment, the pixel circuit may further include: a first capacitor comprising a first electrode configured to receive a first power supply voltage and a second electrode connected to a second node; a second capacitor comprising a first electrode connected to the first node and a second electrode connected to the second node; and a third capacitor comprising a first electrode connected to a control electrode of a fourth transistor and a second electrode connected to the second node.

[0025] In an embodiment, a frame period of a pixel circuit may include: a first period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; a second period, in which the initialization signal changes from invalid to valid, the compensation signal is invalid, and the write signal is valid; a third period, in which the initialization signal is valid, the compensation signal is valid, and the write signal is valid; a fourth period, in which the initialization signal changes from valid to invalid, the compensation signal is invalid, and the write signal is valid; and a fifth period, in which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

[0026] As described above, the pixel circuit according to the embodiment may include five transistors and three capacitors. Compared with the conventional pixel circuit, the pixel circuit may perform internal compensation and may have a relatively small number of transistors, thereby achieving high integration. Therefore, the pixel circuit may be applied to an ultra-high resolution display device.

[0027] Furthermore, a display device including the pixel circuit may not use an emission driver, which may be advantageous for cost reduction and high-resolution design. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features and advantages of the inventive concept will become more apparent by describing detailed embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept;

[0030] Figure 2 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept;

[0031] Figure 3 is shown applied to Figure 2 A timing diagram of an example of an input signal of a pixel circuit;

[0032] Figure 4 Is used to describe Figure 2 a circuit diagram of the operation of a pixel circuit in a first time period;

[0033] Figure 5 is used to describe a situation in which the first transistor has an off state in the first period Figure 2 a circuit diagram of the operation of the pixel circuit in a second time period;

[0034] Figure 6 is used to describe a situation in which the first transistor has an on state in the first period Figure 2 a circuit diagram of the operation of the pixel circuit in a second time period;

[0035] Figure 7 Is used to describe Figure 2 a circuit diagram of the operation of the pixel circuit in a third time period;

[0036] Figure 8 Is used to describe Figure 2 A circuit diagram of the operation of the pixel circuit in a fourth period;

[0037] Fig. 9 Is used to describe Figure 2 A circuit diagram of the operation of the pixel circuit in a fifth period;

[0038] Fig.10 is shown applied to Figure 2 A timing diagram of an example of an input signal of a pixel circuit;

[0039] Fig.11 is shown applied to Figure 2 A timing diagram of an example of an input signal of a pixel circuit;

[0040] Fig.12 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept;

[0041] Fig.13 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept;

[0042] Fig.14 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept;

[0043] Fig.15 is shown applied to Fig.14 A timing diagram of an example of an input signal of a pixel circuit;

[0044] Fig.16 Is used to describe Fig.14 a circuit diagram of the operation of a pixel circuit in a first time period;

[0045] Fig.17 is used to describe a situation in which the first transistor has an off state in the first period Fig.14 a circuit diagram of the operation of the pixel circuit in a second time period;

[0046] Fig.18 is used to describe a situation in which the first transistor has an on state in the first period Fig.14 a circuit diagram of the operation of the pixel circuit in a second time period;

[0047] Fig.19 Is used to describe Fig.14 a circuit diagram of the operation of the pixel circuit in a third time period;

[0048] Fig. 20 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a fourth period;

[0049] Fig.21 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a fifth period;

[0050] Fig. 22 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a sixth period;

[0051] Fig.23 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a seventh period;

[0052] Fig.24 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in an eighth period;

[0053] Fig.25 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a ninth period;

[0054] Fig.26 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a tenth time period;

[0055] Fig. 27 is shown applied to Fig.14 A timing diagram of an example of an input signal of a pixel circuit;

[0056] Fig.28 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept; and

[0057] Fig.29 It shows that Fig.28 A diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0058] Hereinafter, the inventive concept will be described in more detail with reference to the accompanying drawings.

[0059] Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept.

[0060] Reference Figure 1 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0061] The display panel 100 may include a display portion configured to display an image and a peripheral portion adjacent to the display portion.

[0062] The display panel 100 may include a plurality of gate lines GWL, GIL, GCL, a plurality of data lines DL, and a plurality of pixel circuits electrically connected to the gate lines GWL, GIL, GCL and the data lines DL, respectively. For example, each pixel circuit of the display panel 100 may include Figure 2 The pixel circuit 600 shown in Fig.12 The pixel circuit 700 shown in Fig.13 The pixel circuit 800 shown in FIG. Fig.14 The gate lines GWL, GIL, GCL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 crossing the first direction D1.

[0063] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0064] The driving controller 200 may generate a gate control signal CONT1 , a data control signal CONT2 , a gamma control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0065] The driving controller 200 may generate a gate control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT to output the generated gate control signal CONT1 to the gate driver 300. The gate control signal CONT1 may include a vertical start signal and a gate clock signal.

[0066] The driving controller 200 may generate a data control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT to output the generated data control signal CONT2 to the data driver 500. The data control signal CONT2 may include a horizontal start signal and a load signal.

[0067] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0068] The driving controller 200 may generate a gamma control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT to output the generated gamma control signal CONT3 to the gamma reference voltage generator 400 .

[0069] The gate driver 300 may generate a gate signal for driving the gate lines GWL, GIL, GCL in response to the gate control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate lines GWL, GIL, GCL. For example, the gate driver 300 may sequentially output the gate signal to the gate lines GWL, GIL, GCL. The gate signal may include an initialization signal GI, a compensation signal GC, and a write signal GW.

[0070] For example, the gate driver 300 may be mounted on a peripheral area of ​​the display panel 100. For example, the gate driver 300 may be integrated in a peripheral area of ​​the display panel 100.

[0071] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the gamma control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500.

[0072] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0073] The data driver 500 may receive the data control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog data voltage by using the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL. In addition, the data driver 500 may generate a reference voltage VREF (see FIG. 1 ) in at least a portion of a frame period. Figure 2 ) or data voltage VDATA (see Figure 2 ) is output to the data line DL.

[0074] For example, the data driver 500 may be mounted on a peripheral area of ​​the display panel 100. For example, the data driver 500 may be integrated in the peripheral area of ​​the display panel 100.

[0075] although Figure 1The gate driver 300 is shown disposed at a first side of the display panel 100 , but the inventive concept is not limited thereto. For example, the gate driver 300 may be disposed at a second side of the display panel 100 different from the first side.

[0076] Figure 2 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept.

[0077] Reference Figure 2 The pixel circuit 600 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a light emitting element EE. In one embodiment, the pixel circuit 600 may further include a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0078] The first transistor T1 may generate a driving current based on a voltage of the second node N2. For example, the first transistor T1 may be referred to as a driving transistor for generating a driving current. In one embodiment, the first transistor T1 includes a control electrode connected to the second node N2, a first electrode configured to receive a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second electrode connected to a third node N3.

[0079] The second transistor T2 may transmit the data voltage VDATA (or the reference voltage VREF) of the data line DL to the first node N1 in response to the write signal GW. For example, the second transistor T2 may be referred to as a write transistor for transmitting the data voltage VDATA to the pixel circuit 600. In one embodiment, the second transistor T2 may include a control electrode configured to receive the write signal GW, a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0080] The third transistor T3 may diode-connect the first transistor T1 in response to the compensation signal GC. For example, the third transistor T3 may be referred to as a compensation transistor for compensating for a threshold voltage of the first transistor T1. In one embodiment, the third transistor T3 may include a control electrode configured to receive the compensation signal GC, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0081] The fourth transistor T4 may transmit the initialization voltage VINIT to the fourth node N4 (or the anode of the light emitting element EE) in response to the initialization signal GI. For example, the fourth transistor T4 may be referred to as an initialization transistor for initializing the anode of the light emitting element EE. In one embodiment, the fourth transistor T4 may include a control electrode configured to receive the initialization signal GI, a first electrode configured to receive the initialization voltage VINIT, and a second electrode connected to the fourth node N4.

[0082] The fifth transistor T5 may selectively connect the first transistor T1 to the light emitting element EE in response to the voltage of the first node N1. For example, the fifth transistor T5 may be referred to as an emission transistor that selectively generates a drive current path. In one embodiment, the fifth transistor T5 may include a control electrode connected to the first node N1, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0083] The light emitting element EE may emit light based on the driving current generated by the first transistor T1. In one embodiment, the light emitting element EE may be an organic light emitting diode (OLED), but is not limited thereto. In other embodiments, the light emitting element EE may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting device. In addition, in one embodiment, the light emitting element EE may include a first electrode (e.g., an anode) connected to a fourth node N4 and a second electrode (e.g., a cathode) configured to receive a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0084] As described above, the control electrode of the fifth transistor T5 (or emission transistor) is configured to receive the voltage of the first node N1 instead of the emission signal. Therefore, a display device including the pixel circuit 600 may not use an emission driver for generating an emission signal, which may be advantageous for cost reduction and high-resolution design.

[0085] The first capacitor C1 may be connected between a line of the first power supply voltage ELVDD and the second node N2. The first capacitor C1 may be used to maintain a voltage of the second node N2 (i.e., a voltage of a control electrode of the first transistor T1). In one embodiment, the first capacitor C1 may include a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the second node N2.

[0086] The second capacitor C2 may be connected between the first node N1 and the second node N2. The second capacitor C2 may be used to transfer the data voltage VDATA applied to the first node N1 to the second node N2. In one embodiment, the second capacitor C2 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0087] The third capacitor C3 may be connected between the control electrode of the fourth transistor T4 and the second node N2. The third capacitor C3 may control the voltage of the second node N2 (i.e., the voltage of the control electrode of the first transistor T1) in response to the initialization signal GI. In one embodiment, the third capacitor C3 may include a first electrode connected to the control electrode of the fourth transistor T4 (i.e., the first electrode configured to receive the initialization signal GI) and a second electrode connected to the second node N2.

[0088] As such, the pixel circuit 600 may have a 5T3C structure including five transistors T1 , T2 , T3 , T4 , T5 and three capacitors C1 , C2 , C3 .

[0089] Figure 3 is shown applied to Figure 2 FIG. 1 is a timing diagram of an example of an input signal of a pixel circuit. Figure 4 Is used to describe Figure 2 Circuit diagram of the operation of the pixel circuit in a first period. Figure 5 is used to describe a situation in which the first transistor has an off state in the first period Figure 2 A circuit diagram of the operation of the pixel circuit in the second period. Figure 6 is used to describe a situation in which the first transistor has an on state in the first period Figure 2 A circuit diagram of the operation of the pixel circuit in the second period. Figure 7 Is used to describe Figure 2 A circuit diagram of the operation of the pixel circuit in a third period. Figure 8 Is used to describe Figure 2 A circuit diagram of the operation of the pixel circuit in a fourth period. Fig. 9 Is used to describe Figure 2 A circuit diagram of the operation of the pixel circuit in the fifth period.

[0090] Reference Figure 2 and Figure 3 , the frame period FP of the pixel circuit 600 may include a first period TP1A, a second period TP2A, a third period TP3A, a fourth period TP4A, and a fifth period TP5A. In one embodiment, the first period TP1A is a first initialization period, the second period TP2A is a second initialization period, the third period TP3A is a first compensation period, the fourth period TP4A is a second compensation period, and the fifth period TP5A may be a light emitting period.

[0091] Reference Figure 3 and Figure 4 In the first period TP1A, the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid. Figure 2As shown in , the pixel circuit 600 may include P-type transistors T1 to T5. Therefore, the effective level / activation level of the initialization signal GI, the compensation signal GC, and the write signal GW may be a low level, and the invalid level / disable level may be a high level, but is not limited to this. In another embodiment, the pixel circuit 600 may include N-type transistors T1 to T5, the effective level / activation level of the initialization signal GI, the compensation signal GC, and the write signal GW may be a high level, and the invalid level / disable level may be a low level. As used herein, a signal "valid" means that the signal level is at a valid level / activation level, and a signal "invalid" means that the signal level is not at a valid level / activation level.

[0092] In the first period TP1A, the reference voltage VREF may be applied to the data line DL, and the second transistor T2 may be turned on in response to the valid write signal GW. Therefore, the second transistor T2 may apply the reference voltage VREF to the first node N1, and the reference voltage VREF may be applied to the control electrode of the fifth transistor T5.

[0093] When the first transistor T1 is turned off in the first period TP1A, the voltage of the second node N2 may be higher than the sum of the first power voltage ELVDD and the threshold voltage (VTH). In this case, the voltage difference between the voltage of the first electrode (e.g., source) of the first transistor T1 and the voltage of the control electrode of the first transistor T1 is higher than the threshold voltage (VTH) of the first transistor T1.

[0094] In addition, when the third transistor T3 is turned off, the voltage difference between the voltage of the first electrode (e.g., source) of the third transistor T3 and the voltage of the control electrode of the third transistor T3 is higher than the threshold voltage (VTH) of the first transistor T3. In this case, the voltage of the second node N2 may be lower than the voltage obtained by subtracting the threshold voltage (VTH) of the third transistor T3 from the voltage of the high level of the compensation signal GC. For example, when the high level of the compensation signal GC is about 8V and the threshold voltage (VTH) of the third transistor T3 is about -0.6V, the voltage of the second node N2 may be lower than about 8.6V.

[0095] On the contrary, when the third transistor T3 is turned on, that is, the voltage difference between the voltage of the first electrode (e.g., source) of the third transistor T3 and the voltage of the control electrode of the third transistor T3 is lower than the threshold voltage (VTH) of the first transistor T3, the voltage of the second node N2 may be higher than the voltage obtained by subtracting the threshold voltage (VTH) of the third transistor T3 from the voltage of the high level of the compensation signal GC. Because the third transistor T3 may have a turned-on state, the voltage of the second node N2 and the voltage of the third node N3 may be the same.

[0096] Therefore, the voltage difference between the voltage of the first electrode (e.g., source) of the fifth transistor T5 and the reference voltage VREF as the voltage of the control electrode applied to the fifth transistor T5 can be lower than the threshold voltage (VTH) of the fifth transistor T5. In this case, the fifth transistor T5 can be turned on. For example, the voltage of the second node N2 is higher than about 8.6V, the reference voltage VREF is about 8V, and the threshold voltage (VTH) of the fifth transistor T5 is about -0.6V. In this case, since the third transistor T3 can be turned on, the voltage of the third node N3 can become equal to the voltage of the second node N2, and the fifth transistor T5 can be turned on. Since the fifth transistor can be turned on, the voltage of the second node N2, the voltage of the third node N3, and the voltage of the fourth node N4 can become equal. If the voltage difference between the voltage of the second electrode (e.g., source) of the fourth transistor T4 and the voltage of the high level of the initialization signal GI applied to the control electrode of the fourth transistor T4 is lower than the threshold voltage of the fourth transistor T4, the fourth transistor T4 can have a conducting state. For example, if the voltage of the second node N2 is higher than about 8.6V, the voltage of the high level of the initialization signal GI is about 8V, and the threshold voltage of the fourth transistor T4 is about -0.6V, the fourth transistor T4 may be turned on. Therefore, the initialization voltage VINIT may be applied to the second node N2.

[0097] On the contrary, when the first transistor T1 has the on-state in the first period TP1A, the voltage of the second node N2 may be lower than the sum of the first power voltage ELVDD and the threshold voltage of the first transistor T1 .

[0098] That is, in the first period TP1A, regardless of whether the first transistor T1 is in the off state or the on state, and regardless of whether the third transistor T3 is in the off state or the on state, the voltage of the second node N2 can be initialized to be lower than a specific voltage. For example, the voltage of the second node N2 can be initialized to be lower than or equal to a voltage obtained by subtracting the threshold voltage of the third transistor T3 from the voltage of the high level of the compensation signal GC.

[0099] Reference Figure 3 as well as Figures 5 and 6 , in the second period TP2A, the initialization signal GI may change from inactive to active, the compensation signal GC may be inactive, and the write signal GW may be active.

[0100] Reference Figure 5 When the first transistor T1 is in the off state, the initialization signal GI may have a low level. Because the initialization signal GI may have a low level, the fourth transistor T4 may be turned on. Therefore, the voltage of the fourth node N4 may be maintained at the initialization voltage VINIT.

[0101] Because the initialization voltage VINIT may be applied to the control electrode of the fifth transistor T5 and the voltage of the fourth node N4 may have the initialization voltage VINIT, the fifth transistor T5 may be turned off.

[0102] The third capacitor C3 may couple the voltage variation of the initialization signal GI and may apply it to the second node N2. Therefore, the first transistor T1 may be turned on in response to the voltage of the second node N2. For example, when the voltage of the second node N2 in the first period TP1A is about 8.6V, the threshold voltage of the first transistor T1 is about -0.6V, the voltage of the low level of the initialization signal GW is about -8V, the voltage of the high level of the initialization signal GW is about 8V, and the ratio of the capacitance of the first capacitor C1, the capacitance of the second capacitor C2, and the capacitance of the third capacitor C3 is 1.5:6:2.5, the voltage applied by the third capacitor C3 through coupling the voltage variation of the initialization signal GI may be about -4V, and thus the voltage of the second node N2 may be about 4.6V.

[0103] Because the voltage of the second node N2 may decrease, a voltage obtained by subtracting the voltage of the first electrode of the third transistor T3 from the voltage of the control electrode of the third transistor T3 may be higher than the threshold voltage of the third transistor. Therefore, the third transistor T3 may be turned off.

[0104] Reference Figure 6 When the first transistor T1 is in the on state, the initialization signal GI may be valid. Therefore, the fourth transistor T4 may be turned on. Therefore, the fourth node N4 may be initialized to the initialization voltage VINIT.

[0105] The reference voltage VREF may be applied to the control electrode of the fifth transistor T5, and the voltage of the third node N3 may have the first power supply voltage ELVDD. Therefore, the voltage obtained by subtracting the voltage of the first electrode (e.g., source) of the fifth transistor T5 from the voltage of the control electrode of the fifth transistor T5 may be higher than the threshold voltage of the fifth transistor T5. Therefore, the fifth transistor T5 may be turned off. For example, when the reference voltage VREF may be about 8V, the threshold voltage of the fifth transistor T5 may be about -0.6V, and the first power supply voltage ELVDD may be about 7V, since 8V-7V>0.6V, the fifth transistor T5 may be turned off.

[0106] The third capacitor C3 may couple the voltage variation of the initialization signal GI and may apply it to the second node N2. Therefore, the first transistor T1 may be maintained in a turned-on state in response to the voltage of the second node N2. For example, when the voltage of the second node N2 in the first period TP1A is about -4V, the threshold voltage of the first transistor T1 is about -0.6V, the voltage of the low level of the initialization signal GI is about -8V, the voltage of the high level of the initialization signal GI is about 8V, and the capacitance ratio of the first capacitor C1, the capacitance of the second capacitor C2, and the third capacitor C3 is 1.5:6:2.5, the voltage applied by the third capacitor C3 through coupling the voltage variation of the initialization signal GI may be about -4V, and thus the voltage of the second node N2 may be about -8V.

[0107] Reference Figure 3 and Figure 7 , in the third period TP3A, the initialization signal GI may be active, the compensation signal GC may be active, and the write signal GW may be active.

[0108] Reference Figure 7 , in the third period TP3A, the third transistor T3 may diode-connect the first transistor T1 in response to the compensation signal GC. Therefore, due to the diode-connected first transistor T1, the voltage of the second node N2 may be the sum of the first power supply voltage ELVDD and the threshold voltage of the first transistor T1. In addition, because the first electrode of the first capacitor C1 may be applied with the first power supply voltage ELVDD and the voltage of the second electrode of the first capacitor C1 may be the voltage of the second node N2, the threshold voltage of the first transistor T1 may be stored between the first electrode of the first capacitor C1 and the second electrode of the first capacitor C1. The voltage of the second node N2 may be the sum of the first power supply voltage ELVDD and the threshold voltage of the first transistor T1. The operation of storing the threshold voltage of the first transistor T1 between the first electrode of the first capacitor C1 and the second electrode of the first capacitor C1 may be referred to as a "compensation operation" herein.

[0109] Reference Figure 3 and Figure 8 , in the fourth period TP4A, the initialization signal GI may change from being valid to being invalid, the compensation signal GC may be invalid, and the write signal GW may be valid.

[0110] Reference Figure 8 , the third transistor T3 may be turned off in response to the inactive state of the compensation signal GC. Since the initialization signal GI may be changed from active to inactive, the fourth transistor T4 may be turned off.

[0111] In the fourth period TP4A, the voltage of the first node N1 may be the data voltage VDATA, and the voltage of the second node N2 may be the final compensation voltage. For example, the final compensation voltage may be ELVDD+VTH+C2 / (C1+C2+C3)×(VDATA)-C2 / (C1+C2+C3)×(VREF)+C3 / (C1+C2+C3)×(VGH-VGL). C1 represents the capacitance of the first capacitor C1, C2 represents the capacitance of the second capacitor C2, and C3 represents the capacitance of the third capacitor C3. In addition, VGL represents the low level voltage of the initialization signal GI, and VGH represents the high level voltage of the initialization signal GI. Therefore, the voltage of the second node N2 may be the final compensation voltage.

[0112] Reference Figure 3 and Fig. 9 , in the fifth period TP5A, the initialization signal GI may be inactive, the compensation signal GC may be inactive, and the write signal GW may be inactive.

[0113] The second transistor T2 may be turned off in response to the inactive state of the write signal GW.

[0114] When a voltage obtained by subtracting the first power voltage ELVDD from the data voltage VDATA is lower than a threshold voltage of the fifth transistor T5 , the fifth transistor T5 may be turned on.

[0115] The light emitting element EE may emit light in response to a current flowing through the first transistor T1 , the fifth transistor T5 , and the light emitting element EE.

[0116] According to the above embodiment, the pixel circuit 600 may include five transistors T1 to T5 and three capacitors C1 to C3. The pixel circuit 600 may perform internal compensation and may have a relatively small number of transistors compared to conventional pixel circuits, allowing high integration. Therefore, the pixel circuit 600 may be applied to ultra-high resolution display devices. In addition, the control electrode of the fifth transistor T5 may receive the voltage of the first node N1, rather than the emission signal as in the conventional pixel circuit. Therefore, the display device including the pixel circuit 600 allows the emission driver to be omitted, which may be advantageous for cost reduction and high resolution design.

[0117] Fig.10 is shown applied to Figure 2 FIG. 1 is a timing diagram of an example of an input signal of a pixel circuit.

[0118] The pixel circuit according to this embodiment Figure 2 The pixel circuit 600 is the same as that in FIG. 1 , but the driving timing according to this embodiment is the same as that in FIG. Figure 3The same reference numerals are used for components that are the same as or similar to those in the previous embodiment, and redundant descriptions are omitted.

[0119] Reference Fig.10 , in the first period TP1B, the initialization signal GI, the compensation level GC, and the write signal GW may be invalid. In the second period TP2B, the initialization signal GI may be valid, the compensation level GC may be invalid, and the write signal GW may be valid. In the third period TP3B, the initialization signal GI may be valid, the compensation level GC may be valid, and the write signal GW may be valid. In the fourth period TP4B, the initialization signal GI may be invalid, the compensation level GC may be invalid, and the write signal GW may be valid. In the fifth period TP5B, the initialization signal GI, the compensation level GC, and the write signal GW may be invalid. Therefore, the stability of the pixel circuit 600 can be increased.

[0120] Fig.11 is shown applied to Figure 2 FIG. 1 is a timing diagram of an example of an input signal of a pixel circuit.

[0121] The pixel circuit according to this embodiment Figure 2 The pixel circuit 600 is the same as that in FIG. 1 , but the driving timing according to this embodiment is the same as that in FIG. Figure 3 The same reference numerals are used for components that are the same as or similar to those in the previous embodiment, and redundant descriptions are omitted.

[0122] Reference Fig.11 , in the first period TP1C, the initialization signal GI and the compensation level GC may be invalid, and the write signal GW may be valid. In the second period TP2C, the initialization signal GI may change from invalid to valid, the compensation level GC may remain invalid, and the write signal GW may be valid. In the third period TP3C, the initialization signal GI may be valid, the compensation level GC may remain invalid, and the write signal GW may be invalid. In the fourth period TP4C, the initialization signal GI may be valid, the compensation level GC may be valid, and the write signal GW may be invalid. In the fifth period TP5B, the initialization signal GI may change from valid to invalid, the compensation level GC may be invalid, and the write signal GW may change from invalid to valid. In the sixth period TP6C, the initialization signal GI may remain invalid, the compensation signal GC may remain invalid, and the write signal GW may be invalid.

[0123] When entering the third period TP3C from the second period TP2C, the write signal GW may change from valid to invalid. The second transistor T2 may be turned off in response to the invalid write signal GW. Because the write signal GW may change from invalid to valid in the fifth period TP5C, the second transistor T2 may be turned on. Therefore, the stability of the pixel circuit 600 may be increased.

[0124] Fig.12 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept.

[0125] The pixel circuit 700 according to this embodiment is Figure 2 The pixel circuit 600 in FIG. 1 is different, but the driving timing according to this embodiment is the same as that in FIG. Figure 3 The same reference numerals are used for components that are the same as or similar to those in the previous embodiment, and redundant descriptions are omitted.

[0126] Reference Fig.12 In this embodiment, the pixel circuit 700 may include Figure 2 The pixel circuit 600 of FIG. 700 is differently connected to the fourth transistor T4. In the pixel circuit 700, the first electrode of the fourth transistor T4 is configured to receive the second power supply voltage ELVSS. In this embodiment, the initialization voltage VINIT may be the second power supply voltage ELVSS. Therefore, the line of the initialization voltage VINIT may be the same as the line of the second power supply voltage ELVSS, thereby reducing the display panel 100 (see FIG. 70). Figure 1 ) and improve the integration level.

[0127] Fig.13 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept.

[0128] The pixel circuit 800 according to this embodiment is Figure 2 The pixel circuit 600 in FIG. 1 is different from that in FIG. 1 , and the driving timing according to the present embodiment is different from that in FIG. Figure 3 The same reference numerals are used for components that are the same as or similar to those in the previous embodiment, and redundant descriptions are omitted.

[0129] Reference Figure 3 and Fig.13 In the present embodiment, the first electrode of the third capacitor C3 of the pixel circuit 800 may be applied with the compensation signal GC. Therefore, the voltage of the fourth node N4 may be initialized in the second period TP2A, and the third capacitor C3 may couple the voltage change of the compensation signal GC between the second period TP2A and the third period TP3A, and may apply the coupled voltage to the second node N2. Therefore, the first transistor T1 may be turned on in response to the voltage of the second node N2.

[0130] Fig.14 is a circuit diagram illustrating a pixel circuit according to an embodiment of the inventive concept.

[0131] The pixel circuit 900 according to this embodiment is Figure 2 The pixel circuit 600 is similar to that in FIG. 6 , but the driving timing according to this embodiment is Figure 3 The same reference numerals are used for components that are the same as or similar to those in the previous embodiment, and redundant descriptions are omitted.

[0132] Reference Figure 3 and Fig.14 , the pixel circuit 900 may further include a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. In addition, the initialization signal GI may be a write signal GW[N+1] of the next stage (referred to herein as "next stage write signal GW[N+1]"). The fourth capacitor C4 may include a first electrode configured to receive the compensation signal GC and a second electrode connected to the second node N2. The fifth capacitor C5 may include a first electrode configured to receive the first power supply voltage ELVDD and a second electrode connected to the first node N1. The sixth capacitor C6 may include a first electrode connected to the fourth node N4 and a second electrode configured to receive a write signal GW (e.g., a write signal GW[N] of the current stage).

[0133] Fig.15 is shown applied to Fig.14 FIG. 1 is a timing diagram of an example of an input signal of a pixel circuit. Fig.16 Is used to describe Fig.14 Circuit diagram of the operation of the pixel circuit in a first period. Fig.17 is used to describe a situation in which the first transistor has an off state in the first period Fig.14 A circuit diagram of the operation of the pixel circuit in the second period. Fig.18 is used to describe a situation in which the first transistor has an on state in the first period Fig.14 A circuit diagram of the operation of the pixel circuit in the second period. Fig.19 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a third period. Fig. 20 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a fourth period. Fig.21 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in the fifth period. Fig. 22 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in the sixth period. Fig.23 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in the seventh period. Fig.24 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in the eighth period. Fig.25 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in a ninth period. Fig.26 Is used to describe Fig.14 A circuit diagram of the operation of the pixel circuit in the tenth time period.

[0134] Reference Figures 15 to 26 , the frame period FP of the pixel circuit 900 may include a first period TP1D, a second period TP2D, a third period TP3D, a fourth period TP4D, a fifth period TP5D, a sixth period TP6D, a seventh period TP7D, an eighth period TP8D, a ninth period TP9D, and a tenth period TP10D. The first period TP1D may be an initialization start period. The second period TP2D may be a second node initialization period. The third period TP3D may be a fourth node initialization period. The fourth period TP4D may be a compensation preparation period. The fifth period TP5D may be a compensation period. The sixth period TP6D may be a compensation completion period. The seventh period TP7D may be a data writing period. The eighth period TP8D may be a final compensation voltage writing preparation period. The ninth period TP9D may be a final compensation voltage writing period. The tenth period TP10D may be an emission period.

[0135] Reference Fig.15 and Fig.16 In the first period TP1D, the write signal GW[N] may change from invalid to valid, the next-stage write signal GW[N+1] may be invalid, and the compensation signal GC (eg, the compensation signal GC[N] of the current stage) may be invalid.

[0136] Reference Fig.16 In the first period TP1D, as the write signal GW[N] changes from invalid to valid, the second transistor T2 may be turned on. Therefore, the reference voltage VREF may be applied to the control electrode of the fifth transistor T5. The fifth transistor T5 may be turned off in response to the reference voltage VREF.

[0137] The second capacitor C2 may couple a voltage difference between the data voltage VDATA and the reference voltage VREF, and may apply the voltage difference to the second node N2.

[0138] The sixth capacitor C6 may couple a voltage difference between a voltage of a high level of the write signal GW[N] and a voltage of a low level of the write signal GW[N], and may apply the voltage difference to the second node N2.

[0139] Reference Fig.15 , Fig.17 and Fig.18 , in the second period TP2D, the write signal GW[N] may be valid, the next-stage write signal GW[N+1] may be invalid, and the compensation signal GC may be invalid.

[0140] Reference Fig.17 When the first transistor T1 is in the off state, the voltage of the second node N2 may be higher than the sum of the first power supply voltage ELVDD and the threshold voltage of the first transistor T1. For example, when the first power supply voltage is about 7V and the threshold voltage of the first transistor T1 is about -1.52V, the voltage of the second node N2 may be higher than about 5.48V.

[0141] When the first transistor T1 is turned off, the voltage of the first electrode (eg, source) of the first transistor T1 is subtracted from the voltage of the control electrode of the first transistor T1 to calculate a difference, and the difference is higher than the threshold voltage of the first transistor T1. In this case, the third transistor T3 can be in an on state or an off state.

[0142] When the third transistor T3 is in the off state, the voltage of the first electrode (e.g., source) of the third transistor T3 is subtracted from the voltage of the control electrode of the third transistor T3 to calculate the difference, and the difference is higher than the threshold voltage of the third transistor T3. In this case, the fifth transistor T5 can be in the on state or the off state.

[0143] When the fifth transistor T5 is in the off state, the voltage of the fourth node N4 in the second period TP2D may be the same as the voltage of the fourth node N4 in the first period TP1D. When the fifth transistor T5 is in the off state, the fourth transistor T4 may be in the on state or the off state. When the fourth transistor T4 is in the off state, the voltage of the fourth node N4 may be lower than the voltage difference obtained by subtracting the threshold voltage of the fourth transistor T4 from the voltage of the next stage write signal GW[N+1]. When the fourth transistor T4 is in the on state, the voltage of the fourth node N4 may be higher than the voltage difference obtained by subtracting the threshold voltage of the fourth transistor T4 from the voltage of the next stage write signal GW[N+1]. When the fourth transistor T4 is turned on, the initialization voltage VINIT may be applied to the fourth node N4.

[0144] When the third transistor T3 is in the on state, the voltage of the compensation signal GC may be lower than the sum of the voltage of the second node N2 and the threshold voltage of the third transistor T3.

[0145] When the third transistor T3 is in the on state, the voltage of the first electrode (e.g., source) of the third transistor T3 is subtracted from the voltage of the control electrode of the third transistor T3 to calculate the difference, and the difference is lower than the threshold voltage of the third transistor T3. In this case, the fifth transistor T5 can be in the on state or the off state. When the fifth transistor T5 is in the off state, the voltage of the fourth node N4 in the second period TP2D can be the same as the voltage of the fourth node N4 in the first period TP1D. In addition, the voltage of the third node N3 can be the same as the voltage of the second node N2. Because the fifth transistor can be in the off state, the voltage difference obtained by subtracting the voltage of the first electrode of the fifth transistor T5 from the voltage of the control electrode of the fifth transistor T5 can be higher than the threshold voltage of the fifth transistor T5. Therefore, the voltage of the second node N2 can be lower than the voltage difference obtained by subtracting the voltage of the first electrode of the fifth transistor T5 from the reference voltage VREF. For example, when the reference voltage is about 9V and the threshold voltage of the fifth transistor T5 is about -1.52V, the voltage of the third node N3 can be about 10.52V.

[0146] When the fifth transistor T5 is in the on state, the fourth transistor T4 can be in the on state or the off state. When the fourth transistor T4 is turned off, the voltage of the fourth node N4 is lower than the voltage difference obtained by subtracting the threshold voltage of the fourth transistor T4 from the voltage of the next stage write signal GW[N+1]. In this case, the initialization voltage VINIT can be applied to the fourth node N4. Therefore, the initialization voltage VINIT can be applied to the second node N2. When the fourth transistor T4 is in the on state, the voltage of the fourth node N4 is higher than the voltage difference obtained by subtracting the threshold voltage of the fourth transistor T4 from the voltage of the next stage write signal GW[N+1]. In this case, the initialization voltage VINIT can be applied to the fourth node N4. Because the initialization voltage VINIT can be applied to the fourth node N4, the initialization voltage VINIT can be applied to the second node N2. For example, the initialization voltage VINIT can be about -4V.

[0147] Therefore, the voltage of the second node N2 may be lower than a voltage difference obtained by subtracting the threshold voltage of the third transistor T3 from the voltage of the high level of the compensation signal GC.

[0148] Reference Fig.18 , when the first transistor T1 is in the on state, the voltage of the second node N2 may be lower than the sum of the power supply voltage ELVDD and the threshold voltage of the first transistor T1. In addition, the fourth transistor T4 and the fifth transistor T5 may be in the off state.

[0149] Reference Fig.17 and Fig.18 In the second period TP2D, whether the first transistor T1 is in the off state or the on state, the voltage of the second node N2 can be initialized. In addition, in the second period TP2D, whether the third transistor T3 is in the off state or the on state, the voltage of the second node N2 can be initialized. In addition, in the second period TP2D, whether the fourth transistor T4 is in the off state or the on state, the voltage of the second node N2 can be initialized.

[0150] Reference Fig.15 and Fig.19 In the third period TP3D, the write signal GW[N] may change from valid to invalid, the next-stage write signal GW[N+1] may change from invalid to valid, and the compensation signal GC may be invalid.

[0151] Reference Fig.19 , since the write signal GW can change from valid to invalid, the second transistor T2 can be turned off. Because the next-level write signal GW[N+1] can change from invalid to valid, the fourth transistor T4 can be turned on. Therefore, the fourth node N4 can be initialized to the initialization voltage VINIT. The third capacitor C3 can couple the voltage change of the next-level write signal GW[N+1], and the voltage change of the next-level write signal GW[N+1] can be applied to the second node N2. Because the voltage difference obtained by subtracting the voltage of the first electrode (e.g., the source) of the first transistor T1 from the voltage of the second node N2 can be lower than the threshold voltage of the first transistor T1, the first transistor T1 can be turned on. Because the voltage difference obtained by subtracting the voltage at the second node N2 from the voltage of the control electrode of the third transistor T3 can be higher than the threshold voltage of the third transistor T3, the third transistor T3 can be turned off. For example, in the second period TP2D, when the voltage of the second node N2 can be approximately 10.52V, the threshold voltage of the first transistor T1 can be approximately -1.52V, the voltage of the low level of the next level write signal GW[N+1] can be approximately -28V, the voltage of the high level of the next level write signal GW[N+1] can be approximately 11V, and the capacitance ratio of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 can be 1:49:20:30, the voltage applied through the third capacitor C3 via the voltage change of the coupling initialization signal GI can be approximately -7.8V, and the voltage of the second node N2 can be approximately 2.72V.

[0152] Reference Fig.15 and Fig. 20In the fourth period TP4D, the write signal GW[N] may change from invalid to valid, the next-stage write signal GW[N+1] may change from valid to invalid, and the compensation signal GC may change from invalid to valid.

[0153] Reference Fig. 20 , because the next-stage write signal GW[N+1] can change from valid to invalid, the fourth transistor T4 can be turned off. Because the next-stage write signal GW[N+1] can change from valid to invalid, the third capacitor C3 can couple the voltage change of the next-stage write signal GW[N+1] and apply the voltage change of the next-stage write signal GW[N+1] to the second node N2. Therefore, the first transistor T1 can remain in the on state. Because the write signal GW can change from invalid to valid, the sixth capacitor C6 can couple the voltage change of the write signal GW and apply the voltage change of the write signal GW to the fourth node N4. Because the voltage difference obtained by subtracting the voltage of the fourth node N4 from the voltage of the control electrode of the fifth transistor T5 can be higher than the threshold voltage of the fifth transistor T5, the fifth transistor T5 can be turned off.

[0154] Reference Fig.15 and Fig.21 , in the fifth period TP5D, the write signal GW[N] may be valid, the next-stage write signal GW[N+1] may be invalid, and the compensation signal GC may be valid.

[0155] Reference Fig.21 , the first power supply voltage ELVDD may be applied to the first electrode of the first capacitor C1, and the voltage of the second electrode of the first capacitor C1 may be the voltage of the second node N2, and the voltage of the second node N2 is the sum of the first power supply voltage ELVDD and the threshold voltage of the first transistor T1. Therefore, the threshold voltage of the first transistor T1 may be stored between the first electrode of the first capacitor C1 and the second electrode of the first capacitor C1. The operation of storing the threshold voltage of the first transistor T1 between the first electrode of the first capacitor C1 and the second electrode of the first capacitor C1 is referred to as a "compensation operation" herein.

[0156] Reference Fig.15 and Fig. 22 In the sixth period TP6D, the write signal GW[N] may be valid, the next-stage write signal GW[N+1] may change from invalid to valid, and the compensation signal GC may change from valid to invalid. For example, when the first power supply voltage is about 7V and the threshold voltage of the first transistor T1 is about -1.52V, the voltage of the second node N2 may be about 5.48V.

[0157] Reference Fig. 22, because the compensation signal GC can be changed from valid to invalid, the third transistor T3 can be turned off. Because the next-level write signal GW[N+1] can be changed from invalid to valid, the fourth transistor T4 can be turned on. Therefore, the voltage of the fourth node N4 can be initialized to the initialization voltage VINIT. Because the voltage of the fourth node N4 can have the initialization voltage VINIT, the fifth transistor T5 can be turned off. The voltage of the second node N2 in the sixth period TP6D can be the same as the voltage of the second node N2 in the fifth period TP5D.

[0158] Reference Fig.15 and Fig.23 , the write signal GW[N] may be valid, the next-stage write signal GW[N+1] may be valid, and the compensation signal GC may be invalid.

[0159] Reference Fig.23 The second transistor T2 may be turned on in response to the write signal GW[N]. The second capacitor C2 may apply the data voltage VDATA to the second node N2.

[0160] In the seventh period TP7D, the voltage of the first node N1 may be the data voltage VDATA, and the voltage of the second node N2 may be ELVDD+T1_VTH+C2 / (C1+C2+C3+C4)×(VDATA–VREF). In this article, C1 represents the capacitance of the first capacitor C1, C2 represents the capacitance of the second capacitor C2, C3 represents the capacitance of the third capacitor C3, and C4 represents the capacitance of the fourth capacitor C4. In addition, T1_VTH represents the threshold voltage of the first transistor T1. For example, when the first power supply voltage ELVDD is about 7V, the threshold voltage of the first transistor T1 is about -1.52V, the data voltage VDATA is about -13V, the reference voltage VREF is about -9V, and the capacitance ratio of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is about 1:49:20:30, the voltage of the second node N2 may be about -5.3V.

[0161] Reference Fig.15 and Fig.24 , in the eighth period TP8D, the write signal GW[N] may change from valid to invalid, the next-stage write signal GW[N+1] may be valid, and the compensation signal GC may be invalid.

[0162] Reference Fig.24 , because the write signal GW[N] may change from valid to invalid, the second transistor T2 may be turned off. The voltage of the second node N2 in the eighth period TP8D may be the same as the voltage of the second node N2 in the seventh period TP7D.

[0163] Reference Fig.15 and Fig.25 In the ninth period TP9D, the write signal GW[N] may be invalid, the next-level write signal GW[N+1] may change from valid to invalid, and the compensation signal GC may be invalid.

[0164] Reference Fig.25 , because the next-stage write signal GW[N+1] can change from valid to invalid, the fourth transistor T4 can be turned off. The third capacitor C3 can couple the voltage change of the next-stage write signal GW[N+1] and apply the voltage change of the next-stage write signal GW[N+1] to the second node N2. The second capacitor C2 can apply the data voltage VDATA to the second node N2 using a bootstrap method.

[0165] The voltage of the second node N2 may be a final compensation voltage. The final compensation voltage may be ELVDD+T1_VTH+C2 / (C1+C2+C3+C4) × (VDATA–VREF)+C3 / (C1+C4+C3+C5C2Eq.cap)(–1 ×GW[N+1][TP8D]+GW[N+1][TP9D]). C1 represents the capacitance of the first capacitor C1, C2 represents the capacitance of the second capacitor C2, C3 represents the capacitance of the third capacitor C3, and C4 represents the capacitance of the fourth capacitor C4. In addition, T1_VTH represents the threshold voltage of the first transistor, C5C2Eq.cap represents the equivalent capacitance of the capacitance of the fifth capacitor C5 and the capacitance of the second capacitor C2, GW[N+1][TP8D] represents the voltage of the next-stage write signal GW[N+1] in the eighth period TP8D, and GW[N+1][TP9D] represents the voltage of the next-stage write signal GW[N+1] in the ninth period TP9D. Therefore, the second node N2 may have a final compensation voltage. For example, when the value of ELVDD+T1_VTH+C2 / (C1+C2+C3+C4)×(VDATA–VREF) is about −5.3V, the voltage of the high level of the next-stage write signal GW[N+1] is about 11V, the voltage of the low level of the next-stage write signal GW[N+1] is about −28V, and the capacitance ratio of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 is 1:1, the voltage of the second node N2 may be about 2.8935V.

[0166] Reference Fig.15 and Fig.26 , in the tenth period TP10D, the write signal GW[N] may be invalid, the next-stage write signal GW[N+1] may be invalid, and the compensation signal GC may be invalid.

[0167] Reference Fig.26 , when a voltage difference obtained by subtracting the first power voltage ELVDD from the data voltage VDATA is lower than a threshold voltage of the fifth transistor T5, the fifth transistor may be turned on.

[0168] The light emitting element EE may emit light in response to a current flowing through the first transistor T1 , the fifth transistor T5 , and the light emitting element EE.

[0169] According to the present embodiment, the pixel circuit 900 may include five transistors T1 to T5 and six capacitors C1 to C6. The pixel circuit 900 may perform internal compensation and may have a relatively small number of transistors compared to conventional pixel circuits, thereby achieving high integration. Therefore, the pixel circuit 900 may be applied to ultra-high resolution display devices. In addition, the control electrode of the fifth transistor T5 may receive the voltage of the first node N1 instead of the emission signal. Therefore, a display device including the pixel circuit 900 may operate without an emission driver, resulting in cost reduction and high-resolution design.

[0170] Fig. 27 is shown applied to Fig.14 FIG. 1 is a timing diagram of an example of an input signal of a pixel circuit.

[0171] The pixel circuit according to this embodiment Fig.14 The pixel circuit 900 is the same as that in FIG. 1 , but the driving timing according to this embodiment is the same as that in FIG. Fig.15 The same reference numerals are used for components that are the same as or similar to those in the previous embodiment, and redundant descriptions are omitted.

[0172] Reference Fig. 27, in the first period TP1E, the write signal GW[N] may change from invalid to valid, the next level write signal GW[N+1] may be invalid, and the compensation signal GC[N] may be invalid. In the second period TP2E, the write signal GW[N] may be valid, the next level write signal GW[N+1] may be invalid, and the compensation signal GC[N] may be invalid. In the third period TP3E, the write signal GW[N] may change from valid to invalid, the next level write signal GW[N+1] may change from invalid to valid, and the compensation signal GC[N] may remain invalid. In the fourth period TP4E, the write signal GW[N] may change from invalid to valid, the next level write signal GW[N+1] may change from valid to invalid, and the compensation signal GC[N] may change from invalid to valid. In the fifth period TP5E, the write signal GW[N] may be valid, the next level write signal GW[N+1] may be invalid, and the compensation signal GC[N] may be valid. In the sixth period TP6E, the write signal GW[N] may change from valid to invalid, the next level write signal GW[N+1] may change from invalid to valid, and the compensation signal GC[N] may change from valid to invalid. In the seventh period TP7E, the write signal GW[N] may remain invalid, the next level write signal GW[N+1] may change from valid to invalid, and the compensation signal GC[N] may remain invalid. In the eighth period TP8E, the write signal GW[N] may be invalid, the next level write signal GW[N+1] may be invalid, and the compensation signal GC[N] may be invalid.

[0173] Fig.28 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept. Fig.29 It is shown Fig.28 A diagram of an example in which the electronic device is implemented as a smart phone.

[0174] Reference Fig.28 and Fig.29 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In this document, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0175] According to an embodiment, Fig.28As shown in , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a laptop computer, and a head mounted display (HMD) device, etc.

[0176] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0177] The processor 1010 may Figure 1 The driving controller 200 outputs input image data IMG and an input control signal CONT.

[0178] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0179] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, and a touch screen, and output devices such as a printer and a speaker. In some embodiments, the display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0180] The present disclosure achieves a high degree of integration. Therefore, the pixel circuit can be applied to ultra-high resolution display devices. In addition, the display device does not rely on an emission driver to operate, which can be advantageous for cost reduction and high-resolution design.

[0181] The foregoing is an illustration of the inventive concept and should not be construed as a limitation on the inventive concept. Although some embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all of these modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function clause is intended to cover the structures described herein that perform the functions described, and includes not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is an illustration of the inventive concept and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and the equivalents of the claims will be included therein.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a first transistor including a control electrode connected to the second node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a write signal, a first electrode connected to the data line, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a compensation signal, a first electrode connected to the second node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node; a fifth transistor including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode configured to receive a second power supply voltage.

2. The pixel circuit according to claim 1, wherein: The pixel circuit further comprises: a first capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and A third capacitor includes a first electrode connected to the control electrode of the fourth transistor and a second electrode connected to the second node.

3. The pixel circuit according to claim 2, wherein: The frame period of the pixel circuit includes: A first time period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; a second period, during which the initialization signal changes from invalid to valid, the compensation signal is invalid, and the write signal is valid; a third time period, during which the initialization signal is valid, the compensation signal is valid, and the write signal is valid; a fourth period, during which the initialization signal changes from valid to invalid, the compensation signal is invalid, and the write signal is valid; and A fifth period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

4. The pixel circuit according to claim 3, wherein: In the first period, the second transistor is in a turned-on state in response to the write signal, a reference voltage of the data line is applied to the control electrode of the fifth transistor, and a voltage of the second node is initialized.

5. The pixel circuit according to claim 3, wherein: In the second period, the fourth transistor is in a turned-on state in response to the initialization signal, the initialization voltage is applied to the fourth node, the fifth transistor is in a turned-off state, and the first transistor is in a turned-on state in response to a coupling operation of the third capacitor.

6. The pixel circuit according to claim 3, wherein: In the third period, the third transistor is in a turned-on state in response to the compensation signal, and a threshold voltage of the first transistor is stored between the first electrode of the first capacitor and the second electrode of the first capacitor.

7. The pixel circuit according to claim 3, wherein: In the fourth time period, the third transistor is in a cut-off state in response to the invalid state of the compensation signal, the second transistor transmits the data voltage of the data line to the first node in response to the valid state of the write signal, and the data voltage of the first node is applied to the second node in response to the coupling operation of the second capacitor.

8. The pixel circuit according to claim 3, wherein: In the fifth period, the second transistor is in a turned-off state in response to the compensation signal, and the fifth transistor is turned on based on the voltage of the first node.

9. The pixel circuit according to claim 2, wherein: The frame period of the pixel circuit includes: a first period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid; a second period, during which the initialization signal is valid, the compensation signal is invalid, and the write signal is valid; a third period, during which the initialization signal is valid, the compensation signal is valid, and the write signal is valid; and a fourth period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; and A fifth period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

10. The pixel circuit according to claim 2, wherein: The frame period of the pixel circuit includes: A first time period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; a second period, during which the initialization signal changes from invalid to valid, the compensation signal is invalid, and the write signal is valid; a third period, during which the initialization signal is valid, the compensation signal is invalid, and the write signal is invalid; a fourth time period, during which the initialization signal is valid, the compensation signal is valid, and the write signal is invalid; a fifth period, in which the initialization signal changes from valid to invalid, the compensation signal changes from invalid, and the write signal changes from invalid to valid; and A sixth period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

11. The pixel circuit according to claim 1, wherein: The initialization voltage is the second power supply voltage.

12. The pixel circuit according to claim 1, wherein: The pixel circuit further comprises: a first capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and The third capacitor includes a first electrode configured to receive the compensation signal and a second electrode connected to the second node.

13. The pixel circuit according to claim 1, wherein: The pixel circuit further comprises: a first capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a third capacitor including a first electrode connected to the control electrode of the fourth transistor and a second electrode connected to the second node; a fourth capacitor including a first electrode connected to the control electrode of the third transistor and a second electrode connected to the second node; a fifth capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the first node; and a sixth capacitor including a first electrode connected to the fourth node and a second electrode connected to the control electrode of the second transistor, Wherein, the initialization signal is a next-level write signal of the next level.

14. The pixel circuit according to claim 13, wherein: The frame period of the pixel circuit includes: A first period, during which the write signal changes from invalid to valid, the next-level write signal is invalid, and the compensation signal is invalid; a second period, during which the write signal is valid, the next-level write signal is invalid, and the compensation signal is invalid; a third period, during which the write signal changes from valid to invalid, the next-level write signal changes from invalid to valid, and the compensation signal is invalid; a fourth period, during which the write signal changes from invalid to valid, the next-stage write signal changes from valid to invalid, and the compensation signal changes from invalid to valid; a fifth period, during which the write signal is valid, the next-stage write signal is invalid, and the compensation signal is valid; a sixth period, in which the write signal is valid, the next-level write signal changes from invalid to valid, and the compensation signal changes from valid to invalid; a seventh period, during which the write signal is valid, the next-level write signal is valid, and the compensation signal is invalid; an eighth period, during which the write signal changes from valid to invalid, the next-level write signal is valid, and the compensation signal is invalid; a ninth period, during which the write signal is invalid, the next-level write signal changes from valid to invalid, and the compensation signal is invalid; and A tenth time period, in which the write signal and the next-level write signal are invalid, and the compensation signal is invalid.

15. The pixel circuit according to claim 14, wherein: In the ninth period, the third transistor is in a cut-off state in response to the compensation signal, a coupling voltage is applied to the second node in response to a coupling operation of the third capacitor, and a voltage of the second node has a final compensation voltage.

16. The pixel circuit according to claim 14, wherein: In the tenth period, the data voltage of the data line is applied to the control electrode of the fifth transistor, and the data voltage is lower than the sum of the first power voltage and a threshold voltage of the fifth transistor, and the fifth transistor is in a turned-on state.

17. The pixel circuit according to claim 13, wherein: The frame period of the pixel circuit includes: A first period, during which the write signal changes from invalid to valid, the next-level write signal is invalid, and the compensation signal is invalid; a second period, during which the write signal is valid, the next-level write signal is invalid, and the compensation signal is invalid; a third period, during which the write signal changes from valid to invalid, the next-level write signal changes from invalid to valid, and the compensation signal is invalid; a fourth period, during which the write signal changes from invalid to valid, the next-stage write signal changes from valid to invalid, and the compensation signal changes from invalid to valid; a fifth period, during which the write signal is valid, the next-stage write signal is invalid, and the compensation signal is valid; a sixth period, in which the write signal changes from valid to invalid, the next-level write signal changes from invalid to valid, and the compensation signal changes from valid to invalid; a seventh period, during which the write signal is invalid, the next-level write signal changes from valid to invalid, and the compensation signal is invalid; and An eighth period, during which the write signal is invalid, the next-level write signal is invalid, and the compensation signal is invalid.

18. A display device, wherein: The display device comprises: A display panel including a pixel circuit; a gate driver configured to output a write signal, a compensation signal, and an initialization signal to the pixel circuit; and a data driver configured to output a data voltage or a reference voltage to the pixel circuit, Wherein, the pixel circuit comprises: a first transistor including a control electrode connected to the second node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a third node; a second transistor including a control electrode configured to receive a write signal, a first electrode connected to the data line, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a compensation signal, a first electrode connected to the second node, and a second electrode connected to the third node; a fourth transistor including a control electrode configured to receive an initialization signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to a fourth node; a fifth transistor including a control electrode connected to the first node, a first electrode connected to the third node, and a second electrode connected to the fourth node; and The light emitting element includes a first electrode connected to the fourth node and a second electrode configured to receive a second power supply voltage.

19. The display device according to claim 18, wherein: The pixel circuit further comprises: a first capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the second node; a second capacitor including a first electrode connected to the first node and a second electrode connected to the second node; and A third capacitor includes a first electrode connected to the control electrode of the fourth transistor and a second electrode connected to the second node.

20. The display device according to claim 18, wherein: The frame period of the pixel circuit includes: A first time period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is valid; a second period, during which the initialization signal changes from invalid to valid, the compensation signal is invalid, and the write signal is valid; a third time period, during which the initialization signal is valid, the compensation signal is valid, and the write signal is valid; a fourth period, during which the initialization signal changes from valid to invalid, the compensation signal is invalid, and the write signal is valid; and A fifth period, during which the initialization signal is invalid, the compensation signal is invalid, and the write signal is invalid.

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