Semiconductor device and memory system

Abstract

The invention discloses a semiconductor device and a storage system, and the semiconductor device comprises at least two storage queues which are arranged along a first direction Y, each storage queue comprises a plurality of storage blocks, and the plurality of storage blocks are arranged along a second direction X; a word line extending in a second direction X and connected to the plurality of memory blocks; the bit line extends along the first direction and is connected with one storage block; wherein the first direction Y and the second direction X intersect. According to the invention, the storage queue is divided into a plurality of storage blocks, and the length of each word line is shortened, so that the impedance in the data transmission process is reduced, and the data transmission efficiency is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of electronic devices, and in particular, to a semiconductor device and a storage system. Background Art

[0002] With the development of semiconductor devices, the number of memory layers manufactured is increasing. During the use of multi-level memory, it is easy to be affected by the internal layout, resulting in the data transmission rate and storage efficiency of the memory being unable to meet higher storage requirements. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device and a storage system to solve the technical problem in the prior art that the number of memory layers cannot meet higher storage requirements after increasing.

[0004] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, including:

[0006] At least two storage queues, the at least two storage queues are arranged along a first direction Y, the storage queues include a plurality of storage blocks, and the plurality of storage blocks are arranged along a second direction X;

[0007] a word line extending along the second direction and connected to a plurality of the storage blocks;

[0008] a bit line extending along the first direction and connected to one of the memory blocks;

[0009] The first direction Y intersects with the second direction X.

[0010] In combination with the first aspect, the ratio of the sum of the sizes of all the storage blocks along the first direction to the size of one of the storage blocks along the first direction is 1-32.

[0011] In combination with the first aspect, a ratio of a sum of dimensions of all the bit lines along the first direction to a dimension of one of the bit lines along the first direction is 1-16.

[0012] In combination with the first aspect, the plurality of storage blocks have the same or different sizes along the first direction.

[0013] In combination with the first aspect, there are a plurality of bit lines, each of the storage blocks is connected to a plurality of the bit lines, and the bit lines are connected to bits.

[0014] In combination with the first aspect, there are multiple sites, one site is connected to one bit line, or one site is connected to multiple bit lines, wherein the multiple bit lines are connected to one storage block, or the multiple bit lines are connected to different storage blocks.

[0015] In combination with the first aspect, there are a plurality of sites, one site is connected to a sense amplifier, or a plurality of sites are connected to one sense amplifier.

[0016] In a second aspect, an embodiment of the present application provides a semiconductor device, including:

[0017] At least two storage queues, the at least two storage queues are arranged along a first direction, the storage queues include a plurality of storage blocks, and the plurality of storage blocks are arranged along a second direction;

[0018] a word line extending along the second direction and connected to a plurality of the storage blocks;

[0019] A bit line extending along the first direction and connected to one of the memory blocks, the bit line being provided with a site; and

[0020] a sense amplifier connected to the bit line;

[0021] The first direction Y intersects with the second direction X.

[0022] In combination with the second aspect, the storage queue is located in a first semiconductor structure, the sense amplifier is located in a second semiconductor structure, and the first semiconductor structure is bonded to the second semiconductor structure.

[0023] In combination with the second aspect, the storage queue and the sense amplifier are located in a same semiconductor structure, and the sense amplifier is connected to the bit line through a bit point.

[0024] In combination with the second aspect, a plurality of the bit lines in one storage block are connected to one sense amplifier.

[0025] In combination with the second aspect, each of the bit lines in the plurality of storage blocks in the same storage queue is connected to a sense amplifier; or

[0026] The bit lines in a plurality of the memory blocks in adjacent memory queues are connected to one of the sense amplifiers.

[0027] In combination with the second aspect, the storage block includes a storage area and a connection area, the connection area is located at one side of the storage area, and the site is set in the connection area.

[0028] In combination with the second aspect, a spacing structure is further included, wherein the spacing structure extends along the second direction X and is located between the storage blocks.

[0029] In combination with the second aspect, the storage block includes storage cells arranged in an array, and the storage cell includes a transistor and a capacitor connected to the transistor in a third direction Z.

[0030] In a third aspect, an embodiment of the present application provides a memory system, including:

[0031] The semiconductor device according to any one of the first aspect or the second aspect; and

[0032] A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

[0033] One of the above technical solutions has the following advantages or beneficial effects:

[0034] Compared with the prior art, the embodiment of the present application provides a semiconductor device, including: at least two storage queues, at least two storage queues are arranged along a first direction Y, the storage queues include multiple storage blocks, and the multiple storage blocks are arranged along a second direction X; word lines, the word lines extend along the second direction X and are connected to multiple storage blocks; bit lines, the bit lines extend along the first direction and are connected to one storage block; wherein the first direction Y intersects with the second direction X. The present application divides the storage queue into multiple storage blocks, and at the same time shortens the length of each word line, thereby reducing the impedance during data transmission, thereby improving the efficiency of data transmission.

[0035] The embodiment of the present application also provides a semiconductor device, including: at least two storage queues, at least two storage queues are arranged along a first direction, the storage queues include multiple storage blocks, and the multiple storage blocks are arranged along a second direction X; word lines, the word lines extend along the second direction X and are connected to multiple storage blocks; bit lines, the bit lines extend along the first direction and are connected to a storage block, and the bit lines are provided with bit points; and sense amplifiers, the sense amplifiers are connected to the bit lines; wherein the first direction Y intersects with the second direction X. The present application divides the storage queue into multiple storage blocks, and at the same time shortens the length of each word line, thereby reducing the impedance during data transmission, thereby improving the efficiency of data transmission, and the bit lines are connected to the sense amplifiers, which improves the parallelism of operations when the storage queue stores data, thereby improving the efficiency of data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 A schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application;

[0038] Figure 2 Provided in Example 1 of this application Figure 1 A schematic diagram of the local enlarged structure at C in the middle;

[0039] Figure 3 Provided for Example 2 of this application Figure 1 A schematic diagram of the local enlarged structure at C in the middle;

[0040] Figure 4 Provided in Example 3 of this application Figure 1 A schematic diagram of the local enlarged structure at C in the middle;

[0041] Figure 5 Provided for the embodiments of this application Figure 1 Schematic diagram of the cross-sectional structure at BB in the middle;

[0042] Figure 6 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of a semiconductor device structure provided for some embodiments of the present application;

[0044] Figure 8 A schematic diagram of the structure of a semiconductor device provided in some other embodiments of the present application;

[0045] Fig. 9 A schematic diagram of a method for preparing a semiconductor device according to an embodiment of the present application;

[0046] Fig.10 A schematic diagram of the local structure of a semiconductor device provided in an embodiment of the present application.

[0047] The reference numerals are as follows:

[0048] 110-storage queue, 111-word line, 112-bit line, 121-storage block, 130-capacitor, 140-connection area, 150-bit point, 160-plate line layer, 170-transistor, 180-bridge part, 200-sense amplifier, 300-bit line selection tube, 400-spacer structure, 500-semiconductor layer, 601-first dielectric layer, 602-second dielectric layer, 701-first stacking structure, 702-second stacking structure. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. In the description of the present application, it is necessary to understand that the orientation or position relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0050] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present invention.

[0051] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0052] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed.

[0053] This article uses a Cartesian coordinate system (expressed as X, Y and Z) to represent the cross-section of the memory in various directions, wherein the direction of the XY plane is parallel to the substrate, and the Z direction is perpendicular to the substrate.

[0054] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0055] The memory in the embodiment of the present invention may be a wafer or a three-dimensional memory. The three-dimensional memory may be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses or game products, etc.

[0056] See also Figure 1 and Figure 3 , Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application, Figure 2 The embodiment of this application provides Figure 1 A schematic diagram of a partially enlarged structure at C in the middle. A semiconductor device provided by an embodiment of the present application includes at least two storage queues 110, a word line 111 and a bit line 112; at least two storage queues 110 are arranged along a first direction Y, and the storage queue 110 includes a plurality of storage blocks 121, and the plurality of storage blocks 121 are arranged along a second direction X; the word line 111 extends along the second direction X and is connected to a plurality of storage blocks 121; the bit line 112 extends along the first direction Y and is connected to a storage block 121; wherein the first direction Y intersects with the second direction X. It can be understood that the semiconductor device is divided into a plurality of storage blocks 121 along the first direction Y and the second direction X, each storage block 121 has a word line 111 and a bit line 112 connected thereto, and the word line 111 connects the plurality of storage blocks 121 in series along the second direction X to form a storage queue 110, that is, in the second direction X, the plurality of storage blocks 121 share the word line 111. Each storage block 121 is only connected to a part of the bit lines 112, that is, in the first direction Y, each storage block 121 uses its own bit line 112 alone, and does not share the bit line 112 with other storage blocks 121. Therefore, when transmitting data, when it is to be transmitted to a certain storage block 121, the bit line 112 can be quickly selected through the word line 111, so as to achieve fast transmission, without causing data congestion, and higher data transmission efficiency. At the same time, the bit line 112 is short in size, the impedance formed is low, and the data transmission time is short.

[0057] See also Figure 1 and Figure 3 In some optional embodiments of the present disclosure, the ratio of the sum of the sizes of all storage blocks 121 along the first direction Y to the size of one storage block 121 along the first direction Y is 1 to 32. It is understandable that different semiconductor devices have different usage requirements, and each semiconductor device includes multiple storage areas, each storage area realizing different storage functions. Therefore, in order to meet the different usage requirements of semiconductor devices and the different functions of each storage area, the semiconductor device can be divided into storage blocks 121 of different sizes. Generally speaking, the sum of the sizes of all storage blocks 121 along the first direction Y is 10 to 500 μm, and the size of a single storage block 121 along the first direction Y is 10 to 50 μm; when the ratio of the size of a single storage block 121 to the size of all storage blocks 121 is closer to 1, the size of the storage block 121 is larger, fewer steps are required when preparing semiconductor devices, and the preparation efficiency is higher. At this time, the sum of the sizes of all storage blocks 121 along the first direction Y is close to 10 μm; and when the ratio of the size of a single storage block 121 to the size of all storage blocks 121 is closer to 32, it means that the size of the storage block 121 is smaller, the data transmission rate of the obtained semiconductor device is faster, and the storage efficiency is higher. At this time, the sum of the sizes of all storage blocks 121 along the first direction Y is close to 500 μm. In some other embodiments of the present application, the ratio of the size of a single storage block 121 to the size of all storage blocks 121 can exceed 32, and the circuit impedance formed by the semiconductor device is lower.

[0058] See also Figure 1 and Figure 3 In some optional embodiments of the present disclosure, the ratio of the sum of the sizes of all storage blocks 121 along the first direction Y to the size of a bit line 112 along the first direction Y is 1 to 16. It can be understood that the bit line 112 is used to transmit data and locate. When the size of the bit line 112 is long, it takes a certain amount of time for data to be transmitted from one end of the bit line 112 to the other end. Although the transmission speed of the electrical signal is very fast, when the amount of data increases, the long bit line 112 will increase the impedance in the line during the data transmission process, thereby reducing the data transmission rate. Therefore, when the semiconductor device is divided, the size of the bit line 112 is further divided to reduce the size of the bit line 112, and the bit line 112 is connected separately on each storage block 121 to ensure that the bit line 112 is not shared between two storage blocks 121. After the size of the bit line 112 is shortened, each bit line 112 can be quickly transmitted to the corresponding storage block 121 during data transmission, thereby speeding up the transmission of data and further speeding up the positioning of data.

[0059] See also Figure 1 and Figure 3In some optional embodiments of the present disclosure, multiple storage blocks 121 have the same or different sizes along the first direction Y. It is understandable that each storage block 121 stores different data, so the volume corresponding to each storage block 121 is also different. Since the communication between the storage blocks 121 is reduced after the storage blocks 121 are divided, it is difficult to split a continuous large data into various parts and store them in different storage queues 110 or storage blocks 121 when storing continuous large data. In order to avoid data loss or incoherence when storing large data, a partitioned storage method is adopted to store the same data in the same storage queue or storage block 121, and try to avoid data loss caused by cross-region storage. Therefore, in order to meet the needs of data of different sizes, the semiconductor device is divided into storage blocks 121 of different sizes, so as to meet the storage of data of different volumes.

[0060] See also Figure 1 and Figure 3 In some optional embodiments of the present disclosure, there are multiple bit lines 112, and each storage block 121 is connected to multiple bit lines 112, and the bit lines 112 are connected to sites 150. It can be understood that each storage block 121 includes multiple storage cells, each storage cell is connected to a bit line 112, and the storage cells can be selected and store data through the bit line 112. Sites 150 connected to other components are set on the bit lines 112, and the sites 150 can facilitate the formation of a unified connection point for the bit lines 112, and can realize the connection of multiple bit lines 112, thereby facilitating the processing of stored data.

[0061] See also Figure 1 and Figure 3In some optional embodiments of the present disclosure, there are multiple sites 150, one site 150 is connected to one bit line 112, or one site 150 is connected to multiple bit lines 112, wherein multiple bit lines 112 are connected to one storage block 121, or multiple bit lines 112 are connected to different storage blocks 121. It can be understood that the site 150 is used as a connecting contact to connect the bit line 112 with other components. When connecting the bit line 112 and the site 150, one bit line 112 can be connected to one site 150, at which time each bit line 112 is connected to the site 150 separately, and after the connection, the site 150 can be directly connected to other components; at the same time, multiple bit lines 112 can also be connected to one site 150, at which time multiple bit lines 112 act on one site 150 together. In order to avoid data duplication, it is necessary to connect a selection device between the site 150 and the bit line 112, thereby ensuring that only one bit line 112 is connected to the component at a time. It should be noted that the multiple bit lines 112 connected to a site 150 can be connected to the same storage block 121. In this case, data processing can be performed for each storage block 121 separately. At the same time, the multiple bit lines 112 connected to a site 150 can also be connected to different storage blocks 121. In this case, data of multiple different storage blocks 121 can be processed.

[0062] See also Figure 1 and Figure 3 In some optional embodiments of the present disclosure, there are multiple sites 150, one site 150 is connected to a sense amplifier 200, or multiple sites 150 are connected to one sense amplifier 200. It can be understood that the sense amplifier 200 is used to amplify the electrical signal on the bit line 112 so as to facilitate other components to read the signal. When one site 150 is connected to a sense amplifier 200, one sense amplifier 200 can process the electrical signal transmitted by one site 150; and when multiple sites 150 are connected to one sense amplifier 200, one sense amplifier 200 can process the electrical signals of multiple storage blocks 121. It should be noted that when one site 150 is connected to a sense amplifier 200, the site 150 at this time can be connected to one bit line 112 or to multiple bit lines 112; at the same time, when multiple sites 150 are connected to one sense amplifier 200, the site 150 at this time can be connected to one bit line 112 or to multiple bit lines 112. When multiple sites 150 are connected to a sensing amplifier 200, a selection tube needs to be set between the site 150 and the bit line 112 to select the bit line 112 according to the signal to prevent multiple bit lines 112 from transmitting data to the sensing amplifier 200 at the same time, causing data reading confusion and errors.

[0063] See also Figure 1 and Figure 2 , the embodiment of the present application also provides a semiconductor device, including at least two storage queues 110, word lines 111, bit lines 112 and sense amplifiers 200; at least two storage queues 110 are arranged along a first direction Y, the storage queues 110 include a plurality of storage blocks 121, and the plurality of storage blocks 121 are arranged along a second direction X; the word lines extend along the second direction X and are connected to the plurality of storage blocks 121; the bit lines 112 extend along the first direction Y and are connected to a storage block 121, and the bit lines 112 are provided with sites 150; the sense amplifiers 200 are connected to the bit lines 112; wherein the first direction Y intersects with the second direction X. It can be understood that the semiconductor device is divided into a plurality of storage blocks 121 along the first direction Y and the second direction X, each storage block 121 has a word line 111 and a bit line 112 connected thereto, and the word lines 111 connect the plurality of storage blocks 121 in series along the second direction X to form the storage queue 110, that is, in the second direction X, the plurality of storage blocks 121 share the word line 111. Each storage block 121 is only connected to one group of bit lines 112, that is, in the first direction Y, each storage block 121 uses its own bit line 112 alone, and does not share the bit line 112 with other storage blocks 121. Therefore, when transmitting data, when it is to be transmitted to a certain storage block 121, the bit line 112 can be quickly selected through the word line 111, so as to achieve fast transmission, without causing data congestion, and the data transmission efficiency is higher. At the same time, the bit line 112 is short in size, the impedance formed is low, and the data transmission time is short. The sense amplifier 200 is used to amplify the electrical signal on the bit line 112 so as to facilitate other components to read and analyze the signal. By amplifying the electrical signal of the bit line 112 by the sense amplifier 200, the data reading efficiency is effectively accelerated and the operation parallelism is improved.

[0064] See also Figure 4 and Figure 6 In some optional embodiments of the present disclosure, the storage queue 110 is located in the first semiconductor structure, the sense amplifier 200 is located in the second semiconductor structure, and the first semiconductor structure is bonded to the second semiconductor structure. It is understandable that the storage queue 110 includes a bit line 112 and a word line 111, and the arrangement of the bit line 112 and the word line 111 needs to be considered when preparing the storage queue 110. When preparing the sense amplifier 200, the influence of the external environment, such as temperature, needs to be considered. Therefore, in order to facilitate the rapid preparation of the storage queue 110 and the sense amplifier 200, the storage queue 110 and the sense amplifier 200 can be prepared in the first semiconductor structure and the second semiconductor structure respectively by different processes, and then the first semiconductor structure and the second semiconductor structure are bonded to each other through the reserved bonding points, thereby realizing the connection between the storage queue 110 and the sense amplifier 200.

[0065] See also Figure 2 and Figure 7 In some optional embodiments of the present disclosure, the storage queue 110 and the sense amplifier 200 are located in the same semiconductor structure, and the sense amplifier 200 is connected to the bit line 112 through the site 150. It can be understood that when the storage queue 110 and the sense amplifier 200 are integrated into a semiconductor structure, the connection between the storage queue 110 and the sense amplifier 200 can be reduced, so that the data transmission speed of the semiconductor device is faster, the response is more sensitive, the operation parallelism is significantly improved, and the overall volume of the semiconductor structure can also be reduced. In some other optional embodiments of the present disclosure, such as Figure 8 As shown, a portion of the sensing amplifier 200 is located in the first semiconductor structure, while another portion of the sensing amplifier 200 and the storage queue 110 are located together in the second semiconductor structure, and then the first semiconductor structure and the second semiconductor structure are bonded and connected through the reserved bonding points. By respectively arranging the sensing amplifier 200 in the first semiconductor structure and the second semiconductor structure, it is possible to change the shape and volume of the semiconductor device, and at the same time, different connection methods can be designed according to the different positions of the storage queue 110. For example, the sensing amplifier 200 connected to the storage queues 110 located at both ends can be arranged in the semiconductor structure where the storage queue 110 is located, and the sensing amplifier 200 connected to the storage queue 110 located in the middle position can be arranged in another semiconductor structure, thereby reducing the volume of the structures at both ends of the semiconductor device, thereby meeting different assembly design requirements.

[0066] See also Figure 2 In some optional embodiments of the present disclosure, a plurality of bit lines 112 in a storage block 121 are connected to a sense amplifier 200. It is understandable that a plurality of bit lines 112 in a storage block 121 may be connected to a sense amplifier 200 or all bit lines 112 in a storage block 121 may be connected to a sense amplifier 200, that is, a storage block 121 is connected to a sense amplifier 200. By processing data on one or more storage blocks 121 through a sense amplifier 200, the operational parallelism of the semiconductor device may be improved, thereby improving the efficiency of data transmission and storage.

[0067] See also Fig.10In some optional embodiments of the present disclosure, each bit line 112 in a plurality of storage blocks 121 in the same storage queue 110 is connected to a sense amplifier 200; or the bit lines 112 in a plurality of storage blocks 121 in adjacent storage queues 110 are connected to a sense amplifier 200. It is understandable that one or more bit lines 112 in different storage blocks 121 are connected to a sense amplifier 200, so as to process data of different storage blocks 121, wherein the different storage blocks 121 may be from the same storage queue 110, or may be adjacent or non-adjacent storage blocks 121. By sharing a sense amplifier 200 for a plurality of storage blocks 121, the parallelism of data transmission and storage is improved.

[0068] See also Figure 2 In some optional embodiments of the present disclosure, the storage block 121 includes a storage area A3 and a connection area 140. The connection area 140 is located on one side of the storage area A3, and the site 150 is set in the connection area 140. It can be understood that the connection area 140 can also be called a stacking area, which is stacked by multiple levels to form a step shape, and is used to lead out corresponding pins or contacts at each level of the semiconductor. In some optional embodiments of the present disclosure, the connection area 140 is used to lead out the connection point of the bit line 112, that is, the site 150. The site 150 is set on the connection area 140, so as to facilitate the connection between the site 150 and the sense amplifier 200, such as Figure 2 As shown, a bit line selection tube 300 is connected between the bit point 150 and the sense amplifier 200. The bit line selection tube 300 selects one of the multiple bit lines 112 to be connected to the sense amplifier 200, and isolates the electrical signals of the other bit lines 112, ensuring that the sense amplifier 200 only processes the data in one bit line 112 at the same time, thereby avoiding data confusion and errors. Figure 4 As shown, the first storage block A1 and the second storage block A2 are arranged opposite to each other, and the first storage block A1 and the second storage block A2 share a connection area 140. The storage areas of the first storage block A1 and the second storage block A2 are respectively located on both sides of the common connection area 140. At the same time, the common connection area 140 is respectively provided with sites 150 connected to the respective bit lines 112 on the first storage block A1 and the second storage block A2. The common connection area 140 can reduce the corresponding area of ​​the semiconductor structure, thereby improving area utilization, and also facilitates the connection of adjacent storage blocks 121 or adjacent storage queues 110 to the shared sense amplifier 200, further reducing space utilization.

[0069] See also Figure 5In some optional embodiments of the present disclosure, a spacing structure 400 is further included. The spacing structure 400 extends along the second direction X and is located between the storage blocks 121. It can be understood that the spacing structure 400 is used to separate the storage blocks 121. Separating the storage blocks 121 by the spacing structure 400 can reduce the impact between the storage blocks 121, and the spacing structure 400 can also enhance the structural strength of the semiconductor device.

[0070] See also Figure 5 In some optional embodiments of the present disclosure, the storage block 121 includes storage cells arranged in an array, and the storage cell includes a transistor 170 and a capacitor 130 connected to the transistor 170 in a third direction Z. It can be understood that a storage block 121 includes a plurality of storage cells, each of which is formed by combining a transistor 170 and a capacitor 130. Each storage cell is connected to a word line 111 and a bit line 112, and each storage cell is positioned and selected by the word line 111 and the bit line 112, so as to achieve data storage.

[0071] See also Figure 5 and Fig. 9 The present application also provides a method for preparing a semiconductor device, the method comprising the following steps:

[0072] S1: forming a first stacking structure 701 on one side of the provided semiconductor layer 500, wherein the first stacking structure 701 includes a plurality of plate line layers 160 and a plurality of first dielectric layers 601 arranged alternately; forming a plurality of receiving holes penetrating the first stacking structure 701 to the semiconductor layer 500 along a third direction Z;

[0073] S2: forming a capacitor 130 in the receiving hole, wherein a plurality of capacitors 130 are arranged along a third direction Z perpendicular to the semiconductor layer 500;

[0074] S3: forming at least one first isolation trench penetrating the first stacking structure 701 to the semiconductor layer 500 along the third direction Z; the first isolation trenches are sequentially arranged along the second direction X and all extend along the first direction Y; at least one spacing structure 400 separates the first stacking structure 701 into a plurality of storage blocks arranged along the second direction X;

[0075] S4: forming a second stacked structure 702 on a side of the first stacked structure 701 away from the semiconductor layer 500; the second stacked structure 702 includes: a word line layer, and second dielectric layers 602 located on opposite sides of the word line layer;

[0076] forming a plurality of channel holes penetrating the second stack structure 702 to the first stack structure 701;

[0077] A gate dielectric layer and a channel layer are sequentially formed in a plurality of channel holes to form a channel structure; the gate dielectric layer is located between the word line layer and the channel layer, and the gate dielectric layer, the channel layer and the word line layer surround the gate dielectric layer to form a transistor 170, and the transistor 170 is electrically connected to the capacitor 130.

[0078] S5: forming a plurality of second isolation trenches penetrating the second stacking structure 702 to the first stacking structure 701 , wherein the plurality of second isolation trenches are sequentially arranged along the first direction Y and all extend along the second direction X; forming a second isolation structure in the second isolation trench; and the plurality of second isolation structures divide the word line layer into a plurality of word lines 111 .

[0079] S6 : forming a bridge layer on a side of the second stacked structure 702 away from the semiconductor layer 500 ; the bridge layer includes a plurality of bridge portions 180 , one end of the bridge portion 180 contacts the channel layer of the transistor 170 , and the other end contacts the bit line 112 .

[0080] S7: forming a bit line layer on a side of the second stacked structure 702 away from the semiconductor layer 500; the bit line layer includes a plurality of bit lines 112 extending along the second direction X and sequentially arranged along the second direction X; the bit lines 112 are electrically connected to the plurality of transistors.

[0081] In some optional embodiments of the present disclosure, when the sensing amplifier 200 and the storage queue 110 are located in the same semiconductor structure, it is necessary to first form the sensing amplifier 200 on the semiconductor layer 500 and then perform the above steps S1-S7, so as to integrate the sensing amplifier 200 and the storage queue 110 in one semiconductor structure; when the sensing amplifier 200 and the storage queue 110 are located in different semiconductor structures, first perform the above steps S1-S7 in the first semiconductor structure to obtain a first semiconductor device, and then prepare the sensing amplifier 200 in another semiconductor structure to obtain a second semiconductor device, and finally bond the two semiconductor devices to each other to obtain a semiconductor device with a storage function.

[0082] The present application also provides a storage system, including:

[0083] A semiconductor device as provided in any of the above embodiments; and a controller, the controller being electrically connected to the semiconductor device and configured to control the semiconductor device to store data.

[0084] The semiconductor device and storage system provided in the embodiments of the present application are introduced in detail above. The principles and implementation methods of the present application are explained in this article using specific examples. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: At least two storage queues, the at least two storage queues are arranged along a first direction (Y), the storage queues include a plurality of storage blocks, and the plurality of storage blocks are arranged along a second direction (X); a word line extending along the second direction and connected to a plurality of the storage blocks; a bit line extending along the first direction and connected to one of the memory blocks; Wherein, the first direction (Y) intersects with the second direction (X).

2. The semiconductor device according to claim 1, wherein: The ratio of the sum of the sizes of all the storage blocks along the first direction to the size of one storage block along the first direction is 1-32.

3. The semiconductor device according to claim 1 or 2, characterized in that: The ratio of the sum of the dimensions of all the bit lines along the first direction to the dimension of one of the bit lines along the first direction is 1-16.

4. The semiconductor device according to claim 1, wherein: The plurality of storage blocks have the same or different sizes along the first direction.

5. The semiconductor device according to claim 1, wherein: There are a plurality of bit lines, each of the storage blocks is connected to a plurality of the bit lines, and the bit lines are connected to bits.

6. The semiconductor device according to claim 5, characterized in that There are multiple sites, one site is connected to one bit line, or one site is connected to multiple bit lines, wherein the multiple bit lines are connected to one storage block, or the multiple bit lines are connected to different storage blocks.

7. The semiconductor device according to claim 5 or 6, characterized in that: There are a plurality of sites, and one of the sites is connected to a sense amplifier, or a plurality of the sites are connected to one sense amplifier.

8. A semiconductor device, characterized in that: include: At least two storage queues, the at least two storage queues are arranged along a first direction, the storage queues include a plurality of storage blocks, and the plurality of storage blocks are arranged along a second direction; a word line extending along the second direction and connected to a plurality of the storage blocks; A bit line, the bit line extending along the first direction and connected to one of the storage blocks, the bit line being provided with a site; as well as a sense amplifier connected to the bit line; Wherein, the first direction (Y) intersects with the second direction (X).

9. The semiconductor device according to claim 8, characterized in that The storage queue is located in a first semiconductor structure, the sense amplifier is located in a second semiconductor structure, and the first semiconductor structure is bonded to the second semiconductor structure.

10. The semiconductor device according to claim 8, characterized in that The storage queue and the sense amplifier are located in a same semiconductor structure, and the sense amplifier is connected to the bit line through a bit point.

11. The semiconductor device according to claim 8, characterized in that A plurality of the bit lines in one memory block are connected to one sense amplifier.

12. The semiconductor device according to claim 8, characterized in that Each of the bit lines in the plurality of storage blocks in the same storage queue is connected to a sense amplifier; or The bit lines in a plurality of the memory blocks in adjacent memory queues are connected to one of the sense amplifiers.

13. The semiconductor device according to claim 8, characterized in that The storage block includes a storage area and a connection area, the connection area is located at one side of the storage area, and the site is set in the connection area.

14. The semiconductor device according to claim 8, characterized in that It also includes a spacing structure, which extends along the second direction and is located between the storage blocks.

15. The semiconductor device according to claim 8, characterized in that The memory block includes memory cells arranged in an array, and the memory cell includes a transistor and a capacitor connected to the transistor in a third direction (Z).

16. A storage system, characterized in that: include: A semiconductor device as claimed in any one of claims 1 to 7 or 8 to 15; as well as A controller is electrically connected to the semiconductor device and is used to control the semiconductor device to store data.

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