Write execution signal control circuit and memory thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a write-in execution signal control circuit and a memory thereof, and the write-in execution signal control circuit comprises a mode register which is configured to output N pieces of configuration information with different values; the write command execution duration control circuit is configured to receive a write command and generate M write execution signals based on the N pieces of configuration information with different values; wherein the M clock cycle lengths of the write-in execution signal continuous effective level are different from one another, and N > = M > 1. The embodiment of the invention is at least beneficial to reducing circuit power consumption.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular to a write execution signal control circuit and a memory thereof. Background Art

[0002] In dynamic random access memory (DRAM), write-related operations are performed after decoding to generate a write command. The maximum cycle for executing a write command is the reference cycle. Usually, some redundant clock cycle lengths are added to the clock cycle length of the reference cycle as the preset clock cycle length. Generally, a valid level signal greater than the preset clock cycle length is set by a counter to include the clock signal used for the write operation, so that the clock cycle length required to perform the write operation is less than the preset clock cycle length.

[0003] However, the reference cycle has multiple different values. In order to make the clock cycle length required to perform a write operation less than the preset clock cycle length, it is necessary to design the preset clock cycle length to be greater than multiple reference cycles with different values. For some reference cycles with smaller values, that is, when the clock cycle length of the reference cycle is smaller, the clock cycle length required for the write operation is much smaller than the preset clock cycle length, resulting in unnecessary dynamic power consumption caused by constant switching of redundant clock cycles. Summary of the invention

[0004] The embodiments of the present disclosure provide a write execution signal control circuit and a memory thereof, which are at least beneficial to reducing circuit power consumption.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a write execution signal control circuit, including: a mode register, configured to output N configuration information with different values; a write command execution duration control circuit, configured to receive a write command and generate M write execution signals based on the N configuration information with different values; wherein the clock cycle lengths of the M write execution signals at a continuous valid level are different from each other, and N≥M>1.

[0006] In some embodiments, the write execution signal control circuit includes a clock counting circuit, a duration setting circuit and a write execution signal generating circuit; the clock counting circuit is used to count the clock signal cycle and output a clock cycle counting signal after counting a preset value; the duration setting circuit is used to receive the configuration information and the clock cycle counting signal, and based on the value of the configuration information, generates an intermediate signal after a preset clock cycle length, and the preset clock cycle length corresponds to the value of the configuration information; the write execution signal generating circuit is used to receive the write command and the intermediate signal, and generates the write execution signal based on the write command and the intermediate signal.

[0007] In some embodiments, the configuration information is a binary code having X bits, and the duration setting circuit is used to receive a Y-bit binary code in the X-bit binary code, wherein X≥Y≥1, and different values ​​of the configuration information correspond to write waiting cycles with different configuration clock cycle lengths.

[0008] In some embodiments, the binary code of the Y bit has M different values, and the clock counting circuit is configured to set the preset values ​​of M different values ​​corresponding to the M different values ​​of the binary code of the Y bit; wherein the maximum value of the write waiting cycle corresponding to each of the multiple values ​​of the binary code of the Y bit corresponding to the same preset value is less than the preset value.

[0009] In some embodiments, the configuration information is a 5-bit binary code, and the duration setting circuit is used to receive the values ​​of the 5th and 4th bits in the configuration information.

[0010] In some embodiments, the clock counting circuit includes: a frequency division circuit, configured to receive a first clock signal, and generate a second clock signal based on the first clock signal, wherein the clock cycle length of the second clock signal is twice the clock cycle length of the first clock signal; a counter, configured to receive the second clock signal and the write execution signal, and when the write execution signal is at a valid level, based on the second clock signal and the write execution signal, output the clock cycle count signal after counting the preset value.

[0011] In some embodiments, the clock cycle counting signal includes a first counting signal, a second counting signal and a third counting signal; the duration setting circuit includes: a configuration information processing circuit, configured to receive the configuration information and generate a first control signal, a second control signal and a third control signal based on the configuration information; a first NAND gate circuit, configured to receive the first counting signal, the second counting signal and the first control signal, and generate a first signal; a second NAND gate circuit, configured to receive the second counting signal, the third counting signal and the second control signal, and generate a second signal; a third NAND gate circuit, configured to receive the third counting signal and the third control signal, and generate a third signal; a fourth NAND gate circuit, configured to receive the first signal, the second signal and the third signal, and generate a fourth signal; a first trigger, configured to receive the fourth signal and the first clock signal, and generate the intermediate signal.

[0012] In some embodiments, the clock cycle length of the first counting signal is 16 times the clock cycle length of the first clock signal, the clock cycle length of the second counting signal is 32 times the clock cycle length of the first clock signal, and the clock cycle length of the third counting signal is 48 times the clock cycle length of the first clock signal.

[0013] In some embodiments, the write execution signal generating circuit includes: a first NOT gate circuit, configured to receive the write command and output a first input signal based on the write command; a second NOT gate circuit, configured to receive the intermediate signal and output a second input signal based on the intermediate signal; an SR latch, configured to receive the first input signal and the second input signal, and output the write execution signal based on the first input signal and the second input signal.

[0014] In some embodiments, the clock counting circuit also has a first reset terminal, which is used to receive a first reset signal; the clock counting circuit is also configured to receive the first reset signal and be reset based on the valid level of the first reset signal, and when the first reset signal is at a valid level, the write execution signal is at an invalid level.

[0015] In some embodiments, the write execution signal generating circuit also has a second reset terminal, which is used to receive a second reset signal; the write execution signal generating circuit is also configured to receive the second reset signal and be reset based on the effective level of the second reset signal; the first reset signal and the second reset signal are differential signals.

[0016] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a memory, comprising: a write execution signal control circuit according to any one of the above items.

[0017] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0018] It can be understood that the clock cycle lengths of the cycles completed by different write commands may be different, that is, the clock cycle lengths actually required to execute different write operations may be different, and different values ​​of the configuration information output by the mode register correspond to different write operations, that is, different values ​​of the configuration information correspond to different clock cycle lengths actually required to execute write operations; moreover, the clock cycle length of the write execution signal that maintains a valid level is the clock cycle length required to wait for the write operation to execute.

[0019] In this way, the write command execution time control circuit is designed so that N configuration information with different values ​​can correspond to M write execution signals, and the clock cycle lengths of the M write execution signals at the continuous effective level are different from each other, that is, configuration information with different values ​​can correspond to write execution signals with different clock cycle lengths of the continuous effective level. For example, for some configuration information with smaller values, a write command execution time control circuit can generate a write execution signal with a short clock cycle length of the continuous effective level based on the configuration information, so as to avoid the clock cycle length actually required to perform the write operation being much shorter than the clock cycle length of the continuous effective level of the write execution signal. This is beneficial to avoid dynamic power consumption caused by constant switching of redundant clock cycles while ensuring that the clock cycle length actually required to perform the write operation is shorter than the clock cycle length of the continuous effective level of the write execution signal, thereby helping to reduce circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A functional block diagram of a write execution signal control circuit provided by an embodiment of the present disclosure;

[0022] Figure 2 A functional block diagram of a write command execution time control circuit in a write execution signal control circuit provided in an embodiment of the present disclosure;

[0023] Figure 3 A corresponding relationship diagram of configuration information, write wait cycle and write execution signal provided by an embodiment of the present disclosure;

[0024] Figure 4 Another functional block diagram of a write command execution time control circuit in a write execution signal control circuit provided in an embodiment of the present disclosure;

[0025] Figure 5 and Figure 6 Two functional block diagrams of a clock counting circuit in a write execution signal control circuit provided in an embodiment of the present disclosure;

[0026] Figure 7A schematic diagram of a circuit structure of a duration setting circuit in a write execution signal control circuit provided in an embodiment of the present disclosure;

[0027] Figure 8 A schematic diagram of a circuit structure of a write execution signal generating circuit in a write execution signal control circuit provided in an embodiment of the present disclosure;

[0028] Fig. 9 and Fig.10 Two circuit structure schematic diagrams of a clock counting circuit in a write execution signal control circuit provided in an embodiment of the present disclosure;

[0029] Figures 11 to 13 Three timing diagrams of various signals corresponding to three values ​​of configuration signals in a write execution signal control circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As known from the background art, the power consumption generated when performing a write operation needs to be reduced.

[0031] The present disclosure implements a write execution signal control circuit and a memory thereof. In the write execution signal control circuit, a write command execution duration control circuit is designed so that N configuration information with different values ​​can correspond to M write execution signals, and the clock cycle lengths of the M write execution signals with continuous valid levels are different from each other, that is, configuration information with different values ​​can correspond to write execution signals with different clock cycle lengths of continuous valid levels. For example, for some configuration information with smaller values, a write execution signal with a short clock cycle length of a continuous valid level can be generated based on the configuration information by the write command execution duration control circuit to avoid the clock cycle length actually required to perform the write operation being much shorter than the clock cycle length of the continuous valid level of the write execution signal. This is beneficial to avoid dynamic power consumption caused by constant switching of redundant clock cycles while ensuring that the clock cycle length actually required to perform the write operation is shorter than the clock cycle length of the continuous valid level of the write execution signal, thereby helping to reduce circuit power consumption.

[0032] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0033] An embodiment of the present disclosure provides a write execution signal control circuit. The write execution signal control circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 1A functional block diagram of a write execution signal control circuit provided by an embodiment of the present disclosure; Figure 2 A functional block diagram of a write command execution time control circuit in a write execution signal control circuit provided in an embodiment of the present disclosure; Figure 3 A corresponding relationship diagram of configuration information, write wait cycle and write execution signal provided by an embodiment of the present disclosure; Figure 4 Another functional block diagram of a write command execution time control circuit in a write execution signal control circuit provided in an embodiment of the present disclosure; Figure 5 and Figure 6 Two functional block diagrams of a clock counting circuit in a write execution signal control circuit provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of a circuit structure of a duration setting circuit in a write execution signal control circuit provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of a circuit structure of a write execution signal generating circuit in a write execution signal control circuit provided in an embodiment of the present disclosure; Fig. 9 and Fig.10 Two circuit structure schematic diagrams of a clock counting circuit in a write execution signal control circuit provided in an embodiment of the present disclosure; Figures 11 to 13 Three timing diagrams of various signals corresponding to three values ​​of configuration signals in a write execution signal control circuit provided in an embodiment of the present disclosure.

[0034] refer to Figures 1 to 4 The write execution signal control circuit includes: a mode register 100, which is configured to output N configuration information OP with different values; a write command execution duration control circuit 101, which is configured to receive a write command WR_CMD and generate M write execution signals WR_PER based on the N configuration information OP with different values; wherein the clock cycle lengths of the M write execution signals WR_PER at the continuous valid level are different from each other, and N≥M>1.

[0035] It can be understood that the clock cycle lengths of the cycles completed by executing different write commands WR_CMD may be different, that is, the clock cycle lengths actually required to execute different write operations may be different, and different values ​​of the configuration information OP output by the mode register 100 correspond to different write operations, that is, different values ​​of the configuration information OP correspond to different clock cycle lengths actually required to execute write operations; and, the clock cycle length of the write execution signal WR_PER that continues to be at a valid level is the clock cycle length required to wait for the write operation to be executed. Generally speaking, in order to ensure the normal execution of the write operation, the clock cycle length actually required to execute the write operation should be less than the clock cycle length required to wait for the write operation to be executed.

[0036] In this way, the write command execution time length control circuit 101 is designed so that N configuration information OP with different values ​​can correspond to M write execution signals WR_PER, and the clock cycle lengths of the M write execution signals WR_PER at the continuous effective level are different from each other, that is, the configuration information OP with different values ​​can correspond to the write execution signals WR_PER at different clock cycle lengths at the continuous effective level. For example, for some configuration information OP with smaller values, the write command execution time length control circuit 101 can generate a write execution signal WR_PER with a short clock cycle length at the continuous effective level based on the configuration information OP, so as to avoid the clock cycle length actually required for executing the write operation being much shorter than the clock cycle length of the continuous effective level of the write execution signal WR_PER. This is beneficial to avoid the dynamic power consumption caused by the constant switching of redundant clock cycles, while ensuring that the clock cycle length actually required for executing the write operation is shorter than the clock cycle length of the continuous effective level of the write execution signal WR_PER, thereby reducing the power consumption of the circuit.

[0037] In addition, N≥M>1 includes at least the following two embodiments:

[0038] In some embodiments, different values ​​of the configuration information OP correspond to different write execution signals WR_PER, that is, different write execution signals WR_PER can be designed for different write commands WR_CMD based on the write command execution duration control circuit 101, and N is equal to M. In this way, the length of the clock cycle required to wait for the write operation can be adjusted according to the value of the configuration information OP, that is, the length of the clock cycle of the write execution signal WR_PER that continues to be at an effective level can be adjusted, and there is no need to determine the length of the clock cycle required to wait for the write operation according to the maximum value of the actual required clock cycle lengths of multiple write commands WR_CMD. The length of the clock cycle required to wait for different write operations can be determined according to different values ​​of the configuration information OP, that is, according to different write commands WR_CMD. This is conducive to avoiding dynamic power consumption caused by constant switching of redundant clock cycles while ensuring that the actual clock cycle length required to execute the write operation is less than the clock cycle length of the write execution signal WR_PER that continues to be at an effective level, thereby helping to reduce circuit power consumption.

[0039] In other embodiments, multiple different values ​​of the configuration information OP may correspond to the same write execution signal WR_PER, and other different values ​​of the configuration information OP may correspond to at least one other write execution signal WR_PER respectively. It can be understood that when the actual required clock cycle lengths of multiple write commands WR_CMD are close, for example, when they are within the same numerical range, the multiple different values ​​of the configuration information OP corresponding to the multiple write commands WR_CMD may be corresponded to the same write execution signal WR_PER, so that the clock cycle length of the continuous valid level of the write execution signal WR_PER is greater than the actual required clock cycle length of each write command WR_CMD in the multiple write commands WR_CMD, thereby ensuring that the multiple write commands WR_CMD can be executed normally and reducing the power consumption of the circuit, while simplifying the operation logic of the write command execution time control circuit 101, so as to reduce the complexity of the write command execution time control circuit 101, thereby helping to reduce the layout area of ​​the write command execution time control circuit 101.

[0040] It should be noted that the effective level of the write execution signal WR_PER may refer to a logic level 1 or a high level. The subsequent various signals being at an effective level may indicate that the signal is a logic level 1 or a high level, and the various signals being at an invalid level may indicate that the signal is a logic level 0 or a low level. In addition, in the description of the high level and the low level, the high level may be a level value greater than or equal to the power supply voltage, and the low level may be a level value less than or equal to the ground voltage. Moreover, the high level and the low level are relative, and the specific level value range contained in the high level and the low level may be determined according to the specific device. For example, for an NMOS tube, a high level refers to a level value range of the gate voltage that can turn on the NMOS tube, and a low level refers to a level value range of the gate voltage that can turn off the NMOS tube; for a PMOS tube, a low level refers to a level value range of the gate voltage that can turn on the PMOS tube, and a high level refers to a level value range of the gate voltage that can turn off the PMOS tube. In addition, a high level may be a logic level 1, and a low level may be a logic level 0.

[0041] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0042] In some embodiments, reference Figure 2 or Figure 3The write command execution duration control circuit 101 may include a clock counting circuit 102, a duration setting circuit 103 and a write execution signal generating circuit 104; the clock counting circuit 102 is used to count the clock signal CLK cycle, and output a clock cycle counting signal 112 after counting a preset value; the duration setting circuit 103 is used to receive configuration information OP and the clock cycle counting signal 112, and based on the value of the configuration information OP, generates an intermediate signal Time Control after a preset clock cycle length, and the preset clock cycle length corresponds to the value of the configuration information OP; the write execution signal generating circuit 104 is used to receive a write command WR_CMD and an intermediate signal Time Control, and generates a write execution signal WR_PER based on the write command WR_CMD and the intermediate signal Time Control.

[0043] It can be understood that the preset clock cycle length corresponds to the preset value, that is, the preset clock cycle length can be determined based on the preset value. The clock counting circuit 102 outputs the clock cycle counting signal 112 after counting the preset value. The time length setting circuit 103 can generate an intermediate signal TimeControl based on the value of the configuration information OP and the clock cycle counting signal 112. The intermediate signal Time Control is a pulse signal, that is, the time length setting circuit 103 can generate a rising edge or a falling edge of the intermediate signal Time Control after the preset clock cycle length based on the value of the configuration information OP and the clock cycle counting signal 112. The subsequent write execution signal generation circuit 104 controls the clock cycle length of the write execution signal WR_PER to maintain a valid level based on the write command WR_CMD and the intermediate signal Time Control.

[0044] It should be noted that Figure 2 The clock signal CLK in the following description is the first clock signal CLK1 (refer to Figure 4 ), and subsequently the clock cycle length of the first clock signal CLK1 is used as a reference, and the preset clock cycle length is determined based on the preset value, which means that the preset clock cycle length is the preset value times the clock cycle length of the first clock signal CLK1. The clock counting circuit 102, the duration setting circuit 103, and the write execution signal generating circuit 104 will be described in detail later.

[0045] In some embodiments, in conjunction with reference Figure 2 and Figure 3 The configuration information OP is a binary code with X bits, and the duration setting circuit 103 is used to receive a Y-bit binary code in the X-bit binary code, where X≥Y≥1, and different values ​​of the configuration information OP correspond to write waiting periods CL with different configuration clock cycle lengths.

[0046] It can be understood that different values ​​of the configuration information OP correspond one-to-one to write wait cycles CL with different clock cycle lengths. In this way, when the write command execution duration control circuit 101 generates M different write execution signals WR_PER based on N configuration information OP with different values, different write execution signals WR_PER can correspond to different write wait cycles CL, so that the write wait cycle CL with a shorter clock cycle length, that is, the configuration information OP with a smaller value, corresponds to the write execution signal WR_PER with a short clock cycle length of a continuous valid level, so as to avoid the clock cycle length actually required to perform the write operation being much shorter than the clock cycle length of the continuous valid level of the write execution signal WR_PER, and avoid the dynamic power consumption caused by the continuous switching of unnecessary clock cycles, thereby helping to reduce the power consumption of the circuit.

[0047] In some embodiments, reference Figure 3 and Figure 4 The configuration information OP is a 5-bit binary code, and the duration setting circuit 103 is used to receive the 5th bit OP in the configuration information OP. <6> and OP No. 4 <5> The binary code of the X bit is OP<6:2>, that is, X is 5, and the binary code of the Y bit can be OP<6:5>, that is, Y is 2. It should be noted that Figure 3 and Figure 4 In the example, only the binary code of the X bit is OP<6:2> and the binary code of the Y bit is OP<6:5>. In practical applications, there is no restriction on the values ​​of X and Y, as long as X≥Y≥1 is satisfied. There is no restriction on whether the binary code of the Y bit in the binary code of the X bit is the Y bit.

[0048] It should be noted that, taking the clock cycle length of the first clock signal CLK1 as a reference, Figure 3In the above, the write waiting cycle CL is 22, which means that the clock cycle length of the write waiting cycle CL corresponding to the binary code of the X bit OP<6:2> being 00000 is 22 times the clock cycle length of the first clock signal CLK1; the write waiting cycle CL is 24, which means that the clock cycle length of the write waiting cycle CL corresponding to the binary code of the X bit OP<6:2> being 00001 is 24 times the clock cycle length of the first clock signal CLK1... and so on, the write waiting cycle CL is 64, which means that the clock cycle length of the write waiting cycle CL corresponding to the binary code of the X bit OP<6:2> being 10101 is 64 times the clock cycle length of the first clock signal CLK1. In addition, in a corresponding write waiting cycle CL and a cycle signal CWL, the clock cycle length of the cycle signal CWL is less than the clock cycle length of the write waiting cycle CL, and the difference between the clock cycle lengths of the cycle signal CWL and the write waiting cycle CL is twice the clock cycle length of the first clock signal CLK1.

[0049] In some embodiments, the Y-bit binary code OP<6:5> has M different values, and the clock counting circuit 102 is configured to set preset values ​​of M different values ​​corresponding to the M different values ​​of the Y-bit binary code OP<6:5>; wherein the maximum value of the write wait cycle CL corresponding to the values ​​of multiple Y-bit binary codes OP<6:5> corresponding to the same preset value is less than the preset value.

[0050] It can be understood that the preset value refers to the ratio of the clock cycle length of the write execution signal WR_PER continuously at the effective level to the clock cycle length of the first clock signal CLK1, that is, Figure 3 The three values ​​of 48, 64 and 80 corresponding to the write execution signal WR_PER shown in FIG. The maximum value of the write wait period CL corresponding to the values ​​of the multiple Y-bit binary codes OP<6:5> corresponding to the same preset value refers to the maximum ratio of the clock cycle lengths of the multiple write wait periods CL corresponding to the same preset value to the clock cycle length of the first clock signal CLK1.

[0051] In some embodiments, reference Figure 3, different values ​​of the X-bit binary code OP<6:2> correspond to different write wait cycles CL of clock cycle length, and each write wait cycle CL corresponds to a cycle signal CWL. Moreover, different values ​​of the Y-bit binary code OP<6:5> in the X-bit binary code OP<6:2> correspond to different write execution signals WR_PER of different clock cycle lengths with continuous valid levels. For example, when the Y-bit binary code OP<6:5> is 00, the 8 write wait cycles CL corresponding to 00 correspond to the same write execution signal WR_PER; when the Y-bit binary code OP<6:5> is 01, the 8 write wait cycles CL corresponding to 01 correspond to the same write execution signal WR_PER; when the Y-bit binary code OP<6:5> is 10, the 6 write wait cycles CL corresponding to 10 correspond to the same write execution signal WR_PER.

[0052] It can be understood that the 22 X-bit binary codes OP<6:2> with different values ​​correspond one-to-one to the 22 write wait cycles CL, and the 22 write wait cycles CL are divided into three groups according to the clock cycle lengths of the 22 write wait cycles CL. The three groups of write wait cycles CL correspond one-to-one to the three Y-bit binary codes OP<6:5> with different values, respectively, and the maximum clock cycle length of the multiple write wait cycles CL in each group is less than the clock cycle length of the write execution signal WR_PER corresponding to the Y-bit binary codes OP<6:5> in the group at a continuous valid level, that is, the maximum value of the write wait cycle CL corresponding to the values ​​of the multiple Y-bit binary codes OP<6:5> corresponding to the same preset value is less than the preset value, so as to ensure that the write command corresponding to each write wait cycle CL in the multiple write wait cycles CL in each group can be executed normally, and it is helpful to reduce the difference between the clock cycle length of the write wait cycle CL and the clock cycle length of the write execution signal WR_PER at a continuous valid level, so as to avoid the dynamic power consumption generated by the continuous switching of redundant clock cycles, thereby helping to reduce the power consumption of the circuit.

[0053] also, Figure 3The example of “8 write wait cycles CL with values ​​of 22, 24, 26…36 correspond to one write execution signal WR_PER, and the cycle length of the clock cycle length of the write execution signal WR_PER continuously at the valid level is 48 times the clock cycle length of the first clock signal CLK1; 8 write wait cycles CL with values ​​of 38, 40, 42…52 correspond to one write execution signal WR_PER, and the cycle length of the clock cycle length of the write execution signal WR_PER continuously at the valid level is 64 times the clock cycle length of the first clock signal CLK1; 6 write wait cycles CL with values ​​of 54, 56, 58…64 correspond to one write execution signal WR_PER, and the cycle length of the clock cycle length of the write execution signal WR_PER continuously at the valid level is 80 times the clock cycle length of the first clock signal CLK1” is used for explanation. In practical applications, the number of groups into which the 22 write wait cycles CL are divided, and the length of the clock cycle of the write execution signal WR_PER corresponding to the write wait cycles CL in different groups at a continuous valid level can be adjusted according to actual needs.

[0054] For ease of description, the following Figure 3 The embodiments shown are described in detail as examples.

[0055] In some embodiments, reference Figure 5 The clock counting circuit 102 may include: a frequency dividing circuit 122, configured to receive a first clock signal CLK1, and generate a second clock signal CLK2 based on the first clock signal CLK1, wherein the clock cycle length of the second clock signal CLK2 is twice the clock cycle length of the first clock signal CLK1; a counter 132, configured to receive the second clock signal CLK2 and a write execution signal WR_PER, and when the write execution signal WR_PER is at an effective level, based on the second clock signal CLK2 and the write execution signal WR_PER, output a clock cycle counting signal 112 after counting a preset value.

[0056] In some embodiments, reference Figure 6 The counter 132 includes: a fifth NAND gate circuit 142, configured to receive the second clock signal CLK2 and the write execution signal WR_PER, and when the write execution signal WR_PER is at a valid level, generate a third clock signal CLK3 based on the second clock signal CLK2 and the write execution signal WR_PER; a counting circuit 152, configured to receive the third clock signal CLK3, and generate a clock cycle count signal 112 based on the third clock signal CLK3.

[0057] It can be understood that when the write execution signal WR_PER is at a valid level, i.e., logic level 1, the fifth NAND gate circuit 142 generates a third clock cycle signal CLK3 representing a logic level 1 based on the second clock signal CLK2 representing a logic level 0, and generates a third clock cycle signal CLK3 representing a logic level 0 based on the second clock signal CLK2 representing a logic level 1, i.e., the third clock cycle signal CLK3 and the second clock signal CLK2 are differential signals.

[0058] It should be noted that the counting circuit 152 and the clock cycle counting signal 112 will be described in detail later.

[0059] In some embodiments, reference Figures 6 to 10 , the clock cycle counting signal 112 may include a first counting signal DIV_16 , a second counting signal DIV_32 , and a third counting signal DIV_64 .

[0060] refer to Figure 7 The duration setting circuit 103 may include: a configuration information processing circuit 113, configured to receive configuration information OP (reference Figure 2 ), and generates a first control signal Control1, a second control signal Control2 and a third control signal Control3 based on the configuration information OP; the first NAND gate circuit 123 is configured to receive the first counting signal DIV_16, the second counting signal DIV_32 and the first control signal Control1, and generate the first signal Signal1; the second NAND gate circuit 133 is configured to receive the second counting signal DIV_32, the third counting signal DIV_64 and the second control signal Control2, and generate the second signal Signal2; the third NAND gate circuit 143 is configured to receive the third counting signal DIV_64 and the third control signal Control3, and generate the third signal Signal3; the fourth NAND gate circuit 153 is configured to receive the first signal Signal1, the second signal Signal2 and the third signal Signal3, and generate the fourth signal Signal4; the first trigger 163 is configured to receive the fourth signal Signal4 and the first clock signal CLK1, and generate the intermediate signal Time Control.

[0061] Figure 7 In the example, the configuration information OP received by the configuration information processing circuit 113 is a Y-bit binary code OP<6:5>, and the configuration information processing circuit 113 has two input terminals, one of which receives the fifth bit OP in the configuration information OP. <6> The other input terminal receives the 4th bit OP in a configuration information OP <5> .

[0062] In some embodiments, the clock cycle length of the first counting signal DIV_16 is 16 times the clock cycle length of the first clock signal CLK1, the clock cycle length of the second counting signal DIV_32 is 32 times the clock cycle length of the first clock signal CLK1, and the clock cycle length of the third counting signal DIV_64 is 48 times the clock cycle length of the first clock signal CLK1.

[0063] In some embodiments, reference Figure 8 The write execution signal generating circuit 104 may include: a first NOT gate circuit 114, configured to receive a write command WR_CMD, and output a first input signal WR_PRE_MASTER based on the write command WR_CMD; a second NOT gate circuit 124, configured to receive an intermediate signal Time Control, and output a second input signal WR_PRE_SLAVE based on the intermediate signal TimeControl; an SR latch 134, configured to receive a first input signal WR_PRE_MASTER and a second input signal WR_PRE_SLAVE, and output a write execution signal WR_PER based on the first input signal WR_PRE_MASTER and the second input signal WR_PRE_SLAVE.

[0064] In some embodiments, reference Fig. 9 The clock counting circuit 102 may also have a first reset terminal 162, which is used to receive a first reset signal SETa; the clock counting circuit 102 may also be configured to receive the first reset signal SETa and be reset based on the valid level of the first reset signal SETa, when the first reset signal SETa is at a valid level, the write execution signal WR_PER is at an invalid level.

[0065] It can be understood that when the clock counting circuit 102 is performing counting, the write execution signal WR_PER is at a valid level and the first reset signal SETa is at an invalid level. After the clock counting circuit 102 completes a counting operation, the first reset signal SETa is set to a valid level and the write execution signal WR_PER is at an invalid level, so that the values ​​of each port in the clock counting circuit 102 are at the initial value, which facilitates the clock counting circuit 102 to perform the next counting operation.

[0066] In other embodiments, reference Fig.10The clock counting circuit 102 may further include: a third NOT gate circuit 172, configured to receive the second reset signal SETb, and output the first reset signal SETa based on the second reset signal SETb, the output end of the third NOT gate circuit 172 is the first reset end 162; the clock counting circuit 102 may further be configured to receive the second reset signal SETb, and be reset based on the valid level of the second reset signal SETb, when the first reset signal SETa is at the valid level, the write execution signal WR_PER is at the invalid level.

[0067] In some embodiments, reference Figure 8 The write execution signal generating circuit 104 may further have a second reset terminal 144, and the second reset terminal 144 is used to receive the second reset signal SETb; the write execution signal generating circuit 104 may further be configured to receive the second reset signal SETb and be reset based on the effective level of the second reset signal SETb; the first reset signal SETa and the second reset signal SETb are differential signals.

[0068] It can be understood that when the write execution signal generating circuit 104 generates the write execution signal WR_PER, the second reset signal SETb is at an invalid level. After the write execution signal generating circuit 104 completes the output of the write execution signal WR_PER, the second reset signal SETb is set to a valid level, so that the values ​​of the various ports in the write execution signal generating circuit 104 are at the initial values, which facilitates the write execution signal generating circuit 104 to output the next write execution signal WR_PER.

[0069] In some embodiments, reference Fig. 9 or Fig.10 The frequency dividing circuit 122 includes a second trigger 105, a second input terminal C of the second trigger 105 receives the first clock signal CLK1, a first input terminal D of the second trigger 105 is coupled to a second output terminal QN, and a first output terminal Q of the second trigger 105 outputs a second clock signal CLK2, wherein a signal output by the second output terminal QN of the second trigger 105 is a differential signal with the second clock signal CLK2.

[0070] In some embodiments, continue to refer to Fig. 9 or Fig.10, the counting circuit 152 includes: a third flip-flop 115, a fourth flip-flop 125, a fifth flip-flop 135, a sixth flip-flop 145 and a seventh flip-flop 155. The second input terminals C of the third flip-flop 115, the fourth flip-flop 125, the fifth flip-flop 135, the sixth flip-flop 145 and the seventh flip-flop 155 all receive the third clock signal CLK3, the first input terminal D of the third flip-flop 115 is coupled to the second output terminal QN, the second output terminals QN of the fourth flip-flop 125, the fifth flip-flop 135, the sixth flip-flop 145 and the seventh flip-flop 155 are all grounded, and the second input terminals C of the third flip-flop 115, the fourth flip-flop 125, the fifth flip-flop 135, the sixth flip-flop 145 and the seventh flip-flop 155 all receive the third clock signal CLK3.

[0071] Continue to refer Fig. 9 or Fig.10 , the first output terminal Q of the third flip-flop 115 outputs the first frequency-divided signal DIV_4, the first output terminal Q of the fourth flip-flop 125 outputs the second frequency-divided signal DIV_8, the first output terminal Q of the fifth flip-flop 135 outputs the first counting signal DIV_16, the first output terminal Q of the sixth flip-flop 145 outputs the second counting signal DIV_32, and the first output terminal Q of the seventh flip-flop 155 outputs the third counting signal DIV_64. Among them, the clock cycle length of the first frequency-divided signal DIV_4 is 4 times the clock cycle length of the first clock signal CLK1, and the clock cycle length of the second frequency-divided signal DIV_8 is 8 times the clock cycle length of the first clock signal CLK1.

[0072] Continue to refer Fig. 9 or Fig.10 The counting circuit 152 also includes: a first XOR gate circuit 107, one input terminal of the first XOR gate circuit 107 is coupled to the first output terminal Q of the third trigger 115, the other input terminal is coupled to the first output terminal Q of the fourth trigger 125, and the output terminal is coupled to the first input terminal D of the fourth trigger 125.

[0073] A sixth NAND gate circuit 165, a fourth NOT gate circuit 106 and a second XOR gate circuit 117, wherein one input terminal of the sixth NAND gate circuit 165 is coupled to the second output terminal QN of the third trigger 115, the other input terminal is coupled to the first output terminal Q of the fourth trigger 125, and the output terminal is coupled to the input terminal of the fourth NOT gate circuit 106; one input terminal of the second XOR gate circuit 117 is coupled to the first output terminal Q of the fifth trigger 135, the other input terminal is coupled to the output terminal of the fourth NOT gate circuit 106, and the output terminal is coupled to the first input terminal D of the fifth trigger 135.

[0074] A seventh NAND gate circuit 175, a fifth NAND gate circuit 116 and a third XOR gate circuit 127, wherein one input terminal of the seventh NAND gate circuit 175 is coupled to the output terminal of the fourth NAND gate circuit 106, the other input terminal is coupled to the first output terminal Q of the fifth trigger 135, and the output terminal is coupled to the input terminal of the fifth NAND gate circuit 116; one input terminal of the third XOR gate circuit 127 is coupled to the first output terminal Q of the sixth trigger 145, the other input terminal is coupled to the output terminal of the fifth NAND gate circuit 116, and the output terminal is coupled to the first input terminal D of the sixth trigger 145.

[0075] An eighth NAND gate circuit 185, a sixth NAND gate circuit 126 and a fourth XOR gate circuit 137, wherein one input terminal of the eighth NAND gate circuit 185 is coupled to the output terminal of the fifth NAND gate circuit 116, the other input terminal is coupled to the first output terminal Q of the sixth trigger 145, and the output terminal is coupled to the input terminal of the sixth NAND gate circuit 126; one input terminal of the fourth XOR gate circuit 137 is coupled to the first output terminal Q of the seventh trigger 155, the other input terminal is coupled to the output terminal of the sixth NAND gate circuit 126, and the output terminal is coupled to the first input terminal D of the seventh trigger 155.

[0076] Continue to refer Fig. 9 or Fig.10 The reset terminals SET of the second flip-flop 105 , the third flip-flop 115 , the fourth flip-flop 125 , the fifth flip-flop 135 , the sixth flip-flop 145 and the seventh flip-flop 155 all receive the first reset signal SETa.

[0077] It can be understood that the clock counting circuit 102 is used to count the cycles of the clock signal CLK, and outputs a clock cycle counting signal 112 after counting a preset value, wherein the clock cycle counting signal 112 includes a first counting signal DIV_16, a second counting signal DIV_32 and a third counting signal DIV_64, that is, after counting the preset value, the clock counting circuit 102 will output the first counting signal DIV_16, the second counting signal DIV_32 and the third counting signal DIV_64 respectively, and then, the duration setting circuit 103 performs different logical operations on the first counting signal DIV_16, the second counting signal DIV_32 and the third counting signal DIV_64 based on the configuration information OP with different values, so as to output different intermediate signals TimeControl, and different intermediate signals Time Control pass through different preset clock cycle lengths.

[0078] The following combination Figures 7 to 9 as well as Figures 11 to 13 , the working principle of the write command execution duration control circuit 101 is described in detail.

[0079] Combination Figures 7 to 9as well as Fig.11 , if the 5th OP in the configuration information OP <6> and OP No. 4 <5> Both represent logic level 0. At this time, the first control signal Control1 represents logic level 1, and the second control signal Control2 and the third control signal Control3 both represent logic level 0. Then, the first NAND gate circuit 123 outputs the first signal Signal1 whose level changes periodically based on the first counting signal DIV_16 and the second counting signal DIV_32 whose level changes periodically, the second NAND gate circuit 133 outputs the second signal Signal2 representing logic level 1, the third NAND gate circuit 143 outputs the third signal Signal3 representing logic level 1, and the fourth NAND gate circuit 153 outputs the fourth signal Signal4 whose level changes periodically based on the first signal Signal1 whose level changes periodically. The subsequent first trigger 163 generates an intermediate signal Time Control that produces a rising edge after 48 clock cycles of the first clock signal CLK1 based on the fourth signal Signal4 affected by the first counting signal DIV_16 and the second counting signal DIV_32 and the first clock signal CLK1. At this time, the second input signal WR_PRE_SLAVE produces a falling edge after 48 clock cycles of the first clock signal CLK1. Then, the write execution signal generating circuit 104 generates a write execution signal WR_PER with a clock cycle length of a continuous valid level of 48 clock cycles of the first clock signal CLK1 based on the first input signal WR_PRE_MASTER and the second input signal WR_PRE_SLAVE.

[0080] It can be understood that the duration setting circuit 103 and the write execution signal generating circuit 104 select both the first counting signal DIV_16 and the second counting signal DIV_32 based on the Y-bit binary code OP<6:5> which is 00 at this time, and control the clock cycle length of the write execution signal WR_PER to maintain a valid level based on the sum of the clock cycle lengths of the first counting signal DIV_16 and the second counting signal DIV_32.

[0081] Combination Figures 7 to 9 as well as Fig.12, if the 5th OP in the configuration information OP <6> Indicates logic level 0, bit 4 OP in configuration information OP <5> Representing logic level 1, at this time, the first control signal Control1 and the second control signal Control2 both represent logic level 0, and the third control signal Control3 represents logic level 1, then the third NAND gate circuit 143 outputs the third signal Signal3 with a level periodic change based on the third counting signal DIV_64 with a level periodic change, the first NAND gate circuit 123 outputs the first signal Signal1 representing logic level 1, the second NAND gate circuit 133 outputs the second signal Signal2 representing logic level 1, and the fourth NAND gate circuit 153 outputs the fourth signal Signal4 with a level periodic change based on the third signal Signal3 with a level periodic change. The subsequent first trigger 163 generates an intermediate signal Time Control that produces a rising edge after 64 clock cycles of the first clock signal CLK1 based on the fourth signal Signal4 affected by the third counting signal DIV_64 and the first clock signal CLK1. At this time, the second input signal WR_PRE_SLAVE produces a falling edge after 64 clock cycles of the first clock signal CLK1. Then, the write execution signal generating circuit 104 generates a write execution signal WR_PER with a clock cycle length of a continuous valid level of 64 clock cycles of the first clock signal CLK1 based on the first input signal WR_PRE_MASTER and the second input signal WR_PRE_SLAVE.

[0082] It can be understood that the duration setting circuit 103 and the write execution signal generating circuit 104 select the third counting signal DIV_64 based on the Y-bit binary code OP<6:5> which is 01 at this time, and control the clock cycle length of the write execution signal WR_PER to maintain a valid level based on the clock cycle length of the third counting signal DIV_64.

[0083] Combination Figures 7 to 9 as well as Fig.13, if the 5th OP in the configuration information OP <6> Indicates logic level 1, bit 4 OP in configuration information OP <5> Representing logic level 0, at this time, the first control signal Control1 and the third control signal Control3 both represent logic level 0, and the second control signal Control2 represents logic level 1, then the second NAND gate circuit 133 outputs the second signal Signal2 with periodic level changes based on the first counting signal DIV_16 and the third counting signal DIV_64 with periodic level changes, the first NAND gate circuit 123 outputs the first signal Signal1 representing logic level 1, the third NAND gate circuit 143 outputs the third signal Signal3 representing logic level 1, and the fourth NAND gate circuit 153 outputs the fourth signal Signal4 with periodic level changes based on the second signal Signal2 with periodic level changes. The subsequent first trigger 163 generates an intermediate signal Time Control that produces a rising edge after 80 clock cycles of the first clock signal CLK1 based on the fourth signal Signal4 affected by the first counting signal DIV_16 and the third counting signal DIV_64 and the first clock signal CLK1. At this time, the second input signal WR_PRE_SLAVE produces a falling edge after 80 clock cycles of the first clock signal CLK1. Then, the write execution signal generating circuit 104 generates a write execution signal WR_PER with a clock cycle length of a continuous valid level of 80 clock cycles of the first clock signal CLK1 based on the first input signal WR_PRE_MASTER and the second input signal WR_PRE_SLAVE.

[0084] It can be understood that the duration setting circuit 103 and the write execution signal generating circuit 104 select both the first counting signal DIV_16 and the third counting signal DIV_64 based on the Y-bit binary code OP<6:5> which is 10 at this time, and control the clock cycle length of the write execution signal WR_PER to maintain a valid level based on the sum of the clock cycle lengths of the first counting signal DIV_16 and the third counting signal DIV_64.

[0085] In summary, N configuration information OP with different values ​​correspond to M write execution signals WR_PER, and the clock cycle lengths of the M write execution signals WR_PER at the continuous effective level are different from each other, that is, configuration information OP with different values ​​can correspond to write execution signals WR_PER with different clock cycle lengths at the continuous effective level. For example, for some configuration information OP with smaller values, the write command execution duration control circuit 101 can generate a write execution signal WR_PER with a short clock cycle length at the continuous effective level based on the configuration information OP, so as to avoid the clock cycle length actually required for executing the write operation being much shorter than the clock cycle length of the continuous effective level of the write execution signal WR_PER. This is beneficial to avoid the dynamic power consumption caused by the constant switching of redundant clock cycles, while ensuring that the clock cycle length actually required for executing the write operation is shorter than the clock cycle length of the continuous effective level of the write execution signal WR_PER, thereby reducing the power consumption of the circuit.

[0086] Another embodiment of the present disclosure further provides a memory, including a write execution signal control circuit as provided in an embodiment of the present disclosure. It should be noted that the parts that are the same or corresponding to the above-mentioned embodiments are not repeated here. In this way, on the basis that the write execution signal control circuit is conducive to reducing the power consumption of the circuit, it is also conducive to reducing the power consumption of the memory.

[0087] In some embodiments, the memory may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0088] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A write execution signal control circuit, characterized in that: include: A mode register is configured to output N configuration information with different values; The write command execution duration control circuit is configured to receive a write command and generate M write execution signals based on N configuration information with different values; wherein the clock cycle lengths of the M write execution signals at a continuous valid level are different from each other, and N≥M>1.

2. The write execution signal control circuit according to claim 1, characterized in that: The write execution signal control circuit includes a clock counting circuit, a time length setting circuit and a write execution signal generating circuit; The clock counting circuit is used to count the clock signal cycle and output a clock cycle counting signal after counting a preset value; The duration setting circuit is used to receive the configuration information and the clock cycle counting signal, and generate an intermediate signal after a preset clock cycle length based on the value of the configuration information, wherein the preset clock cycle length corresponds to the value of the configuration information; The write execution signal generating circuit is used for receiving the write command and the intermediate signal, and generating the write execution signal based on the write command and the intermediate signal.

3. The write execution signal control circuit according to claim 2, characterized in that: The configuration information is a binary code with X bits, and the duration setting circuit is used to receive a Y-bit binary code in the X-bit binary code, wherein X≥Y≥1, and different values ​​of the configuration information correspond to write waiting cycles with different configuration clock cycle lengths.

4. The write execution signal control circuit according to claim 3, characterized in that: The binary code of the Y bit has M different values, and the clock counting circuit is configured to set the preset values ​​of M different values ​​corresponding to the M different values ​​of the binary code of the Y bit; wherein the maximum value of the write waiting cycle corresponding to the multiple values ​​of the binary code of the Y bit corresponding to the same preset value is less than the preset value.

5. The write execution signal control circuit according to claim 4, characterized in that: The configuration information is a binary code with 5 bits, and the duration setting circuit is used to receive the values ​​of the 5th and 4th bits in the configuration information.

6. The write execution signal control circuit according to any one of claims 2 to 5, characterized in that: The clock counting circuit comprises: The frequency dividing circuit is configured to receive a first clock signal and generate a second clock signal based on the first clock signal. The clock cycle length of the second clock signal is twice the clock cycle length of the first clock signal; The counter is configured to receive the second clock signal and the write execution signal, and when the write execution signal is at an effective level, output the clock cycle count signal after counting the preset value based on the second clock signal and the write execution signal.

7. The write execution signal control circuit according to any one of claims 2 to 5, characterized in that: The clock cycle counting signal includes a first counting signal, a second counting signal and a third counting signal; the duration setting circuit includes: a configuration information processing circuit configured to receive the configuration information and generate a first control signal, a second control signal and a third control signal based on the configuration information; A first NAND gate circuit is configured to receive the first counting signal, the second counting signal and the first control signal, and generate a first signal; A second NAND gate circuit is configured to receive the second counting signal, the third counting signal and the second control signal, and generate a second signal; A third NAND gate circuit is configured to receive the third counting signal and the third control signal and generate a third signal; a fourth NAND gate circuit, configured to receive the first signal, the second signal and the third signal, and generate a fourth signal; The first flip-flop is configured to receive the fourth signal and the first clock signal and generate the intermediate signal.

8. The write execution signal control circuit according to claim 7, characterized in that: The clock cycle length of the first counting signal is 16 times the clock cycle length of the first clock signal, the clock cycle length of the second counting signal is 32 times the clock cycle length of the first clock signal, and the clock cycle length of the third counting signal is 48 times the clock cycle length of the first clock signal.

9. The write execution signal control circuit according to any one of claims 2 to 5, characterized in that: The write execution signal generating circuit comprises: A first NOT gate circuit is configured to receive the write command and output a first input signal based on the write command; The second NOT gate circuit is configured to receive the intermediate signal and output a second input signal based on the intermediate signal; the SR latch is configured to receive the first input signal and the second input signal and output the write execution signal based on the first input signal and the second input signal.

10. The write execution signal control circuit according to any one of claims 1 to 5, characterized in that: The clock counting circuit also has a first reset terminal, and the first reset terminal is used to receive a first reset signal; The clock counting circuit is further configured to receive the first reset signal and be reset based on an active level of the first reset signal, wherein when the first reset signal is at an active level, the write execution signal is at an inactive level.

11. The write execution signal control circuit according to claim 10, wherein: The write execution signal generating circuit further has a second reset terminal, and the second reset terminal is used to receive a second reset signal; The write execution signal generating circuit is further configured to receive the second reset signal and be reset based on the valid level of the second reset signal; The first reset signal and the second reset signal are differential signals.

12. A memory, characterized in that: include: A write execution signal control circuit according to any one of claims 1 to 11.

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