Small area common voltage multiple write non-volatile memory array

Abstract

The invention discloses a small-area common-voltage multi-write non-volatile memory array, which belongs to the field of memory arrays and comprises a plurality of word lines, a plurality of selection lines, a plurality of common-voltage lines and a plurality of memory sub-arrays. The word lines comprise a first word line and a second word line, and the selection lines comprise a first selection line. The common voltage lines are directly coupled together and include a first common voltage line and a second common voltage line. The first word line and the second word line are respectively close to the first common voltage line and the second common voltage line. Each memory sub-array is coupled with two word lines, one selection line and two common voltage lines, and comprises a first non-volatile memory unit cell and a second non-volatile memory unit cell. The first non-volatile memory unit cell is coupled to the first word line, the first selection line and the first common voltage line, and the second non-volatile memory unit cell is coupled to the second word line, the first selection line and the second common voltage line. According to the invention, the number and the overall area of decoders are reduced.

Description

Technical Field

[0001] The present invention belongs to the field of memory arrays, and in particular to a small-area common voltage multiple-write non-volatile memory array. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application-specific integrated circuits (ASICs). In today's rapidly developing computer information technology landscape, Electrically Erasable Programmable Read-Only Memory (EEPROM) is widely used in electronic products because it offers non-volatile memory capabilities that can be electrically programmed and erased, and its data persists even after power is turned off.

[0003] Non-volatile memory is programmable, storing charge to change the gate voltage of the memory's transistors, or not storing charge to retain the original gate voltage of the memory's transistors. The erase operation removes all charge stored in the non-volatile memory, returning the gate voltage of all non-volatile memory transistors to the original state. During programming, the internal switching elements of the non-volatile memory are either turned on or off. To program the non-volatile memory array, a specific voltage and current are applied to open or close the corresponding switching elements. These programming signals must be transmitted to the correct locations in the non-volatile memory array through a decoder. However, the decoder increases the overall area of ​​the non-volatile memory array.

[0004] Therefore, the present invention addresses the above-mentioned difficulties and proposes a small-area common voltage multiple-write non-volatile memory array to solve the problems in the prior art. Summary of the Invention

[0005] The present invention provides a small-area common voltage multiple-write non-volatile memory array, which can reduce the number of decoders and the overall area.

[0006] In one embodiment of the present invention, a small-area common voltage multiple write non-volatile memory array is provided, comprising a plurality of parallel word lines, a plurality of parallel select lines, a plurality of parallel common voltage lines, and a plurality of memory sub-arrays. All word lines include a first word line and a second word line, all select lines are perpendicular to all word lines, and all select lines include a first select line. All common voltage lines are perpendicular to all select lines, and all common voltage lines are directly coupled together, and all common voltage lines include a first common voltage line and a second common voltage line. The first word line and the second word line are respectively adjacent to the first common voltage line and the second common voltage line. Each memory sub-array is coupled to two word lines, one select line, and two common voltage lines. Each memory sub-array includes a first non-volatile memory cell and a second non-volatile memory cell. The first non-volatile memory cell is coupled to the first word line, the first select line, and the first common voltage line, while the second non-volatile memory cell is coupled to the second word line, the first select line, and the second common voltage line.

[0007] In one embodiment of the present invention, the first non-volatile memory unit cell and the second non-volatile memory unit cell are symmetrically arranged.

[0008] In one embodiment of the present invention, a first non-volatile memory cell and a second non-volatile memory cell are disposed in a P-type semiconductor region. The first non-volatile memory cell includes a first gate dielectric block, a first common voltage gate, a first N-type doped region, a second N-type doped region, and a third N-type doped region. The first gate dielectric block includes a high-k dielectric material, and the first common voltage gate includes a high-k dielectric metal. The first gate dielectric block is disposed on the P-type semiconductor region and between a first word line and the P-type semiconductor region. The first common voltage gate is disposed on the first gate dielectric block and coupled to the first common voltage line. The first common voltage gate is closer to the first common voltage line than the first word line. The first N-type doped region, the second N-type doped region, and the third N-type doped region are disposed in the P-type semiconductor region. The first N-type doping region and the second N-type doping region are arranged on different sides of the P-type semiconductor region directly below the first word line, the second N-type doping region and the third N-type doping region are arranged on different sides of the P-type semiconductor region directly below the first common voltage gate, and the first N-type doping region is coupled to the first selection line.

[0009] In one embodiment of the present invention, the second non-volatile memory cell includes a second gate dielectric block, a second common voltage gate, a fourth N-type doped region, a fifth N-type doped region, and a sixth N-type doped region. The second gate dielectric block includes a high-k dielectric material, and the second common voltage gate includes a high-k dielectric metal. The second gate dielectric block is disposed on a P-type semiconductor region and between a second wordline and the P-type semiconductor region. The second common voltage gate is disposed on the second gate dielectric block and coupled to the second common voltage line. The second common voltage gate is closer to the second common voltage line than the second wordline. The fourth N-type doped region, the fifth N-type doped region, and the sixth N-type doped region are disposed in the P-type semiconductor region. The fourth N-type doped region and the fifth N-type doped region are disposed on opposite sides of the P-type semiconductor region directly below the second wordline, and the fifth N-type doped region and the sixth N-type doped region are disposed on opposite sides of the P-type semiconductor region directly below the second common voltage gate. The fourth N-type doped region is coupled to a first select line.

[0010] In one embodiment of the present invention, when the first non-volatile memory cell is selected for forming, a medium voltage is applied to the first common voltage line, a medium voltage or a low voltage is applied to the first word line, and a ground voltage is applied to the first select line. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

[0011] In one embodiment of the present invention, when the first non-volatile memory cell is not selected for formation, a medium voltage is applied to the first common voltage line, a ground voltage is applied to the first word line, and a bias voltage is applied to the first select line or is electrically floating, wherein the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0012] In one embodiment of the present invention, when the first non-volatile memory cell is selected for a set operation, half of the medium voltage is applied to the first common voltage line, the medium voltage or the low voltage is applied to the first word line, and the ground voltage is applied to the first select line. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

[0013] In one embodiment of the present invention, when the first non-volatile memory cell is not selected for a set operation, half of the middle voltage is applied to the first common voltage line, the first word line is applied to the ground voltage, and the first select line is biased or electrically floating, wherein the middle voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0014] In one embodiment of the present invention, when the first non-volatile memory cell is selected for a reset operation, a ground voltage is applied to the first common voltage line, a medium voltage or a low voltage is applied to the first word line, and half of the medium voltage is applied to the first select line, where the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

[0015] In one embodiment of the present invention, when the first non-volatile memory cell is not selected for the reset operation, the first common voltage line, the first word line, and the first selection line are applied with the ground voltage.

[0016] In one embodiment of the present invention, when the first non-volatile memory cell is selected for a read operation, a ground voltage is applied to the first common voltage line, a medium voltage or a low voltage is applied to the first word line, and a bias voltage is applied to the first select line, wherein the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0017] In one embodiment of the present invention, when the first non-volatile memory cell is not selected for a read operation, the first common voltage line, the first word line, and the first selection line are applied with a ground voltage.

[0018] In one embodiment of the present invention, when the second non-volatile memory cell is selected for forming, a medium voltage is applied to the second common voltage line, a medium voltage or a low voltage is applied to the second word line, and a ground voltage is applied to the first select line. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

[0019] In one embodiment of the present invention, when the second non-volatile memory cell is not selected for formation, a medium voltage is applied to the second common voltage line, a ground voltage is applied to the second word line, and a bias voltage is applied to the first select line or is electrically floating, wherein the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0020] In one embodiment of the present invention, when the second non-volatile memory cell is selected for a set operation, half of the middle voltage is applied to the second common voltage line, the middle voltage or the low voltage is applied to the second word line, and the first select line is applied to the ground voltage, wherein the middle voltage is greater than the low voltage, and both the middle voltage and the low voltage are greater than the ground voltage.

[0021] In one embodiment of the present invention, when the second non-volatile memory cell is not selected for a set operation, half of the middle voltage is applied to the second common voltage line, the second word line is applied to the ground voltage, and the first select line is biased or electrically floating, wherein the middle voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0022] In one embodiment of the present invention, when the second non-volatile memory cell is selected for a reset operation, a ground voltage is applied to the second common voltage line, a medium voltage or a low voltage is applied to the second word line, and half of the medium voltage is applied to the first select line, where the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

[0023] In one embodiment of the present invention, when the second non-volatile memory cell is not selected for the reset operation, the second common voltage line, the second word line, and the first selection line are applied with the ground voltage.

[0024] In one embodiment of the present invention, when the second non-volatile memory cell is selected for a read operation, a ground voltage is applied to the second common voltage line, a medium voltage or a low voltage is applied to the second word line, and a bias voltage is applied to the first select line, wherein the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0025] In one embodiment of the present invention, when the second non-volatile memory cell is not selected for the read operation, the second common voltage line, the second word line, and the first selection line are applied with the ground voltage.

[0026] In one embodiment of the present invention, the P-type semiconductor region is a P-type semiconductor substrate.

[0027] In one embodiment of the present invention, the P-type semiconductor region is a P-type doped well region, and the doped well region is disposed in an N-type semiconductor substrate.

[0028] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0029] Based on the above, a small-area common voltage is used for multiple writing into a non-volatile memory array by directly coupling common voltage lines together, thereby reducing the number of decoders and the overall area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 FIG. 1 is a schematic diagram of a circuit layout of a small-area common-voltage multiple-write non-volatile memory array according to an embodiment of the present invention.

[0032] Figure 2 FIG. 1 is a schematic diagram of a circuit layout of a memory sub-array according to an embodiment of the present invention.

[0033] Figure 3 FIG. 4 is a cross-sectional view of the structure of an embodiment of the first non-volatile memory cell of the present invention.

[0034] Figure 4 FIG. 4 is a cross-sectional view of the structure of a second non-volatile memory cell according to an embodiment of the present invention.

[0035] Figure 5 FIG. 4 is a cross-sectional view of the structure of another embodiment of the first non-volatile memory cell of the present invention.

[0036] Figure 6 FIG. 4 is a cross-sectional view of the structure of another embodiment of the second non-volatile memory cell of the present invention.

[0037] Explanation of symbols:

[0038] 1: Small-area common voltage multiple write non-volatile memory array; 10: Memory sub-array; 100: First non-volatile memory cell; 1000: First gate dielectric block; 1001: First common voltage gate; 1002: First N-type doped region; 1003: Second N-type doped region; 1004: Third N-type doped region; 1005: First sidewall spacer; 1006: First N-type lightly doped drain region; 1007: Second sidewall spacer; 1008: Second N-type lightly doped drain region; 101: Second non-volatile memory cell; 1010: Second gate 1011: second common voltage gate; 1012: fourth N-type doped region; 1013: fifth N-type doped region; 1014: sixth N-type doped region; 1015: third sidewall spacer; 1016: third N-type lightly doped drain region; 1017: fourth sidewall spacer; 1018: fourth N-type lightly doped drain region; 2: P-type semiconductor region; 3: N-type semiconductor substrate; 4: first conductive metal block; 5: first conductive via; 6: second conductive via; 7: second conductive metal block; 8: third conductive via; 9: fourth conductive via.

[0039] WL: word line; WL1: first word line; WL2: second word line; SL: select line; SL1: first select line; CVL: common voltage line; CVL1: first common voltage line; CVL2: second common voltage line; L: gate dielectric layer; CH1, CH2, CH3, CH4: channel regions. DETAILED DESCRIPTION

[0040] The embodiments of the present invention are further explained below with reference to the accompanying drawings. Whenever possible, identical reference numerals will be used throughout the drawings and the specification to represent identical or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It should be understood that components not specifically shown in the drawings or described in the specification are generally known to those skilled in the art. Those skilled in the art may make various changes and modifications based on the teachings of this invention.

[0041] Unless otherwise specified, conditional clauses or words such as "can," "could," "might," or "may" are generally intended to indicate that an embodiment of the present invention has features, components, or steps, but may also be interpreted as not being required. In other embodiments, these features, components, or steps may not be required.

[0042] The following description of "one embodiment" or "an embodiment" refers to a specific component, structure, or feature associated with at least one embodiment. Therefore, multiple references to "one embodiment" or "an embodiment" in various places below do not necessarily refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in any suitable manner.

[0043] Certain words are used in the specification and claims to refer to specific components. However, a person with ordinary knowledge in the technical field should understand that the same component may be referred to by different terms. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and claims is an open term and should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first component coupled to a second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal-connected to the second component through other components or connection means.

[0044] The following examples are specifically described, but these examples are intended to be illustrative only. As variations and modifications are readily apparent to those skilled in the art without departing from the spirit and scope of the present invention, the scope of the present invention is intended to be determined by the appended claims. Throughout the specification and claims, unless the context clearly dictates otherwise, the meanings of "a," "an," and "the" include references to "one or at least one" of the elements or components. Furthermore, as used herein, the singular article includes references to plural elements or components unless the context clearly dictates otherwise. Furthermore, as used in this description and throughout the claims that follow, the meaning of "in which" includes references to "in which" and "on which" unless the context clearly dictates otherwise. Terms used throughout the specification and claims generally have their ordinary meanings as used in the art, within the disclosure, and in the specific context, unless otherwise noted. Certain terms used to describe the present invention are discussed below and elsewhere in this specification to provide practitioners with additional guidance regarding the present invention. The examples anywhere in the entire specification, including the use of examples of any term discussed herein, are for illustration only and certainly do not limit the scope and meaning of the invention or any exemplified term. Likewise, the invention is not limited to the various embodiments set forth in this specification.

[0045] In the specification and claims, if a first element is described as being on, above, connected to, bonded to, coupled to, or in contact with a second element, it means that the first element may be directly on, directly connected to, directly bonded to, or directly coupled to the second element, or it may mean that there are other elements between the first and second elements. Conversely, if a first element is described as being directly on, directly connected to, directly bonded to, directly coupled to, or directly in contact with a second element, it means that there are no other elements between the first and second elements.

[0046] In the following description, a small-area common voltage multiple-write non-volatile memory array is provided, which directly couples common voltage lines together to reduce the number of decoders and the overall area.

[0047] Figure 1 FIG. 1 is a schematic diagram of a circuit layout of an embodiment of a small-area common voltage multiple-write non-volatile memory array according to the present invention. Figure 2 FIG. 1 is a schematic diagram of a circuit layout of a memory sub-array according to an embodiment of the present invention. Figure 1 With the Figure 2 The following describes a small-area common voltage multi-write non-volatile memory array 1 of the present invention. The small-area common voltage multi-write non-volatile memory array 1 includes a plurality of parallel word lines WL, a plurality of parallel select lines SL, a plurality of parallel common voltage lines CVL, and a plurality of memory sub-arrays 10. All word lines WL include a first word line WL1 and a second word line WL2. All select lines SL are perpendicular to all word lines WL, and all select lines SL include a first select line SL1. All common voltage lines CVL are perpendicular to all select lines SL, and all common voltage lines CVL are directly coupled together via their ends on the same side. All common voltage lines CVL include a first common voltage line CVL1 and a second common voltage line CVL2. The first word line WL1 and the second word line WL2 are adjacent to the first common voltage line CVL1 and the second common voltage line CVL2, respectively. Each memory sub-array 10 is coupled to two word lines WL, one select line SL, and two common voltage lines CVL. Each memory sub-array 10 includes a first non-volatile memory cell 100 and a second non-volatile memory cell 101. The first non-volatile memory cell 100 is coupled to a first word line WL1, a first select line SL1, and a first common voltage line CVL1. The second non-volatile memory cell 101 is coupled to a second word line WL2, the first select line SL1, and a second common voltage line CVL2. In some embodiments of the present invention, the first non-volatile memory cell 100 and the second non-volatile memory cell 101 are arranged symmetrically.

[0048] Figure 3 FIG1 is a cross-sectional view of the structure of an embodiment of the first non-volatile memory cell of the present invention. Figure 3 and Figure 2 The first non-volatile memory cell 100 is disposed in a P-type semiconductor region 2. For example, the P-type semiconductor region 2 is a doped well region, and the doped well region is disposed in an N-type semiconductor substrate 3. The first non-volatile memory cell 100 includes a first gate dielectric block 1000, a first common voltage gate 1001, a first N-type doped region 1002, a second N-type doped region 1003, and a third N-type doped region 1004. The first gate dielectric block 1000 is Figure 1 A portion of a gate dielectric layer L in the first common voltage gate 1001 and Figure 1 The word lines WL in FIG. 1 are each part of an electrode layer. The electrode layer, the first common voltage gate 1001, and the word lines WL can all be made of a high-k dielectric constant metal, such as, but not limited to, hafnium. The first gate dielectric block 1000 and the gate dielectric layer L can be made of a high-k dielectric constant material, such as, but not limited to, hafnium dioxide. Figure 1 The selection line SL is a portion of a first conductive metal layer. Figure 1 The common voltage line CVL is part of a second conductive metal layer. The electrode layer, the first conductive metal layer, and the second conductive metal layer are arranged from bottom to top. The first gate dielectric block 1000 is disposed on the P-type semiconductor region 2 and is located between the first word line WL1 and the P-type semiconductor region 2. The first common voltage gate 1001 is disposed on the first gate dielectric block 1000 and coupled to the first common voltage line CVL1, wherein the first common voltage gate 1001 is closer to the first common voltage line CVL1 than the first word line WL1. Specifically, the first common voltage gate 1001 overlaps with a first conductive metal block 4, which is part of the first conductive metal layer. The first conductive via 5 is located between the first common voltage gate 1001 and the first conductive metal block 4. The first common voltage gate 1001 is coupled to the first conductive metal block 4 through the first conductive via 5. The first conductive metal block 4 overlaps with the first common voltage line CVL1. The second conductive via 6 is located between the first conductive metal block 4 and the first common voltage line CVL1. The first conductive metal block 4 is coupled to the first common voltage line CVL1 through the second conductive via 6.

[0049] A first N-type doped region 1002, a second N-type doped region 1003, and a third N-type doped region 1004 are disposed in a P-type semiconductor region 2. The first N-type doped region 1002 and the second N-type doped region 1003 are disposed on opposite sides of the P-type semiconductor region 2 directly below the first word line WL1. The second N-type doped region 1003 and the third N-type doped region 1004 are disposed on opposite sides of the P-type semiconductor region 2 directly below the first common voltage gate 1001. The first N-type doped region 1002 is coupled to a first select line SL1. The first select line SL1 is coupled to a first conductive via 5 directly below it. The first conductive via 5 penetrates the gate dielectric layer L, and the first select line SL1 is coupled to an external voltage through the first conductive via 5.

[0050] The P-type semiconductor region 2, the first word line WL1, the first N-type doped region 1002, the second N-type doped region 1003, and the first gate dielectric block 1000 form a first selection MOSFET. Two first sidewall spacers 1005 are disposed on either side of the first word line WL1. These first sidewall spacers 1005 extend to the sidewalls of the first gate dielectric block 1000. Directly beneath these first sidewall spacers 1005 are two first N-type lightly doped drain (LDD) regions 1006. When the first selection MOSFET is turned on, a channel region CH1 is formed between the first N-type lightly doped drain regions 1006.

[0051] The P-type semiconductor region 2, the first common voltage gate 1001, the second N-type doped region 1003, the third N-type doped region 1004, and the first gate dielectric block 1000 form a first MOSFET. Two second sidewall spacers 1007 are located on either side of the first common voltage gate 1001. These second sidewall spacers 1007 extend to the sidewalls of the first gate dielectric block 1000. Directly beneath these second sidewall spacers 1007 are two second N-type lightly doped drain regions 1008. When the first MOSFET is turned on, a channel region CH2 is formed between the second N-type lightly doped drain regions 1008. However, the first common voltage gate 1001 can form parasitic capacitances with the second N-type doped region 1003 and the third N-type doped region 1004, thereby storing data.

[0052] Figure 4 FIG2 is a cross-sectional view of the structure of an embodiment of the second non-volatile memory cell of the present invention. Figure 4 and Figure 2 The second non-volatile memory cell 101 is also disposed in the P-type semiconductor region 2. The second non-volatile memory cell 101 includes a second gate dielectric block 1010, a second common voltage gate 1011, a fourth N-type doping region 1012, a fifth N-type doping region 1013, and a sixth N-type doping region 1014. The second gate dielectric block 1010 is Figure 1 A portion of the gate dielectric layer L in the second common voltage gate 1011 and Figure 1The word lines WL in the diagram are all part of the electrode layer, and the second common voltage gate 1011 can be a high dielectric constant metal, such as but not limited to hafnium. The second gate dielectric block 1010 can be a high dielectric constant material, such as but not limited to hafnium dioxide. The second gate dielectric block 1010 is disposed on the P-type semiconductor region 2 and is located between the second word line WL2 and the P-type semiconductor region 2. The second common voltage gate 1011 is disposed on the second gate dielectric block 1010 and coupled to the second common voltage line CVL2, wherein the second common voltage gate 1011 is closer to the second common voltage line CVL2 than the second word line WL2. Specifically, the second common voltage gate 1011 overlaps with a second conductive metal block 7, and the second conductive metal block 7 is part of the first conductive metal layer. The third conductive through-hole 8 is located between the second common voltage gate 1011 and the second conductive metal block 7. The second common voltage gate 1011 is coupled to the second conductive metal block 7 through the third conductive through-hole 8. The second conductive metal block 7 overlaps with the second common voltage line CVL2. The fourth conductive through-hole 9 is located between the second conductive metal block 7 and the second common voltage line CVL2. The second conductive metal block 7 is coupled to the second common voltage line CVL2 through the fourth conductive through-hole 9.

[0053] The fourth N-type doping region 1012, the fifth N-type doping region 1013, and the sixth N-type doping region 1014 are disposed in the P-type semiconductor region 2. The fourth N-type doping region 1012 and the fifth N-type doping region 1013 are disposed on opposite sides of the P-type semiconductor region 2 directly below the second word line WL2. The fifth N-type doping region 1013 and the sixth N-type doping region 1014 are disposed on opposite sides of the P-type semiconductor region 2 directly below the second common voltage gate 1011. The fourth N-type doping region 1012 is coupled to the first select line SL1.

[0054] The P-type semiconductor region 2, the second word line WL2, the fourth N-type doped region 1012, the fifth N-type doped region 1013, and the second gate dielectric block 1010 form a second selection MOSFET. Two third sidewall spacers 1015 are disposed on either side of the second word line WL2. These two third sidewall spacers 1015 extend to the sidewalls of the second gate dielectric block 1010. Directly beneath each of the two third sidewall spacers 1015 are two third N-type lightly doped drain regions 1016. When the second selection MOSFET is turned on, a channel region CH3 is formed between the third N-type lightly doped drain regions 1016.

[0055] The P-type semiconductor region 2, the second common voltage gate 1011, the fifth N-type doped region 1013, the sixth N-type doped region 1014, and the second gate dielectric block 1010 form a second MOSFET. Two fourth sidewall spacers 1017 are provided on either side of the second common voltage gate 1011. These fourth sidewall spacers 1017 extend to the sidewalls of the second gate dielectric block 1010. Directly beneath these fourth sidewall spacers 1017 are two fourth N-type lightly doped drain regions 1018. When the second MOSFET is turned on, a channel region CH4 is formed between the fourth N-type lightly doped drain regions 1018. However, parasitic capacitance is formed between the second common voltage gate 1011 and the fifth N-type doped region 1013 and the sixth N-type doped region 1014, thereby storing data.

[0056] See also Figure 2 The following describes the operation process of the first non-volatile memory cell 100 and the second non-volatile memory cell 101, which includes a forming action, a setting action, a reset action, and a read action. The forming action is defined as setting the memory cell to a state for storage and operation; the setting action is defined as operating the memory cell to the storage state (1); the reset action is defined as operating the memory cell to the storage state (0); and the read action is defined as reading the storage state of the memory cell.

[0057] When the first non-volatile memory cell 100 is selected for a forming operation, a medium voltage is applied to the first common voltage line CVL1, a medium voltage or a low voltage is applied to the first word line WL1, and a ground voltage is applied to the first select line SL1. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage. When the first non-volatile memory cell 100 is not selected for a forming operation, a medium voltage is applied to the first common voltage line CVL1, a ground voltage is applied to the first word line WL1, and a first bias voltage is applied to the first select line SL1 or is electrically floating. The medium voltage is greater than the first bias voltage, and the first bias voltage is greater than the ground voltage. When the first non-volatile memory cell 100 is selected for a set operation, half of the medium voltage is applied to the first common voltage line CVL1, a medium voltage or a low voltage is applied to the first word line WL1, and a ground voltage is applied to the first select line SL1. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage. When the first non-volatile memory cell 100 is not selected for a set operation, half of the medium voltage is applied to the first common voltage line CVL1, the first word line WL1 is applied to ground, and the first select line SL1 is applied to a first bias voltage or electrically floating, where the medium voltage is greater than the first bias voltage, which is greater than ground. During the formation and set operations of the first non-volatile memory cell 100, the first common voltage line CVL1 is directly coupled to the external voltage without passing through the decoder. The Edge Fowler-Neumann effect applies pressure to the transistor to form a conductive path, resulting in a low-impedance state. When the first non-volatile memory cell 100 is selected for a reset operation, ground is applied to the first common voltage line CVL1, the first word line WL1 is applied to a medium voltage or a low voltage, and half of the medium voltage is applied to the first select line SL1, where the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than ground. When the first non-volatile memory cell 100 is not selected for a reset operation, the first common voltage line CVL1, the first word line WL1, and the first select line SL1 are applied to a ground voltage. When the first non-volatile memory cell 100 is reset, the edge Fuller-Neumann effect stresses the transistor, disconnecting the conduction path and forming a high-impedance state. When the first non-volatile memory cell 100 is selected for a read operation, the first common voltage line CVL1 is applied to a ground voltage, the first word line WL1 is applied to a mid voltage or a low voltage, and the first select line SL1 is applied to a first bias voltage. The mid voltage is greater than the low voltage, and both the mid voltage and the low voltage are greater than the first bias voltage, which is greater than the ground voltage. When the first non-volatile memory cell 100 is not selected for a read operation, the first common voltage line CVL1, the first word line WL1, and the first select line SL1 are applied to a ground voltage. When the first non-volatile memory cell 100 performs a reading operation, the corresponding current can be read through the voltage difference between the two ends of the first non-volatile memory cell 100 .If the first non-volatile memory cell 100 is in a high impedance state, a low current is read. If the first non-volatile memory cell 100 is in a low impedance state, a high current is read.

[0058] Based on the above operation, the common voltage line directly receives the external voltage without passing through the decoder, and is directly coupled to the non-volatile memory cell, so that the non-volatile memory cell performs a forming action or a setting action, thereby reducing the number of decoders and the overall area of ​​the non-volatile memory array that is written multiple times with a small area common voltage. In the above operation, applying a medium voltage or a low voltage to the word line will affect the current size of the component, so it will be adjusted according to different designs and situations. The selection line is biased or electrically floating according to the process characteristics. In addition, the medium voltage is greater than the low voltage, the low voltage is greater than the first bias voltage, and the first bias is greater than the ground voltage. Specifically, the medium voltage is equal to the breakdown voltage of the drain to source of the field effect transistor × 0.5, and the low voltage is equal to the breakdown voltage of the drain to source of the field effect transistor × 0.25.

[0059] When the second non-volatile memory cell 101 is selected for a forming operation, a medium voltage is applied to the second common voltage line CVL2, a medium voltage or a low voltage is applied to the second word line WL2, and a ground voltage is applied to the first select line SL1. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage. When the second non-volatile memory cell 101 is not selected for a forming operation, a medium voltage is applied to the second common voltage line CVL2, a ground voltage is applied to the second word line WL2, and a second bias voltage is applied to the first select line SL1 or is electrically floating. The medium voltage is greater than the second bias voltage, and the second bias voltage is greater than the ground voltage. When the second non-volatile memory cell 101 is selected for a set operation, half the medium voltage is applied to the second common voltage line CVL2, a medium voltage or a low voltage is applied to the second word line WL2, and a ground voltage is applied to the first select line SL1. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage. When the second non-volatile memory cell 101 is not selected for a set operation, half of the medium voltage is applied to the second common voltage line CVL2, the second word line WL2 is applied to ground, and the first select line SL1 is applied to a second bias voltage or electrically floating, wherein the medium voltage is greater than the second bias voltage, which is greater than ground. When the second non-volatile memory cell 101 is forming and setting operations, the second common voltage line CVL2 is directly coupled to the external voltage without passing through the decoder. The Edge Fowler-Neumann effect applies pressure to the transistor to form a conductive path, resulting in a low-impedance state. When the second non-volatile memory cell 101 is selected for a reset operation, ground is applied to the second common voltage line CVL2, the second word line WL2 is applied to a medium voltage or a low voltage, and half of the medium voltage is applied to the first select line SL1, wherein the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than ground. When the second non-volatile memory cell 101 is not selected for a reset operation, the second common voltage line CVL2, the second word line WL2, and the first select line SL1 are applied to a ground voltage. When the second non-volatile memory cell 101 is reset, the edge Fuller-Neumann effect applies pressure to the transistor, disconnecting the conduction path and forming a high-impedance state. When the second non-volatile memory cell 101 is selected for a read operation, the second common voltage line CVL2 is applied to a ground voltage, the second word line WL2 is applied to a medium voltage or a low voltage, and the first select line SL1 is applied to a second bias voltage. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the second bias voltage, which is greater than the ground voltage. When the second non-volatile memory cell 101 is not selected for a read operation, the second common voltage line CVL2, the second word line WL2, and the first select line SL1 are applied to a ground voltage. When the second non-volatile memory cell 101 performs a reading operation, the corresponding current can be read through the voltage difference between the two ends of the second non-volatile memory cell 101 .If the second non-volatile memory cell 101 is in a high impedance state, a low current is read. If the second non-volatile memory cell 101 is in a low impedance state, a high current is read.

[0060] Based on the above operation, the common voltage line directly receives the external voltage without passing through the decoder, and is directly coupled to the non-volatile memory cell, so that the non-volatile memory cell performs a forming action or a setting action, thereby reducing the number of decoders and the overall area of ​​the non-volatile memory array that is written multiple times with a small area common voltage. In the above operation, applying a medium voltage or a low voltage to the word line will affect the current size of the component, so it will be adjusted according to different designs and situations. The selection line is biased or electrically floating according to the process characteristics. In addition, the medium voltage is greater than the low voltage, the low voltage is greater than the second bias voltage, and the second bias is greater than the ground voltage. Specifically, the medium voltage is equal to the breakdown voltage of the drain to source of the field effect transistor × 0.5, and the low voltage is equal to the breakdown voltage of the drain to source of the field effect transistor × 0.25.

[0061] Figure 5 FIG. 1 is a cross-sectional view of the structure of another embodiment of the first non-volatile memory cell of the present invention. Figure 6 FIG2 is a cross-sectional view of another embodiment of the second non-volatile memory cell of the present invention. Figure 5 and Figure 6 The first non-volatile memory cell 100 and the second non-volatile memory cell 101 can implement the P-type semiconductor region 2 on a P-type semiconductor substrate. The remaining structures have been described above and will not be repeated here.

[0062] According to the above embodiment, a small-area common voltage is repeatedly written into a non-volatile memory array by directly coupling common voltage lines together, thereby reducing the number of decoders and the overall area.

[0063] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications in the shape, structure, characteristics and spirit described in the scope of the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A small area common voltage multiple write non-volatile memory array, characterized in that: include: A plurality of parallel word lines, including a first word line and a second word line; A plurality of parallel selection lines are perpendicular to the plurality of word lines, wherein the plurality of selection lines include a first selection line; A plurality of parallel common voltage lines are perpendicular to the plurality of selection lines, and the plurality of common voltage lines are directly coupled together, wherein the plurality of common voltage lines include a first common voltage line and a second common voltage line, and the first word line and the second word line are respectively close to the first common voltage line and the second common voltage line; A plurality of memory sub-arrays, each of which is coupled to two word lines, a selection line and two common voltage lines, wherein each of the memory sub-arrays comprises: A first non-volatile memory cell is coupled to the first word line, the first selection line and the first common voltage line; and a second non-volatile memory cell is coupled to the second word line, the first selection line and the second common voltage line.

2. The small area common voltage multiple write non-volatile memory array according to claim 1, characterized in that: The first non-volatile memory unit cell and the second non-volatile memory unit cell are symmetrically arranged.

3. The small area common voltage multiple write non-volatile memory array according to claim 2, characterized in that: The first non-volatile memory cell and the second non-volatile memory cell are disposed in a P-type semiconductor region, and the first non-volatile memory cell includes: a first gate dielectric block, disposed on the P-type semiconductor region and between the first word line and the P-type semiconductor region, wherein the first gate dielectric block comprises a high dielectric constant material; a first common voltage gate, disposed on the first gate dielectric block and coupled to the first common voltage line, wherein the first common voltage gate is closer to the first common voltage line than the first word line, and the first common voltage gate comprises a high dielectric constant metal; A first N-type doping region, a second N-type doping region and a third N-type doping region are arranged in the P-type semiconductor region, wherein the first N-type doping region and the second N-type doping region are arranged on different sides of the P-type semiconductor region directly below the first word line, the second N-type doping region and the third N-type doping region are arranged on different sides of the P-type semiconductor region directly below the first common voltage gate, and the first N-type doping region is coupled to the first selection line.

4. The small area common voltage multiple write non-volatile memory array according to claim 3, characterized in that: The second non-volatile memory cell comprises: a second gate dielectric block disposed on the P-type semiconductor region and between the second word line and the P-type semiconductor region, wherein the second gate dielectric block comprises a high dielectric constant material; a second common voltage gate, disposed on the second gate dielectric block and coupled to the second common voltage line, wherein the second common voltage gate is closer to the second common voltage line than the second word line, and the second common voltage gate comprises a high dielectric constant metal; A fourth N-type doping region, a fifth N-type doping region and a sixth N-type doping region are arranged in the P-type semiconductor region, wherein the fourth N-type doping region and the fifth N-type doping region are arranged on different sides of the P-type semiconductor region directly below the second word line, the fifth N-type doping region and the sixth N-type doping region are arranged on different sides of the P-type semiconductor region directly below the second common voltage gate, and the fourth N-type doping region is coupled to the first selection line.

5. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is selected for formation, a medium voltage is applied to the first common voltage line, the medium voltage or the low voltage is applied to the first word line, a ground voltage is applied to the first selection line, the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

6. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is not selected for formation, a medium voltage is applied to the first common voltage line, a ground voltage is applied to the first word line, a bias voltage is applied to the first selection line or it is electrically floating, the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

7. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is selected for a setting action, half of a medium voltage is applied to the first common voltage line, the medium voltage or a low voltage is applied to the first word line, and a ground voltage is applied to the first selection line. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

8. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is not selected for setting, half of a middle voltage is applied to the first common voltage line, a ground voltage is applied to the first word line, a bias voltage is applied to the first selection line or the first selection line is electrically floating, the middle voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

9. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is selected for a reset action, a ground voltage is applied to the first common voltage line, a medium voltage or a low voltage is applied to the first word line, and half of the medium voltage is applied to the first selection line. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

10. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is not selected to perform a reset operation, a ground voltage is applied to the first common voltage line, the first word line, and the first selection line.

11. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is selected for a read operation, a ground voltage is applied to the first common voltage line, a medium voltage or a low voltage is applied to the first word line, a bias is applied to the first selection line, the medium voltage is greater than the low voltage, the medium voltage and the low voltage are both greater than the bias, and the bias is greater than the ground voltage.

12. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the first non-volatile memory cell is not selected for a read operation, a ground voltage is applied to the first common voltage line, the first word line, and the first selection line.

13. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is selected for formation, a medium voltage is applied to the second common voltage line, the medium voltage or the low voltage is applied to the second word line, a ground voltage is applied to the first selection line, the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

14. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is not selected for formation, a medium voltage is applied to the second common voltage line, a ground voltage is applied to the second word line, a bias voltage is applied to the first selection line or the first selection line is electrically floating, the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

15. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is selected for a setting action, half of a medium voltage is applied to the second common voltage line, the medium voltage or a low voltage is applied to the second word line, and a ground voltage is applied to the first selection line, the medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

16. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is not selected for setting, half of the middle voltage is applied to the second common voltage line, the second word line is applied with a ground voltage, the first selection line is biased or electrically floating, the middle voltage is greater than the bias, and the bias is greater than the ground voltage.

17. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is selected for reset, a ground voltage is applied to the second common voltage line, a medium voltage or a low voltage is applied to the second word line, and half of the medium voltage is applied to the first selection line. The medium voltage is greater than the low voltage, and both the medium voltage and the low voltage are greater than the ground voltage.

18. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is not selected for a reset operation, a ground voltage is applied to the second common voltage line, the second word line, and the first selection line.

19. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is selected for a read operation, a ground voltage is applied to the second common voltage line, a medium voltage or a low voltage is applied to the second word line, a bias is applied to the first selection line, the medium voltage is greater than the low voltage, the medium voltage and the low voltage are both greater than the bias, and the bias is greater than the ground voltage.

20. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: When the second non-volatile memory cell is not selected for a read operation, a ground voltage is applied to the second common voltage line, the second word line, and the first selection line.

21. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: The P-type semiconductor region is a P-type semiconductor substrate.

22. The small area common voltage multiple write non-volatile memory array according to claim 4, characterized in that: The P-type semiconductor region is a P-type doped well region, and the doped well region is arranged in an N-type semiconductor substrate.

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