Method and device for testing ECS circuit
By creating data errors in the storage array and using ECS circuits for error detection, the problem of not being able to effectively test ECS circuits in the prior art is solved, and verification and testing of the accuracy of ECS circuits is realized.
Patent Information
- Application Number
- CN202310782943.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2025-01-07
AI Technical Summary
The prior art cannot effectively manufacture errors in memory, which limits the testing of error checking and clearing (ECS) circuits, and thus cannot determine whether the errors detected by the ECS circuit are accurate.
By writing data to the storage array and performing preset processing on the target storage unit, it causes data errors to occur, and then performing error checking and clearing operations through the ECS circuit, the error storage unit is determined, and finally according to the target storage unit and the error storage unit Compare and verify the accuracy of the ECS circuit.
Accuracy testing of ECS circuits is achieved, ensuring the simplicity and high accuracy of the test method.
Smart Images
Figure CN119274633A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a method and a testing device for an ECS circuit. Background Art
[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.
[0003] Due to the faster and faster transmission speed of memory, the shrinking of memory cells and row hammer, errors may occur in the memory, so it is necessary to use an Error Check and Scrub (ECS) circuit to check and clear the memory. However, there is currently no effective means to solve the errors in the manufacturing memory, which limits the testing of the ECS circuit and makes it impossible to determine whether the errors detected by the ECS circuit are accurate. Summary of the invention
[0004] In view of this, embodiments of the present disclosure provide a method and a testing device for testing an ECS circuit.
[0005] In a first aspect, an embodiment of the present disclosure provides a method for testing an ECS circuit, the method comprising:
[0006] Write data to the storage array;
[0007] Performing a preset process on the storage array so as to cause a data error to occur in a target storage unit in the storage array;
[0008] Performing an ECS operation on the storage array by the ECS circuit to determine an erroneous storage cell;
[0009] A test result is determined according to the target storage unit and the error storage unit.
[0010] In some embodiments, the storage array includes at least one storage row, each of the storage rows includes at least one storage unit, and writing data to the storage array includes:
[0011] Data are written into each of the storage units respectively.
[0012] In some embodiments, the number of the target storage unit is at least one, and the performing of a preset process on the storage array to cause a data error to occur in the target storage unit in the storage array includes:
[0013] At least one target storage unit is determined from the at least one storage unit, and leakage processing is performed on the target storage unit to cause data errors in the target storage unit.
[0014] In some embodiments, determining the target storage unit and performing leakage processing on the target storage unit to cause a data error in the target storage unit includes:
[0015] Determine at least one target storage row, where the target storage row is a storage row including the target storage unit in the at least one storage row;
[0016] A refresh operation is performed on non-target storage rows so that the storage cells in the non-target storage rows do not leak electricity, and a refresh operation is not performed on the target storage row so that the storage cells in the target storage row leak electricity within a preset time after writing data to the storage array; wherein the preset time is a time required for the storage cells to leak electricity and cause data errors, and the non-target storage rows are the remaining storage rows in the storage array except the target storage row;
[0017] After the memory cell in the target memory row leaks electricity, data is written into the memory cells in the target memory row except the target memory cell.
[0018] In some embodiments, if each memory cell in the target memory row is the target memory cell, after the memory cells in the target memory row leak electricity, the step of directly performing an ECS operation on the memory array through the ECS circuit is performed.
[0019] In some embodiments, performing a refresh operation on a non-target storage row includes:
[0020] Performing an activation operation on the storage cells in the non-target storage row according to the activation command;
[0021] A precharge operation is performed on the memory cells in the non-target memory row according to the precharge command.
[0022] In some embodiments, the storage unit comprises a capacitor, wherein:
[0023] The preventing the memory cells in the non-target memory row from leaking electricity comprises: preventing the capacitors of the memory cells in the non-target memory row from leaking electricity;
[0024] The causing the memory cells in the target memory row to leak electricity comprises: causing the capacitors of the memory cells in the target memory row to leak electricity.
[0025] In some embodiments, determining a test result according to the target storage unit and the error storage unit includes:
[0026] Comparing the target storage unit with the error storage unit to determine whether the target storage unit is consistent with the error storage unit;
[0027] When the target storage unit and the error storage unit are consistent, it is determined that the ECS circuit has no defects; when the target storage unit and the error storage unit are inconsistent, it is determined that the ECS circuit has defects.
[0028] In some embodiments, the memory array is a dynamic random access memory.
[0029] In a second aspect, an embodiment of the present disclosure provides a testing device, the device comprising:
[0030] A write module configured to write data to the storage array;
[0031] an error generating module configured to perform a preset process on the storage array so as to cause a data error to occur in a target storage unit in the storage array;
[0032] A detection module configured to perform an ECS operation on the storage array through an ECS circuit to determine an erroneous storage unit;
[0033] The judgment module is configured to determine a test result according to the target storage unit and the error storage unit.
[0034] The disclosed embodiment provides a method and a testing device for an ECS circuit, wherein the method comprises: first, writing data to a storage array; second, performing a preset process on the storage array to cause a data error to occur in a target storage unit in the storage array; third, performing an ECS operation on the storage array through the ECS circuit to determine an erroneous storage unit; and finally, determining a test result according to the target storage unit and the erroneous storage unit. Since an ECS operation is performed on the storage array through the ECS circuit after a data error occurs in the target storage unit in the storage array, the erroneous storage unit is detected. Thus, the accuracy of the ECS circuit can be verified by comparing whether the target storage unit and the erroneous storage unit are consistent. The testing method is simple and has high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 A flowchart of a method for testing an ECS circuit provided in an embodiment of the present disclosure;
[0036] Figure 2 Schematic diagram of the layout structure of the storage array provided in the embodiment of the present disclosure Figure 1 ;
[0037] Figure 3 Schematic diagram of the layout structure of the storage array provided in the embodiment of the present disclosure Figure 2 ;
[0038] Figure 4 Schematic diagram of the layout structure of the storage array provided in the embodiment of the present disclosure Figure 3 ;
[0039] Figure 5 Schematic diagram of the layout structure of the storage array provided in the embodiment of the present disclosure Figure 4 ;
[0040] Figure 6 A schematic diagram of the structure of a test device provided in an embodiment of the present disclosure;
[0041] Figure 7 A hardware entity schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0042] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.
[0044] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0045] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.
[0046] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:
[0047] Dynamic Random Access Memory (DRAM);
[0048] Double Data Rate (DDR);
[0049] Error Check and Scrub (ECS);
[0050] Error Check and Correct (ECC);
[0051] Storage array (Array);
[0052] Multi-Purpose Command (MPC);
[0053] Refresh signal (Refresh All Bank);
[0054] Self-refresh signal (Self Refresh);
[0055] Joint Electron Device Engineering Council (JEDEC);
[0056] Mode Register (MR);
[0057] One Transistor One Capacitance (1T1C);
[0058] Two Transistor Two Capacitance (2T2C);
[0059] Word line (WL);
[0060] Bit line (BL);
[0061] Active Command (ACT);
[0062] Precharge command (Precharge).
[0063] Y-Page Write: A Y-direction write operation. When performing a write operation, a word line is opened and the contents of all burst lengths of cells on this word line are written sequentially, then this word line is closed, and then the next word line is opened to perform the same operation as above, until all word lines are written.
[0064] X-Fast Write: An X-direction write operation mode. Before each write operation, all word lines on the same bit line are sequentially opened. After a word line is opened and the contents of a burst length unit on the word line are sequentially written, the word line is closed, and then the next word line is opened and the contents of a burst length unit on the word line are sequentially written.
[0065] Y-Fast Write: A Y-direction write operation. Before each write operation, a word line is turned on, and after writing a burst length unit on this word line in sequence, the word line is turned off. Then the word line is turned on again to write a burst length unit in sequence. The word line is turned on and off repeatedly until all the corresponding storage units on this word line are written, and then the next word line is turned on to perform the same operation.
[0066] Taking DDR5 DRAM as an example, the ECS circuit allows the DRAM to read and modify the detected error codewords, write the corrected data back to the storage array, and record the error count. It requires a complete error check and clearing of the DRAM at least once every 24 hours. Among them, during the execution of the ECS operation, the ECC circuit can detect errors in the storage unit. Therefore, the errors detected during the execution of the ECS are usually called ECC errors. Since there is currently no effective means to create ECC errors in the storage array, the testing of the ECS circuit is limited, and it is impossible to determine whether the detection and correction results of the ECS circuit are accurate.
[0067] In order to test the ECS circuit and determine whether the ECS circuit is accurate, the embodiment of the present disclosure provides a method for testing the ECS circuit, including: first, writing data to a storage array; second, performing a preset process on the storage array to cause a data error to occur in a target storage unit in the storage array; third, performing an ECS operation on the storage array through the ECS circuit to determine the erroneous storage unit; and finally, determining the test result according to the target storage unit and the erroneous storage unit. Since the ECS operation is performed on the storage array through the ECS circuit after the data error occurs in the target storage unit in the storage array, the erroneous storage unit is detected. In this way, the accuracy of the ECS circuit can be verified by comparing whether the target storage unit (i.e., the storage unit with ECC error manufactured in this embodiment) and the erroneous storage unit (i.e., the storage unit with ECC error detected by the ECS circuit) are consistent. The test method is simple and has high accuracy.
[0068] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
[0069] In one embodiment of the present disclosure, see Figure 1 , which shows a flow chart of a method for testing an ECS circuit. The method for testing an ECS circuit includes: steps S110 to S140.
[0070] Step S110, writing data to the storage array;
[0071] Here, writing data into the storage array means: writing data into each storage unit in the storage array, that is, filling the storage array; wherein the written data may be a low-level logic 0, or a high-level logic 1, which is not limited in the present disclosure.
[0072] In addition, the process of writing data into the storage array may be to write data into the storage array in a Y-Page Write, X-Fast Write, Y-Fast Write, etc. The present disclosure is not limited to this.
[0073] Step S120, performing a preset process on the storage array to cause a data error to occur in a target storage unit in the storage array;
[0074] Here, causing a data error to occur in the target storage unit means: causing the data in the target storage unit to be different from the data value written in step S110. For example, when writing a logic 0 in the target storage unit, the data in the target storage unit is caused to have an error through a preset process, so that the written logic 0 is converted to a logic 1; for another example, when writing a logic 1 in the target storage unit, the data in the target storage unit is caused to have an error through a preset process, so that the written logic 1 is converted to a logic 0.
[0075] It should be noted that, taking DRAM as an example, the storage unit therein stores data through a capacitor. At this time, the preset processing may include: performing leakage processing on the capacitor in the target storage unit, so that the data in the target storage unit is erroneous. Specifically, after writing data to the target storage unit, waiting for a preset time, at which time the capacitor in the target storage unit will gradually leak electricity, thereby causing the data in the target storage unit to be erroneous.
[0076] It should also be noted that, in the process of performing preset processing on the target storage unit, the non-target storage unit can be refreshed and written to keep the data of the non-target storage unit in the storage array unchanged. The non-target storage unit is the other storage unit in the storage array except the target storage unit. In other words, the "preset processing" of the target storage unit is actually a way of "not processing" the target storage unit and performing normal refresh processing on the non-target storage unit.
[0077] Step S130, performing an ECS operation on the storage array through the ECS circuit to determine an erroneous storage cell;
[0078] It should be noted that in DRAM DDR5 chips, a complete error check and clearing of DRAM is required at least once every 24 hours. The ECS circuit can be used to generate ECS command signals and some internal command signals, as well as error tracking signals, to detect error information while performing internal read and write error detection and repair. For example, during the execution of an ECS operation, the ECC circuit can detect errors in the storage unit, thereby determining the erroneous storage unit.
[0079] In addition, taking the application of ECS operation in DRAM as an example, the ECS circuit provided by the embodiment of the present disclosure can realize error checking and clearing of the storage array. In short, the function to be realized by the ECS circuit is: in the manual ECS operation mode or the automatic ECS operation mode, the multi-purpose command signal or the refresh command signal is used to generate the ECS command signal, and the internal command signal necessary for the internal execution of the ECS operation is generated to perform complete error checking and clearing on the DRAM, and other modules are used to track and record the detected error information. Among them, the refresh command signal can include a refresh signal and a self-refresh signal.
[0080] The DDR5 JEDEC-defined ECS circuit integrates a counter to track and count the number of ECC errors detected, and stores the statistical results in the mode register MR16-20.
[0081] Step S140, determining a test result according to the target memory cell and the error memory cell.
[0082] In the disclosed embodiment, the consistency of the target storage unit and the error storage unit is determined; if the target storage unit and the error storage unit are consistent, it means that the ECC error detected by the ECS circuit is a pre-manufactured ECC error, and it can be determined that the ECS circuit has no defects; if the target storage unit and the error storage unit are inconsistent, it means that the ECC error detected by the ECS circuit is not a pre-manufactured ECC error, but a storage unit without an ECC error is mistakenly judged as an error storage unit, and it can be determined that the ECS circuit has defects.
[0083] Here, the consistency of the target storage unit and the error storage unit refers to whether the addresses in the target storage unit and the error storage unit are consistent, and may also include whether the data written to the target storage unit with the same address is consistent with the data detected in the error storage unit.
[0084] In the disclosed embodiment, after a data error occurs in a target storage cell in the storage array, an ECS operation is performed on the storage array through an ECS circuit to detect the erroneous storage cell. In this way, the accuracy of the ECS circuit can be verified by comparing whether the target storage cell and the erroneous storage cell are consistent. The testing method is simple and has high accuracy.
[0085] The method for testing the ECS circuit in the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings. Figures 2 to 5 A schematic diagram of the layout structure of a storage array provided in an embodiment of the present disclosure.
[0086] In some embodiments, please refer to Figure 1 and Figure 2 The storage array 10 includes at least one storage row, and each storage row includes at least one storage unit 11. Step S110, writing data to the storage array 10, includes: Step S111, writing data to each storage unit 11 respectively.
[0087] In the embodiment of the present disclosure, the memory array 10 includes a plurality of memory rows, and each memory row includes a plurality of memory cells 11. For example, Figure 2 The storage array 10 in the embodiment includes 8 storage rows, and each storage row includes 8 storage cells 11. In other embodiments, the storage array 10 may also include one or more storage rows, and each storage row may include one or more storage cells 11, which is not limited in the embodiments of the present disclosure.
[0088] It should be noted that since the embodiment of the present disclosure utilizes the leakage characteristics of the capacitor to cause errors in the data in the target storage unit 111, the embodiment of the present disclosure can be applied to a memory that uses capacitors to store data, that is, the storage array 10 can be a storage array in a DRAM, wherein, for DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.
[0089] Furthermore, the storage unit 11 in the present disclosure may be a structure with a capacitor such as 1T1C or 2T2C. For example, the storage unit 11 is a 1T1C structure, and the storage unit 11 may include a capacitor and a transistor; wherein the control end of the transistor (usually the gate) is connected to the word line, the first end of the transistor (usually the source) is connected to the bit line, and the second end of the transistor (usually the drain) is connected to the capacitor. The capacitor is used to store written data, the bit line is used to read or write the capacitor, and the word line is used to control the conduction and cutoff of the transistor, thereby controlling the charging and discharging process of the capacitor.
[0090] In some embodiments, please refer to Figure 1 , Figures 3 to 5 , the number of the target storage unit 111 is at least one. Step S120, performing a preset process on the storage array 10 to cause a data error to occur in the target storage unit 111 in the storage array 10, includes: step S121, determining at least one target storage unit 111 from at least one storage unit 11, and performing a leakage process on the target storage unit 111, so that a data error occurs in the target storage unit 111.
[0091] Here, the number of the determined target storage units 111 is at least one, and the number of the target storage units 111 is less than the number of the storage units 11. For example, if the number of the storage units 11 is 64, the number of the target storage units 111 may be 1, 2, 3 or more. Figure 3 The number of (as shown in the dashed box) is 11 as an example for explanation.
[0092] In addition, since the storage unit includes a capacitor, the embodiment of the present disclosure can perform leakage processing on the target storage unit 111 through the leakage characteristics of the capacitor, causing the capacitor of the target storage unit 111 to leak, thereby causing errors in the data stored in the target storage unit 111.
[0093] In some embodiments, please refer to Figures 3 to 5, step S121, determining the target storage unit 111, and performing leakage processing on the target storage unit 111, so that a data error occurs in the target storage unit 111, including: steps S121a to S121c.
[0094] Step S121a, determining at least one target storage row, where the target storage row is a storage row including the target storage unit 111 in the at least one storage row;
[0095] Please refer to Figure 3 , the dotted box is the target storage unit 111. At this time, the row where the target storage unit 111 is located, that is, the third row and the fifth row from bottom to top are the target storage rows.
[0096] Step S121b, performing a refresh operation on the non-target storage row so that the storage cells 11 in the non-target storage row do not leak electricity, and not performing a refresh operation on the target storage row so that the storage cells 11 in the target storage row leak electricity within a preset time after writing data to the storage array 10;
[0097] The preset duration is the duration required for the storage unit 11 to leak electricity and cause data errors, and the non-target storage rows are the remaining storage rows in the storage array 10 except the target storage row. Here, due to the leakage characteristics of the capacitor, the capacitor in the storage unit 11 continuously leaks electricity. When the capacitor leaks electricity to a certain extent, the data in the storage unit 11 will change, causing data errors, thereby successfully creating an ECC error in the target storage unit.
[0098] In some embodiments, please refer to Figure 4 , step S121b, performing a refresh operation on the non-target storage row, including: step S11 and step S12.
[0099] Step S11, performing an activation operation on the storage unit 11 in the non-target storage row according to the activation command;
[0100] In the disclosed embodiment, due to the leakage characteristics of the capacitor, in order to ensure that the data in the non-target storage row remains unchanged, an activation operation can be performed on the non-target storage row through an activation command. Specifically, the non-target storage row receives an ACT signal, activates the word line of the corresponding address of the non-target storage row, turns on the corresponding transistor of the non-target storage row, and prepares for a precharge operation.
[0101] Step S12, performing a precharge operation on the memory cells 11 in the non-target memory row according to the precharge command.
[0102] In the embodiment of the present disclosure, the precharge operation is performed on the non-target storage row through the precharge command, so that the data in the non-target storage row can be continuously refreshed, thereby avoiding the change of the data in the non-target storage row due to the capacitor leakage characteristics, thereby protecting the data in the non-target storage row. Specifically, when performing the precharge operation, the non-target storage row ( Figure 4 The area with the filling pattern in the middle is continuously charged, and the data in the non-target storage row is continuously refreshed to ensure the data is correct.
[0103] In some embodiments, please refer to Figure 4 , step S121b, preventing the memory cell 11 in the non-target memory row from leaking electricity, comprising: step S13, preventing the capacitor of the memory cell 11 in the non-target memory row from leaking electricity;
[0104] Step S121b, causing the memory cell 11 in the target memory row to leak electricity, includes: step S14, causing the capacitor of the memory cell 11 in the target memory row to leak electricity.
[0105] Here, the memory cell 11 in the present disclosure may be a structure having a capacitor such as 1T1C or 2T2C. For example, the memory cell 11 is a 1T1C structure, and the memory cell 11 may include a capacitor and a transistor.
[0106] The disclosed embodiment can utilize the leakage characteristics of the capacitor in the storage cell 11 to create an ECC error. Thus, the leakage characteristics of the capacitor can be combined with the charging characteristics of ACT PRE to continuously charge the capacitor of the storage cell 11 in the non-target storage row, thereby protecting the data in the storage cell 11 in the non-target storage row from being changed; at the same time, within the preset time period, since the target storage row is not refreshed, the leakage characteristics of the capacitor will cause the capacitor of the storage cell 11 in the target storage row to leak, causing errors in the data in the storage cell 11 in the non-target storage row (such as Figure 4 white area).
[0107] Step S121c, please refer to Figure 5 After the memory cell 11 in the target memory row leaks, data is written into the memory cells 11 in the target memory row except the target memory cell 111 .
[0108] In the embodiment of the present disclosure, the storage cells in the target storage row are not necessarily all target storage cells, and may also include non-target storage cells, for example, Figure 5 The fifth target storage row from bottom to top includes three target storage cells and five non-target storage cells 112. Since, after step S121b, the non-target storage cells 112 in the target storage row have also been subjected to leakage treatment (such as Figure 4 Therefore, before performing the ECS operation, the data in the non-target storage unit 112 in the target storage row needs to be restored to the correct value (i.e., the value at the time of writing).
[0109] Specifically, data is written into the non-target storage cells 112 in the target storage row again, so that the data in all non-target storage cells 112 are correct and the data in all target storage cells 111 are wrong.
[0110] In some other embodiments, please refer to Figure 4 If each memory cell 11 in the target memory row is the target memory cell 111, then after the memory cell 11 in the target memory row has a leakage, the step of directly performing an ECS operation on the memory array 10 through the ECS circuit is performed.
[0111] At this time, the data in all non-target storage units 112 are correct, and the data in all target storage units 111 are wrong.
[0112] In some embodiments, step S140, determining a test result according to the target storage unit 111 and the error storage unit, includes: step S141 and step S142.
[0113] Step S141, comparing the target storage unit 111 and the error storage unit to determine whether the target storage unit 111 and the error storage unit are consistent;
[0114] It can be seen that in the embodiment of the present disclosure, the target storage unit refers to: a storage unit that has an ECC error through a preset operation; the error storage unit refers to: a storage unit with an ECS error detected by the ECS circuit.
[0115] Step S142, when the target storage unit 111 and the error storage unit are consistent, it is determined that the ECS circuit has no defects; when the target storage unit 111 and the error storage unit are inconsistent, it is determined that the ECS circuit has defects.
[0116] If the erroneous storage unit detected by the ECS circuit is the same as the target storage unit 111, this indicates that the ECS circuit can correctly implement error checking and clearing of the storage array; otherwise, it indicates that the ECS circuit has defects and cannot correctly detect the ECC error, and cannot implement error checking and clearing of the storage array.
[0117] In short, the embodiments of the present disclosure provide a DRAM ECS test method using capacitor leakage characteristics (or called a DRAM ECS track test method, because the ECS circuit detects ECC errors inaccurately, which must be a defect in a certain link of the ECS circuit detection path). The method mainly includes the following four steps:
[0118] (1) Write data to the entire storage array; this step is to fill the entire array. Figure 2 (2) ACT and PRE protect the storage rows that do not need to generate ECC errors. After a long time, the unprotected storage rows will gradually leak electricity, causing ECC errors. This step is to use ACT and PRE to protect the "storage rows that do not need to generate ECC errors". Specifically, according to the row address from small to large, activate and precharge the non-target storage rows ( Figure 4 The non-target storage rows will be continuously charged and the data will be continuously refreshed. After a period of time, due to the leakage effect of the capacitor, the target storage row ( Figure 4 Some storage units (or storage bits) on the white storage rows in the middle will have errors due to leakage, then the data will change, the ECC check will be wrong, and thus an ECC error will be generated. (3) Rewrite the data in the unprotected storage rows (i.e., the target storage rows) in step (2) where no ECC error is required; in this step, since some storage rows do not require ECC errors for the entire storage row, but require errors to be made at specified locations, for those locations that do not require ECC errors, write the data again, and the ECC here will be recalculated and updated, and no ECC error will be generated; in this way, the disclosed embodiment can create ECC errors at any specified location for ECS track testing. (4) Verify whether the result of the ECS test is consistent with the manufactured ECC error, so as to determine whether the ECS circuit has defects.
[0119] In the disclosed embodiment, the leakage characteristics of the capacitor are used in combination with the charging characteristics of ACT and PRE to create an ECC error at a specified position for verifying and testing the ECS Track function. After a data error occurs in the target storage cell in the storage array, the ECS operation is performed on the storage array through the ECS circuit to detect the erroneous storage cell. In this way, the accuracy of the ECS circuit can be verified by comparing whether the target storage cell and the erroneous storage cell are consistent. The test method is simple and has high accuracy.
[0120] In another embodiment of the present disclosure, Figure 6 As shown, it shows a schematic diagram of the composition structure of a test device 20 provided in an embodiment of the present disclosure, which is used to perform the above-mentioned method of testing the ECS circuit, such as Figure 6 As shown, the testing device 20 comprises:
[0121] A writing module 21, configured to write data to the storage array 10;
[0122] The error generating module 22 is configured to perform a preset process on the storage array 10 so as to cause a data error to occur in the target storage unit 111 in the storage array 10;
[0123] A detection module 23, configured to perform an ECS operation on the storage array 10 through an ECS circuit to determine an erroneous storage cell;
[0124] The judgment module 24 is configured to determine the test result according to the target storage unit 111 and the error storage unit.
[0125] In some embodiments, the storage array includes at least one storage row, each storage row includes at least one storage cell, wherein: the writing module 21 is specifically configured to write data into each storage cell respectively.
[0126] In some embodiments, the number of target storage cells is at least one, wherein: the error generation module 22 is specifically configured to determine at least one target storage cell from at least one storage cell, and perform leakage processing on the target storage cell to cause a data error in the target storage cell.
[0127] In some embodiments, the error generation module 22 includes a first determination submodule and a refresh submodule, wherein: the first determination submodule is configured to determine at least one target storage row, and the target storage row is a storage row including a target storage cell in at least one storage row; the refresh submodule is configured to perform a refresh operation on a non-target storage row so that the storage cells in the non-target storage row do not leak electricity, and the refresh operation is not performed on the target storage row, so that the storage cells in the target storage row leak electricity within a preset time after writing data to the storage array; wherein the preset time is the time required for the storage cell to leak electricity and cause data errors, and the non-target storage rows are the remaining storage rows in the storage array except the target storage row; the write module is also configured to write data to the storage cells except the target storage cells in the target storage row after the storage cells in the target storage row leak electricity.
[0128] In some embodiments, if each storage cell in the target storage row is a target storage cell, the write module is further configured to directly perform an ECS operation on the storage array through the ECS circuit after leakage occurs in the storage cell in the target storage row.
[0129] In some embodiments, the refresh submodule is specifically configured to perform an activation operation on the storage cells in the non-target storage row according to the activation command; and perform a precharge operation on the storage cells in the non-target storage row according to the precharge command.
[0130] In some embodiments, the storage cells include capacitors, wherein: the refresh submodule is further specifically configured to prevent the capacitors of the storage cells in the non-target storage row from leaking; and to cause the capacitors of the storage cells in the target storage row to leak.
[0131] In some embodiments, the judgment module 24 includes a judgment submodule and a second determination submodule, wherein: the judgment submodule is configured to compare the target storage unit and the error storage unit to determine whether the target storage unit and the error storage unit are consistent; the second determination submodule is configured to determine that the ECS circuit is not defective when the target storage unit and the error storage unit are consistent; and determine that the ECS is defective when the target storage unit and the error storage unit are inconsistent.
[0132] It should be noted that the embodiments of the present disclosure relate to DDR ECS (such as DDR5 ECS), and in particular to DDR5 ECStrack, which uses the capacitor leakage characteristics and is applied to DDR5 ECS track testing. In the embodiments of the present disclosure, since the error generation module can detect the data error of the target storage unit in the storage array, and then use the detection module and the judgment module to perform ECS operations on the storage array to detect the erroneous storage unit, the accuracy of the ECS circuit can be verified by comparing whether the target storage unit and the erroneous storage unit are consistent. The test method is simple and has high accuracy.
[0133] It should be noted that the description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.
[0134] It should be noted that in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of commands to enable an electronic device (which can be a personal computer, server, etc.) to execute all or part of the methods of each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a ROM (Read Only Memory), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.
[0135] Correspondingly, an embodiment of the present disclosure provides an electronic device, including: a memory and a processor, the memory stores a computer program that can be run on the processor, and when the processor executes the program, the steps in the method for testing the ECS circuit provided in the above embodiment are implemented.
[0136] Correspondingly, an embodiment of the present disclosure provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the method for testing an ECS circuit are implemented.
[0137] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and electronic device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.
[0138] Figure 7 A hardware entity diagram of an electronic device provided by an embodiment of the present disclosure, such as Figure 7 As shown, the hardware entity of the electronic device 70 includes: a processor 71, a communication interface 72 and a memory 73, wherein the processor 71 generally controls the overall operation of the electronic device 70; the communication interface 72 enables the electronic device 70 to communicate with other electronic devices or servers or platforms through a network.
[0139] The processor 71 , the communication interface 72 and the memory 73 are connected via a bus.
[0140] The memory 73 is configured to store commands and applications executable by the processor 71, and can also cache data to be processed or processed by the processor 71 and various modules in the electronic device 70 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (Flash) or random access memory (Random Access Memory, RAM).
[0141] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.
[0142] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0143] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.
[0144] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0145] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.
[0146] The features disclosed in several method or circuit embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or circuit embodiments.
[0147] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A method for testing an ECS circuit, characterized in that: The method comprises: Write data to the storage array; Performing a preset process on the storage array so as to cause a data error to occur in a target storage unit in the storage array; Performing an ECS operation on the storage array by the ECS circuit to determine an erroneous storage cell; A test result is determined according to the target storage unit and the error storage unit.
2. The method according to claim 1, characterized in that The storage array includes at least one storage row, each of the storage rows includes at least one storage unit, and writing data to the storage array includes: Data are written into each of the storage units respectively.
3. The method according to claim 2, characterized in that The number of the target storage unit is at least one, and the performing of a preset process on the storage array so as to cause a data error to occur in the target storage unit in the storage array includes: At least one target storage unit is determined from the at least one storage unit, and leakage processing is performed on the target storage unit to cause data errors in the target storage unit.
4. The method according to claim 3, characterized in that Determining the target storage unit and performing leakage processing on the target storage unit so as to cause a data error in the target storage unit includes: Determine at least one target storage row, where the target storage row is a storage row including the target storage unit in the at least one storage row; A refresh operation is performed on non-target storage rows so that the storage cells in the non-target storage rows do not leak electricity, and a refresh operation is not performed on the target storage row so that the storage cells in the target storage row leak electricity within a preset time after writing data to the storage array; wherein the preset time is a time required for the storage cells to leak electricity and cause data errors, and the non-target storage rows are the remaining storage rows in the storage array except the target storage row; After the memory cell in the target memory row leaks electricity, data is written into the memory cells in the target memory row except the target memory cell.
5. The method according to claim 4, characterized in that If each memory cell in the target memory row is the target memory cell, then after the memory cells in the target memory row leak electricity, the step of directly performing an ECS operation on the memory array through the ECS circuit is performed.
6. The method according to claim 5, characterized in that The performing a refresh operation on the non-target storage row includes: Performing an activation operation on the storage cells in the non-target storage row according to the activation command; A precharge operation is performed on the memory cells in the non-target memory row according to the precharge command.
7. The method according to claim 6, characterized in that The storage unit comprises a capacitor, wherein: The step of preventing the memory cells in the non-target memory row from leaking electricity comprises: preventing the capacitors of the memory cells in the non-target memory row from leaking electricity; The causing the memory cells in the target memory row to leak electricity includes: causing the capacitors of the memory cells in the target memory row to leak electricity.
8. The method according to claim 1, characterized in that The step of determining a test result according to the target storage unit and the error storage unit includes: Comparing the target storage unit with the error storage unit to determine whether the target storage unit is consistent with the error storage unit; When the target storage unit and the error storage unit are consistent, it is determined that the ECS circuit has no defects; when the target storage unit and the error storage unit are inconsistent, it is determined that the ECS circuit has defects.
9. The method according to any one of claims 1 to 8, characterized in that: The storage array belongs to a dynamic random access memory.
10. A testing device, characterized in that: The device comprises: A write module configured to write data to the storage array; an error generating module configured to perform a preset process on the storage array so as to cause a data error to occur in a target storage unit in the storage array; A detection module configured to perform an ECS operation on the storage array through an ECS circuit to determine an erroneous storage unit; The judgment module is configured to determine a test result according to the target storage unit and the error storage unit.