Semiconductor structure and manufacturing method thereof, memory and manufacturing method thereof, and electronic equipment
By using a double-layer barrier layer structure and high-efficiency etchant in the STI process to form a shallow groove isolation structure, the problems of reducing the thickness of the silicon nitride layer and damage to the barrier layer are solved, and the quality and electrical performance of DRAM products are improved.
Patent Information
- Application Number
- CN202310813747.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-04
- Publication Date
- 2025-01-07
AI Technical Summary
When the existing STI process forms a shallow groove isolation structure, it is easy to cause the thickness of the silicon nitride layer to decrease, increase the risk of breakdown, affect the quality of DRAM products, and traditional grinding processes are difficult to avoid damage to the barrier layer and affect the integrity of the substrate.
A double-layer barrier layer structure is adopted, wherein the first barrier layer is used to prevent etching to the substrate, and the second barrier layer prevents chemical mechanical polishing damage. The first insulating layer is etched efficiently by etching agent to form a shallow groove isolation structure , and stop etching at the preset position to avoid breakdown and damage.
It realizes the protection of the substrate while forming a shallow groove isolation structure, reduces material costs and etching costs, and improves the quality and electrical performance of DRAM products.
Smart Images
Figure CN119275175A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a semiconductor structure and manufacturing method, a memory and manufacturing method, and an electronic device. Background Art
[0002] Shallow Trench Isolation (STI) is a process that uses a silicon nitride mask to deposit, pattern, and etch silicon to form a trench, and then fills the trench with deposited oxide for isolation from silicon. Compared with the Local Oxidation of Silicon (LOCOS) process, the STI process has better isolation characteristics. Summary of the invention
[0003] The present application provides a semiconductor structure and a manufacturing method, a memory and a manufacturing method, and an electronic device.
[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:
[0005] Providing a substrate with a plurality of grooves, and forming a first barrier layer on a side of the substrate where the grooves are provided, wherein the first barrier layer covers the inner wall of the groove and the substrate;
[0006] forming a first insulating layer on a side of the first barrier layer away from the substrate, wherein the first insulating layer at least fills a portion of the trench;
[0007] forming a second barrier layer on a side of the first insulating layer away from the substrate, wherein the second barrier layer covers the first insulating layer;
[0008] forming a second insulating layer on a side of the second barrier layer away from the substrate;
[0009] performing a planarization process to expose the second barrier layer;
[0010] removing the second barrier layer to expose the first insulating layer;
[0011] The first insulating layer is etched by using an etchant whose etching rate for the first insulating layer is greater than that for the first barrier layer, and the etching is stopped at a preset position in the trench, and the remaining first insulating layer in the trench forms a shallow trench isolation structure.
[0012] Optionally, forming a first barrier layer comprises:
[0013] A silicon nitride film layer having a thickness greater than or equal to 1 nm and less than or equal to 8 nm is formed on one side of the substrate where the groove is provided by atomic layer deposition technology to serve as a first barrier layer.
[0014] Optionally, the substrate has an array region and a peripheral region, and on a plane parallel to the substrate, the width of the grooves in the array region is smaller than the width of the grooves in the peripheral region;
[0015] Forming a first insulating layer, comprising:
[0016] A silicon oxide film layer is formed on a side of the first barrier layer away from the substrate by a spin spraying method to serve as a first insulating layer, and the first insulating layer at least fills the grooves located in the array area.
[0017] Optionally, the trenches located in the array region are word line isolation trenches, and between adjacent word line isolation trenches there are active column columns, the active column columns include a plurality of active columns, and the active columns include drains, channels, and sources arranged in sequence in a direction from the bottom of the word line isolation trench to the top of the word line isolation trench;
[0018] A shallow trench isolation structure is formed, comprising:
[0019] The first insulating layer is etched by a steam etching method to remove a portion of the first insulating layer in the grooves in the array area, and the remaining first insulating layer in the grooves in the array area forms a shallow trench isolation structure, and the upper surface of the shallow trench isolation structure is lower than or flush with the upper surface of the drain, wherein the etching selectivity of the etchant to the first insulating layer and the first barrier layer is greater than or equal to 10:1.
[0020] Optionally, forming a second barrier layer comprises:
[0021] A silicon nitride film layer with a thickness greater than 3 nm is formed on a side of the first insulating layer away from the substrate by atomic layer deposition technology to serve as a second barrier layer.
[0022] Optionally, forming a second insulating layer includes:
[0023] A silicon oxide film layer is formed on a side of the second barrier layer away from the substrate by a spin spraying method to serve as a second insulating layer.
[0024] Optionally, a planarization process is performed, including:
[0025] The second insulating layer is chemically mechanically polished until the second barrier layer is exposed, wherein the thickness of the remaining second barrier layer is less than 3 nm.
[0026] Optionally, before removing the second barrier layer, the method further comprises:
[0027] Cleaning the second barrier layer after chemical mechanical polishing;
[0028] Removing the second barrier layer, comprising:
[0029] The second barrier layer is stripped by using a hot phosphoric acid wet etching method.
[0030] In a second aspect, an embodiment of the present application provides a method for manufacturing a memory, including the method for manufacturing the semiconductor structure described above;
[0031] The method for manufacturing the memory further includes:
[0032] Before forming the first barrier layer, forming a plurality of bit lines extending along a first direction;
[0033] After forming the shallow trench isolation structure, a plurality of word lines extending along a second direction are formed, wherein the second direction is arranged at an angle to the first direction.
[0034] In a third aspect, an embodiment of the present application provides a semiconductor structure manufactured using the above-mentioned semiconductor structure manufacturing method.
[0035] In a fourth aspect, an embodiment of the present application provides a memory manufactured using the above-mentioned memory manufacturing method.
[0036] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: the above-mentioned semiconductor structure, or the above-mentioned memory.
[0037] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:
[0038] The semiconductor structure and manufacturing method, memory and manufacturing method, and electronic device provided by the embodiments of the present application form two barrier layers during the process of manufacturing the semiconductor structure, wherein the first barrier layer serves as an etching barrier layer to prevent etching to the substrate during the process of etching the first insulating layer to form a shallow trench isolation structure; the second barrier layer serves as a grinding barrier layer to prevent chemical mechanical polishing from damaging the first insulating layer; and an etchant having an etching rate for the first insulating layer greater than the etching rate for the first barrier layer is used to etch the first insulating layer, and the etching is stopped at a preset position in the groove, which can avoid the problem that the conventional grinding process stops on the first barrier layer and causes certain damage to the barrier layer, resulting in the barrier layer being penetrated and damaging the substrate during the subsequent etching of the first insulating layer, and can achieve the purpose of forming a shallow trench isolation structure in the trench of the substrate while avoiding damage to the substrate.
[0039] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0041] Figure 1A schematic diagram of a process for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0042] Figure 2 for Figure 1 The process schematic diagram of step S11 of the method for manufacturing the semiconductor structure shown;
[0043] Figure 3 for Figure 1 The process schematic diagram of step S12 of the method for manufacturing the semiconductor structure shown;
[0044] Figure 4 for Figure 1 The process schematic diagram of step S13 of the method for manufacturing the semiconductor structure shown;
[0045] Figure 5 for Figure 1 The process schematic diagram of step S14 of the method for manufacturing the semiconductor structure shown;
[0046] Figure 6 for Figure 1 The process schematic diagram of step S15 of the method for manufacturing the semiconductor structure shown;
[0047] Figure 7 for Figure 1 The process schematic diagram of step S16 of the method for manufacturing the semiconductor structure shown;
[0048] Figure 8 for Figure 1 The process schematic diagram of step S17 of the method for manufacturing the semiconductor structure shown;
[0049] Fig. 9 A schematic flow chart of a method for manufacturing a semiconductor structure used in a vertical channel memory provided in an embodiment of the present application;
[0050] Fig.10 for Fig. 9 The process schematic diagram of step S21 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0051] Fig.11 for Fig. 9 The process schematic diagram of step S22 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0052] Fig.12 for Fig. 9 The process schematic diagram of step S23 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0053] Fig.13 for Fig. 9The process schematic diagram of step S24 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0054] Fig.14 for Fig. 9 The process schematic diagram of step S25 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0055] Fig.15 for Fig. 9 The process schematic diagram of step S26 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0056] Fig.16 for Fig. 9 The process schematic diagram of step S28 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown;
[0057] Fig.17 for Fig. 9 The process diagram of step S29 of the method for manufacturing a semiconductor structure used in a vertical channel memory is shown.
[0058] Reference numerals:
[0059] 10-array area; 20-peripheral area;
[0060] BL-bit line; S-source; D-drain; CH-channel;
[0061] 100-groove; 100a-word line isolation groove; 100b-groove located in the peripheral area;
[0062] 11-substrate; 110-active column array; 111-active column; 12-first barrier layer; 13-first insulating layer; 13a-shallow trench isolation structure; 13b-remaining insulating layer; 14-second barrier layer; 14a-second barrier layer remaining after chemical mechanical polishing; 15-second insulating layer; 161-ion implantation layer; 162-first metal structure; 163-second metal structure; 17-protective layer. DETAILED DESCRIPTION
[0063] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.
[0064] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".
[0065] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0066] For a vertical channel memory, that is, a memory including a vertical channel transistor (VCT), after the bit line is fabricated, a shallow trench isolation structure is usually formed in a word line isolation trench using STI technology in a subsequent bit line silicide process (BLs loop).
[0067] During the STI process, the silicon nitride layer needs to be patterned as a hard mask, and a silicon oxide layer is formed on the silicon nitride layer. The silicon oxide layer is then polished by chemical mechanical polishing (CMP) until the silicon nitride layer is exposed.
[0068] However, STI CMP usually causes the thickness of the silicon nitride layer to be reduced by more than 2nm, resulting in a smaller thickness of the silicon nitride layer. There is a risk of breakdown at the weak points of the silicon nitride layer, which will reduce the quality of DRAM (Dynamic Random Access Memory) products. In order to provide space for subsequent processes, in some products (such as vertical channel memory), as the integration continues to increase, the space left for the silicon nitride layer is very small, making the thickness of the silicon nitride layer limited. It is necessary to control the reduction of the thickness of the silicon nitride layer by STI CMP to within 2nm, otherwise there is a risk of breakdown at the weak points of the silicon nitride layer.
[0069] In order to avoid the above-mentioned breakdown, the etching time is often controlled, resulting in incomplete etching of the silicon oxide layer on the silicon nitride layer, resulting in a small amount of silicon oxide residue on the silicon nitride layer, which will also reduce the quality of DRAM products.
[0070] The semiconductor structure and manufacturing method, memory and manufacturing method, and electronic device provided in this application are intended to solve at least one of the above technical problems in the prior art.
[0071] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.
[0072] The present application provides a method for manufacturing a semiconductor structure. Figures 1 to 8 As shown, the method for manufacturing the semiconductor structure provided in this embodiment includes:
[0073] S11 : providing a substrate 11 having a plurality of grooves 100 , and forming a first barrier layer 12 on a side of the substrate 11 having the grooves 100 , wherein the first barrier layer 12 covers inner walls of the grooves 100 and the substrate 11 .
[0074] Specifically, Figure 2 As shown, in this embodiment, step S11 includes: forming a silicon nitride film layer with a thickness greater than or equal to 1 nm and less than or equal to 8 nm on one side of the substrate 11 where the groove 100 is provided by atomic layer deposition technology to serve as the first barrier layer 12. Optionally, the substrate 11 is a silicon substrate.
[0075] Optionally, in the embodiment of the present application, before forming the first barrier layer 12, the method for manufacturing the semiconductor structure further includes:
[0076] A protective layer 17 is formed on one side of the substrate 11 where the trench 100 is provided by a thermal oxidation method.
[0077] Specifically, Fig.10 As shown, the thermal oxidation method specifically grows a protective layer 17 on the inner wall of the trench 100 and the surface of one side of the substrate 11 where the trench 100 is provided. Specifically, the exposed silicon reacts with oxygen at a high temperature, such as 800° C. to 1150° C., thereby generating silicon oxide to form the protective layer 17. The protective layer 17 can protect the substrate 11, thereby enhancing the protection of the substrate 11 and preventing the structures on the substrate 11 (source S, drain D and channel CH) from being damaged.
[0078] In the embodiment of the present application, the first barrier layer 12 serves as an etching barrier layer, which can prevent the protective layer 17 and the substrate 11 from being etched during the process of etching the first insulating layer 13 to form the shallow trench isolation structure 13 a.
[0079] Specifically, Figure 2As shown, in this embodiment, the substrate 11 has an array region 10 and a peripheral region 20. On a plane parallel to the substrate 11, the width of the groove 100 located in the array region 10 is smaller than the width of the groove 100 located in the peripheral region 20; wherein the array region 10 is a region for designing functional devices (such as transistors and capacitors), and the integration level of the peripheral region 20 is much lower than that of the array region 10.
[0080] S12 : forming a first insulating layer 13 on a side of the first barrier layer 12 away from the substrate 11 , wherein the first insulating layer 13 at least fills a portion of the trench 100 .
[0081] Specifically, Figure 3 As shown, in this embodiment, step S12 includes: forming a silicon oxide film layer on the side of the first barrier layer 12 away from the substrate 11 by a spin spray method to serve as a first insulating layer 13, and the first insulating layer 13 at least fills the groove 100 located in the array region 10.
[0082] For the array region 10 with narrower grooves 100, the filling speed of the first insulating layer 13 formed by the rotary spraying method in the narrow grooves 100 in the array region 10 is greater than the filling speed of the grooves 100 in the peripheral region 20. Therefore, the first insulating layer 13 can easily fill the narrow grooves 100 in the array region 10, but it is difficult to fill the larger grooves 100 in the peripheral region 20. In this step, the grooves 100 in the array region 10 are filled or nearly filled. Even if the grooves 100 in the peripheral region 20 are not filled, it will not damage the quality of the final product. In this way, it is unnecessary to make an overly thick first insulating layer 13, which is beneficial to saving material costs and reducing subsequent etching costs.
[0083] S13 : forming a second barrier layer 14 on a side of the first insulating layer 13 away from the substrate 11 , wherein the second barrier layer 14 covers the first insulating layer 13 .
[0084] Specifically, Figure 4 As shown, in this embodiment, step S13 includes: forming a silicon nitride film layer with a thickness greater than 3 nm on the side of the first insulating layer 13 away from the substrate 11 by atomic layer deposition technology to serve as the second barrier layer 14. The reason why the thickness of the second barrier layer 14 needs to be greater than 3 nm is to prevent the second barrier layer 14 from being completely ground away in the subsequent chemical mechanical polishing and unable to be used as a mask.
[0085] like Figure 4As shown, since the grooves 100 located in the array area 10 have been filled or nearly filled by the first insulating layer 13, the second barrier layers 14 located in the array area 10 are all located above the grooves 100, while the second barrier layers 14 located in the peripheral area 20 are partially located in the grooves 100 of the peripheral area 20, and the other part is located above the protrusions between the grooves 100 of the peripheral area 20.
[0086] S14 : forming a second insulating layer 15 on the second barrier layer 14 .
[0087] Specifically, Figure 5 As shown, in this embodiment, step S14 includes: forming a silicon oxide film layer on a side of the second barrier layer 14 away from the substrate 11 by a spin spraying method to serve as the second insulating layer 15 .
[0088] like Figure 5 As shown, since the first insulating layer 13 previously filled or nearly filled the grooves 100 located in the array area 10, the second barrier layers 14 located in the array area 10 are all located above the grooves 100, while the grooves 100 located in the peripheral area 20 are not filled by the first insulating layer 13, and part of the second barrier layer 14 located in the peripheral area 20 is located in the grooves 100 of the peripheral area 20, and the other part is located above the protrusions between the grooves 100 in the peripheral area 20. Therefore, the upper surface of the second insulating layer 15 located in the array area 10 is relatively flat, and the second insulating layer 15 located in the peripheral area 20 fills the grooves 100 located in the peripheral area 20 and covers the second barrier layer 14, and the upper surface of the second insulating layer 15 located in the peripheral area 20 has a height difference.
[0089] S15 : performing a planarization process to expose the second barrier layer 14 .
[0090] Specifically, Figure 6 As shown, in this embodiment, step S15 includes: using a grinding liquid to chemically mechanically polish the second insulating layer 15 until the second barrier layer 14 is exposed, wherein the remaining thickness of the second barrier layer 14 is less than 3nm. Specifically, the second barrier layer 14 located directly above the active pillar 111 is exposed.
[0091] The upper surface of the film layer formed by the spin spraying method is relatively flat, but it is far from the flatness required for the subsequent formation of a mask, so chemical mechanical polishing is required to obtain a flat upper surface.
[0092] In the embodiment of the present application, the second insulating layer 15 is formed on a side of the second barrier layer 14 away from the substrate 11 and covers the second barrier layer 14. The upper surface of the second insulating layer 15 located in the array area 10 is relatively flat. The second insulating layer 15 located in the peripheral area 20 fills the groove 100 located in the peripheral area 20. In this way, chemical mechanical polishing is facilitated to achieve flattening treatment to expose the second barrier layer 14.
[0093] In the embodiment of the present application, the second barrier layer 14 is used as a grinding barrier layer to prevent chemical mechanical polishing from damaging the first insulating layer 13 .
[0094] In this embodiment, after the chemical mechanical polishing, the method for manufacturing the semiconductor structure further includes: cleaning the second barrier layer 14 after the chemical mechanical polishing.
[0095] Specifically, in this embodiment, cleaning the second barrier layer 14 after the chemical mechanical polishing includes: using an ACM cleaning device to clean the second barrier layer 14 after the chemical mechanical polishing to remove slurry generated during the chemical mechanical polishing process.
[0096] S16: removing the second barrier layer 14 to expose the first insulating layer 13.
[0097] Specifically, Figure 7 As shown, in this embodiment, step S16 includes: using a hot phosphoric acid wet etching method to peel off the second barrier layer 14 to expose the first insulating layer 13. The first insulating layer 13 is located on the side of the first barrier layer 12 away from the substrate 11, and covers the first barrier layer 12. On the one hand, the first barrier layer 12 is not damaged by chemical mechanical polishing, which avoids the problem of thinning the barrier layer thickness caused by chemical mechanical polishing of the first insulating layer in the prior art. On the other hand, when the first insulating layer 13 is etched, the first barrier layer 12 located on the surface of one side of the substrate 11 (specifically including the first barrier layer 12 located directly above the active pillar 111) will not contact the etchant for the first time, which shortens the contact time of the first barrier layer 12 with the etchant, and can reduce the influence of the etchant on the first barrier layer 12. Therefore, it can avoid the problem of breaking through the first barrier layer 12 in the subsequent etching process of the first insulating layer 13, resulting in damage to the protective layer 17 and the substrate 11.
[0098] S17: using an etchant whose etching rate for the first insulating layer 13 is greater than that for the first barrier layer 12, the first insulating layer 13 is etched, and the etching is stopped at a preset position in the groove 100, and the remaining first insulating layer 13 in the groove 100 forms a shallow trench isolation structure 13a.
[0099] In this embodiment, the trench 100 located in the array area 10 is a word line isolation trench 100a, and an active column column 110 is located between adjacent word line isolation trenches 100a. The active column column 110 includes a plurality of active columns 111. The active columns 111 include a drain D, a channel CH, and a source S arranged in sequence in a direction from the bottom of the word line isolation trench 100a to the top of the word line isolation trench 100a.
[0100] Optionally, the material of the substrate 11 is silicon. The material of the active pillar 111 is silicon.
[0101] Specifically, Figure 8 As shown, in this embodiment, step S17 includes: etching the first insulating layer 13 using a steam etching method to remove a portion of the first insulating layer 13 located in the groove 100 of the array area 10, and the remaining first insulating layer 13 located in the groove 100 of the array area 10 forms a shallow trench isolation structure 13a, and the upper surface of the shallow trench isolation structure 13a is lower than or flush with the upper surface of the drain D, wherein the etching selectivity of the etchant to the first insulating layer 13 and the first barrier layer 12 is greater than or equal to 10:1.
[0102] like Figure 8 As shown, in this embodiment, the remaining first insulating layer 13 in the trench 100 in the peripheral region 20 is a remaining insulating layer 13 b.
[0103] Optionally, the steam etching method is performed under the condition of relatively high etching selectivity for the first insulating layer 13 and the first barrier layer 12, that is, the steam etching method is performed under the condition of relatively high etching selectivity for silicon oxide and silicon nitride. In this way, the influence of the etchant on the first barrier layer 12 can be reduced during the etching of the first insulating layer 13, thereby avoiding the problem of breaking through the first barrier layer 12 and damaging the protective layer 17 and the substrate 11 during the subsequent etching of the first insulating layer 13.
[0104] It should be noted that Figures 2 to 8 In the substrate 11 shown, only a part of the array region 10 and a part of the peripheral region 20 are shown. The boundary between the array region 10 and the peripheral region 20 is shown at Figures 2 to 8 The area between the array area 10 and the peripheral area 20 shown in FIG.
[0105] Through the manufacturing method of the semiconductor structure provided in this embodiment, two barrier layers (including a first barrier layer 12 and a second barrier layer 14) can be formed, wherein the first barrier layer 12 is used as an etching barrier layer to prevent the protective layer 17 and the substrate 11 from being etched during the process of etching the first insulating layer 13 to form a shallow trench isolation structure 13a; the second barrier layer 14 is used as a grinding barrier layer to prevent chemical mechanical polishing from causing damage to the first insulating layer 13; and an etchant with an etching rate for the first insulating layer 13 greater than the etching rate for the first barrier layer 12 is used to etch the first insulating layer 13, and the etching is stopped at a preset position in the groove 100, which can avoid the problem that the conventional grinding process stops on the first barrier layer and causes certain damage to the barrier layer, resulting in the breakdown of the barrier layer and damaging the substrate in the subsequent etching of the first insulating layer, and can achieve the purpose of forming the shallow trench isolation structure 13a in the groove 100 of the substrate 11 while avoiding damage to the protective layer 17 and the substrate 11.
[0106] A common application scenario of the shallow trench isolation structure includes application in a vertical channel memory. Based on this, this embodiment provides a method for manufacturing a semiconductor structure (the semiconductor structure has a shallow trench isolation structure) applied in a vertical channel memory.
[0107] In the method for manufacturing a semiconductor structure used in a vertical channel memory provided in this embodiment, a substrate 11 is used to manufacture a vertical channel memory, and the provided substrate is the substrate 11 after forming a bit line BL; the trench 100 located in the array region 10 is a word line isolation trench 100a, and between adjacent word line isolation trenches 100a is an active column 110, and the active column column 110 includes a plurality of active columns 111, and the active columns 111 include a drain D, a channel CH, and a source S arranged in sequence in a direction from the bottom of the word line isolation trench 100a to the top of the word line isolation trench 100a. Optionally, the material of the active column 111 is silicon.
[0108] For vertical channel memory, based on the requirements for integration, the word line isolation groove has a large depth and a small width, and the barrier layer must not have a large thickness, otherwise it will occupy the space of the subsequent structure in the groove 100. Therefore, the design of using two barrier layers in the manufacturing method of the semiconductor structure is particularly suitable for vertical channel memory.
[0109] The manufacturing method provided in this embodiment is applied to the silicide process after the bit line BL is manufactured in the vertical channel memory, that is, the BLs loop process. Figures 10 to 17In a specific embodiment, the bit line BL includes an ion implantation layer 161, a first metal structure 162, and a second metal structure 163. The ion implantation layer 161 is formed by implanting ions at a set position of the substrate 11, and has better conductivity after ion implantation. The ion implantation layer 161 is provided with a plurality of grooves, and a layer of the first metal is first deposited in the grooves to serve as the first metal structure 162, and then the grooves are filled with the second metal to serve as the second metal structure 163. In a specific embodiment, the first metal is titanium (Ti), and the second metal is tungsten (W).
[0110] Figures 10 to 17 The figure shows a schematic cross-sectional view of a substrate 11 cut along a direction parallel to the bit line BL. In a vertical channel memory, a bit line isolation groove parallel to the extending direction of the bit line BL and a word line isolation groove 100a parallel to the extending direction of the word line are provided on the substrate 11. It should be noted that the extending direction of the bit line BL is perpendicular to the extending direction of the word line, and Figures 10 to 17 The word lines are not shown in the figure, and the word lines are formed in the subsequent process of the method for manufacturing the semiconductor structure provided in the present application.
[0111] It should be noted that Figures 10 to 17 The bit line BL in the substrate 11 shown in FIG. 1 may also be in other forms, such as using a metal bit line BL instead of Figures 10 to 17 The bit line BL of the “ion implantation layer+metal structure” shown in FIG. 1 is not limited in the present application.
[0112] like Figures 9 to 17 As shown, the method for manufacturing a semiconductor structure used in a vertical channel CH memory provided in this embodiment includes:
[0113] S21: providing a substrate 11 on which a bit line BL is fabricated, wherein the substrate 11 on which the bit line BL is fabricated is provided with a word line isolation groove 100a perpendicular to the extension direction of the bit line BL, and between adjacent word line isolation grooves 100a there is an active column array 110, wherein the active column array 110 includes a plurality of active columns 111 and an isolation medium between adjacent active columns 111; forming a protective layer 17 on a surface of the substrate 11 on which the word line isolation groove 100a is provided by a thermal oxidation method.
[0114] like Fig.10 As shown, the thermal oxidation method specifically grows a protective layer 17 on the top and exposed sidewalls of the active pillar 111. Specifically, the exposed silicon reacts with oxygen at a high temperature, such as 800° C. to 1150° C., thereby generating silicon oxide to form the protective layer 17. The protective layer 17 can protect the active pillar 111, thereby enhancing the protection of the active pillar 111 and preventing the structures (source S, drain D, and channel CH) on the active pillar 111 from being damaged.
[0115] S22 : forming a silicon nitride film layer with a thickness greater than or equal to 1 nm and less than or equal to 8 nm on the protective layer 17 by atomic layer deposition technology to serve as the first barrier layer 12 .
[0116] like Fig.11 As shown, in order to improve the integration degree, the width of the word line isolation groove 100a is limited, so the thickness of the first barrier layer 12 is relatively small, so as to provide accommodation space for subsequent structures.
[0117] S23: The substrate 11 includes an array region 10 and a peripheral region 20. On a plane parallel to the substrate 11, the width of the groove located in the array region 10 is smaller than the width of the groove 100b located in the peripheral region 20. The groove located in the array region 10 is the word line isolation groove 100a. A silicon oxide film layer is formed on the side of the first barrier layer 12 away from the substrate 11 by a rotary spraying method to serve as a first insulating layer 13. The first insulating layer 13 at least fills the word line isolation groove 100a.
[0118] like Fig.12 As shown, the word line isolation groove 100a located in the array region 10 is narrower, while the width of the groove 100b located in the peripheral region 20 is larger. Based on the characteristics of the rotary spraying method, the filling speed of the first insulating layer 13 in the narrow groove 100 located in the array region 10 is greater than the filling speed of the groove 100 located in the peripheral region 20. Therefore, the narrow word line isolation groove 100a is easy to be filled, while the groove 100b located in the peripheral region 20 with a larger width is not easy to be filled. Since the groove 100b located in the peripheral region 20 will not affect the final product quality even if it is not filled, it is sufficient to fill the word line isolation groove 100a or nearly fill it. In this way, it is unnecessary to make an overly thick first insulating layer 13, which is beneficial to saving material costs and reducing subsequent etching costs.
[0119] S24 : forming a silicon nitride film layer with a thickness greater than 3 nm on the first insulating layer 13 by atomic layer deposition technology to serve as the second barrier layer 14 .
[0120] like Fig.13 As shown, the thickness of the second barrier layer 14 needs to be greater than 3 nm. This is because the subsequent chemical mechanical polishing will cause damage to the second barrier layer 14 of about 3 nm when the second insulating layer 15 located in the array area 10 is fully polished. This ensures that the second barrier layer 14 can still be relatively intact after chemical mechanical polishing.
[0121] S25 : forming a silicon oxide film layer on the side of the second barrier layer 14 away from the substrate 11 by a spin spray method to serve as the second insulating layer 15 .
[0122] like Fig.14As shown, since the first insulating layer 13 previously filled or nearly filled the word line isolation groove 100a, and the groove 100b located in the peripheral area 20 was not filled, the upper surface of the second insulating layer 15 located in the array area 10 is relatively flat, while the upper surface of the second insulating layer 15 located in the peripheral area 20 has a height difference.
[0123] S26: chemically mechanically polishing the substrate 11 on which the second insulating layer 15 is formed until the second barrier layer 14 is exposed, and the thickness of the remaining second barrier layer 14a after chemical mechanical polishing is less than 3 nm.
[0124] like Fig.15 As shown, the silicon oxide film layer (ie, the second insulating layer 15 ) is chemically mechanically polished using a polishing liquid until the second barrier layer 14 is exposed, specifically, the second barrier layer 14 located directly above the active pillar 111 is exposed.
[0125] S27: cleaning the second barrier layer 14 after chemical mechanical polishing.
[0126] In this embodiment, an ACM cleaning device is used to clean the second barrier layer 14 after the chemical mechanical polishing to remove the slurry generated during the chemical mechanical polishing process.
[0127] S28: removing the second barrier layer 14 to expose the first insulating layer 13.
[0128] like Fig.16 As shown, in this embodiment, a hot phosphoric acid wet etching method is adopted to strip off the second barrier layer 14 to expose the first insulating layer 13 .
[0129] S29: Etching the first insulating layer 13 by steam etching to remove part of the first insulating layer 13 in the word line isolation groove 100a to form a shallow trench isolation structure 13a; the active pillar 111 includes a drain D, a channel CH and a source S arranged in sequence in a direction from the bottom of the word line isolation groove 100a to the top of the word line isolation groove 100a, and the upper surface of the shallow trench isolation structure 13a is lower than or flush with the upper surface of the drain D. Etching the first insulating layer 13 by using an etchant having an etching selectivity ratio of greater than or equal to 10:1 to the first insulating layer 13 and the first barrier layer 12, and stopping the etching at a preset position in the word line isolation groove 100a.
[0130] like Fig.17 As shown, the shallow trench isolation structure 13a is located in the word line isolation trench 100a, and the upper surface of the shallow trench isolation structure 13a is lower than or flush with the upper surface of the drain D. The shallow trench isolation structure 13a is used to achieve isolation between adjacent active pillars 111. The remaining first insulating layer 13 in the trench 100 located in the peripheral area 20 forms a remaining insulating layer 13b.
[0131] The method for manufacturing a semiconductor structure used in a vertical channel CH memory provided in this embodiment uses a double-layer barrier layer to protect the active pillar 111, thereby preventing the source S, drain D and channel CH in the active pillar 111 from being damaged during the subsequent etching process, thereby improving the performance of the transistor in the memory.
[0132] Based on the same inventive concept, an embodiment of the present application also provides a method for manufacturing a memory, which includes the method for manufacturing the semiconductor structure in the above embodiment and has the beneficial effects of the method for manufacturing the semiconductor structure in the above embodiment, which will not be repeated here.
[0133] The manufacturing method of the memory provided in this embodiment further includes: before forming the first barrier layer 12, forming a plurality of strips along the first direction (for example, along Fig.10 After forming the shallow trench isolation structure 13a, a plurality of lines extending in a second direction (eg, perpendicular to the left and right directions of the paper) are formed. Fig.10 The word line is extended in the direction of the paper, wherein the second direction is arranged at an angle with the first direction. In some specific embodiments, the first direction is perpendicular to the second direction.
[0134] Based on the same inventive concept, an embodiment of the present application further provides a semiconductor structure, which is manufactured using the above-mentioned semiconductor structure manufacturing method and has the beneficial effects of the semiconductor structure manufacturing method in the above-mentioned embodiment, which will not be described in detail here.
[0135] Specifically, the semiconductor structure provided in this embodiment has a shallow trench isolation structure and can be applied to a vertical channel memory.
[0136] Based on the same inventive concept, an embodiment of the present application further provides a memory, which is manufactured using the manufacturing method of the memory in the above embodiment and has the beneficial effects of the manufacturing method of the memory in the above embodiment, which will not be described in detail here.
[0137] Specifically, the memory provided in this embodiment may be a DRAM memory. Through electron microscope imaging and electrical performance testing, the results show that the damage to the active pillar of the DRAM memory obtained by the memory manufacturing method provided in this application is significantly less than the damage to the active pillar of the DRAM memory made by only using one barrier layer in the BLs loop process in the prior art, and the electrical performance is also improved.
[0138] Based on the same inventive concept, an embodiment of the present application also provides an electronic device. The electronic device provided in this embodiment includes the semiconductor structure or memory in the above embodiment, and has the beneficial effects of the semiconductor structure or memory in the above embodiment, which will not be repeated here.
[0139] Specifically, the electronic device in the embodiment of the present application includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply, etc., which can be determined according to actual conditions. The storage device can include a memory in a computer, etc., which is not limited here.
[0140] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:
[0141] 1) The semiconductor structure and manufacturing method, memory and manufacturing method, and electronic device provided in this embodiment form two barrier layers during the process of manufacturing the semiconductor structure, wherein the first barrier layer serves as an etching barrier layer to prevent etching to the substrate during the process of etching the first insulating layer to form a shallow trench isolation structure; the second barrier layer serves as a grinding barrier layer to prevent chemical mechanical polishing from damaging the first insulating layer; and an etchant having an etching rate for the first insulating layer greater than the etching rate for the first barrier layer is used to etch the first insulating layer, and the etching is stopped at a preset position in the groove, which can avoid the problem that the conventional grinding process stops on the first barrier layer and causes certain damage to the barrier layer, resulting in the barrier layer being penetrated and damaging the substrate during the subsequent etching of the first insulating layer, and can achieve the purpose of forming a shallow trench isolation structure in the trench of the substrate while avoiding damage to the substrate.
[0142] 2) In the semiconductor structure and manufacturing method, memory and manufacturing method, and electronic device provided in this embodiment, during the process of forming a shallow trench isolation structure, the first insulating layer can only fill the grooves located in the array area. Even if the grooves located in the peripheral area are not filled, it will not cause damage to the quality of the final product. In this way, there is no need to produce an overly thick first insulating layer, which is beneficial to saving material costs and reducing subsequent etching costs.
[0143] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.
[0144] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.
[0145] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.
[0146] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.
[0147] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.
[0148] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of grooves, and forming a first barrier layer on a side of the substrate having the grooves, wherein the first barrier layer covers inner walls of the grooves and the substrate; forming a first insulating layer on a side of the first barrier layer away from the substrate, wherein the first insulating layer at least fills a portion of the trench; forming a second barrier layer on a side of the first insulating layer away from the substrate, wherein the second barrier layer covers the first insulating layer; forming a second insulating layer on a side of the second barrier layer away from the substrate; performing a planarization process to expose the second barrier layer; removing the second barrier layer to expose the first insulating layer; The first insulating layer is etched by using an etchant whose etching rate for the first insulating layer is greater than that for the first barrier layer, and the etching is stopped at a preset position in the trench, and the remaining first insulating layer in the trench forms a shallow trench isolation structure.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a first barrier layer, comprising: A silicon nitride film layer having a thickness greater than or equal to 1 nm and less than or equal to 8 nm is formed on a side of the substrate where the groove is provided by atomic layer deposition technology to serve as the first barrier layer.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The substrate has an array region and a peripheral region, and on a plane parallel to the substrate, the width of the grooves located in the array region is smaller than the width of the grooves located in the peripheral region; Forming a first insulating layer, comprising: A silicon oxide film layer is formed on a side of the first barrier layer away from the substrate by a spin spraying method to serve as a first insulating layer, and the first insulating layer at least fills the grooves located in the array area.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The trenches located in the array region are word line isolation trenches, and between adjacent word line isolation trenches are active column rows, wherein the active column rows include a plurality of active columns, and the active columns include drains, channels, and sources arranged in sequence in a direction from the bottom of the word line isolation trench to the top of the word line isolation trench; A shallow trench isolation structure is formed, comprising: The first insulating layer is etched by a steam etching method to remove a portion of the first insulating layer located in the groove of the array area, and the remaining first insulating layer in the groove of the array area forms a shallow trench isolation structure, and the upper surface of the shallow trench isolation structure is lower than or flush with the upper surface of the drain, wherein the etching selectivity of the etchant to the first insulating layer and the first barrier layer is greater than or equal to 10:
1.
5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: forming a second barrier layer, comprising: A silicon nitride film layer with a thickness greater than 3 nm is formed on a side of the first insulating layer away from the substrate by atomic layer deposition technology to serve as the second barrier layer.
6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: Forming a second insulating layer, comprising: A silicon oxide film layer is formed on a side of the second barrier layer away from the substrate by a spin spraying method to serve as the second insulating layer.
7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: Perform flattening, including: The second insulating layer is chemically mechanically polished until the second barrier layer is exposed, wherein the remaining thickness of the second barrier layer is less than 3 nm.
8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: Before removing the second barrier layer, the method further comprises: Cleaning the second barrier layer after chemical mechanical polishing; Removing the second barrier layer comprises: The second barrier layer is stripped by using a hot phosphoric acid wet etching method.
9. A method for manufacturing a memory, characterized in that: A method for manufacturing a semiconductor structure comprising any one of claims 1 to 8; The method for manufacturing the memory further includes: Before forming the first barrier layer, forming a plurality of bit lines extending along a first direction; After forming the shallow trench isolation structure, a plurality of word lines extending along a second direction are formed, wherein the second direction is arranged at an angle to the first direction.
10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the manufacturing method of any one of claims 1 to 8.
11. A memory, characterized in that: The memory is manufactured by the manufacturing method of the memory according to claim 9.
12. An electronic device, characterized in that: include: The semiconductor structure according to claim 10, or the memory according to claim 11.