Radio frequency power amplifier using VDMOS device and debugging method thereof

Abstract

The present application belongs to the field of electronic communication technology, and discloses a radio frequency power amplifier using a VDMOS device and a debugging method thereof. The VDMOS device is used as a power amplifier tube, and the power amplifier comprises a radio frequency input terminal, a power division module, a first impedance matching module, a power amplifier module, a second impedance matching module, a power synthesis module and a radio frequency output terminal connected in sequence from front to back; the power amplifier tube is a VDMOS device, and a direct current isolation structure is provided between any two adjacent modules among the power division module, the first impedance matching module, the power amplifier module, the second impedance matching module and the power synthesis module, so as to solve the problems of complex structure, low output power and poor frequency characteristics of the radio frequency power amplifier in the prior art, and has the advantages of simple structure, high output power, good frequency characteristics, highly linear transconductance and large safe working area.

Description

Technical Field

[0001] The present application relates to the field of electronic communication technology, and in particular to a radio frequency power amplifier using a VDMOS device and a debugging method thereof. Background Art

[0002] VDMOS (vertical double diffused metal oxide semiconductor field effect transistor) devices have the advantages of both bipolar transistors and ordinary MOS devices. Compared with bipolar transistors, it has low switching loss, high input impedance, low driving power, good frequency characteristics, and highly linear transconductance. It is particularly worth pointing out that it has a negative temperature coefficient, does not have the secondary breakdown problem of bipolar power, and has a large safe operating area. Therefore, whether it is a switching application or a linear application, VDMOS devices are ideal power devices.

[0003] In the field of RF power amplifiers, existing designs often fail to fully utilize the advantages of VDMOS devices, resulting in limited output power levels, complex structures, and low efficiency. Specifically, the existing technology has many deficiencies in key links such as power division, impedance matching, and power synthesis, such as uneven signal distribution, inaccurate impedance matching, and low power synthesis efficiency. These problems seriously restrict the performance improvement of RF power amplifiers. Therefore, it is necessary to seek an RF power amplifier that can fully utilize the advantages of VDMOS devices, has a simple structure, and can achieve a higher output power level. Summary of the invention

[0004] The purpose of the present application is to provide a radio frequency power amplifier using a VDMOS device and a debugging method thereof, which can fully utilize the advantages of the VDMOS device, have a simple structure and can achieve a higher output power level.

[0005] In a first aspect, the present application provides a radio frequency power amplifier using a VDMOS device, comprising a radio frequency input terminal, a power division module, a first impedance matching module, a power amplifier module, a second impedance matching module, a power synthesis module and a radio frequency output terminal connected in sequence from front to back;

[0006] The power division module is used to divide the input radio frequency signal into two radio frequency signals with the same power;

[0007] The power amplifier module includes two power amplifier tubes and a bias circuit for providing an operating voltage for the power amplifier tubes;

[0008] The first impedance matching module and the second impedance matching module are respectively used to achieve impedance matching of the input end and the output end of the two power amplifier tubes;

[0009] The power synthesis module is used to synthesize the two RF signals output from the second impedance matching module into one output RF signal;

[0010] The power amplifier tube is a VDMOS device, and a DC isolation structure is provided between any two adjacent modules among the power division module, the first impedance matching module, the power amplifier module, the second impedance matching module and the power synthesis module.

[0011] This RF power amplifier solves the problems of complex structure, low output power and poor frequency characteristics of RF power amplifiers in the prior art through precise signal distribution, impedance matching and power synthesis. It has the advantages of simple structure, high output power, good frequency characteristics, highly linear transconductance and large safe operating area.

[0012] Preferably, each of the DC blocking structures includes at least one DC blocking capacitor.

[0013] Preferably, the power division module comprises a first inductor L1, a second inductor L2, a first resistor R1, at least one first combined capacitor c1, at least one first shunt capacitor c2 and at least one second shunt capacitor c3; the inductance values ​​of the first inductor L1 and the second inductor L2 are equal, and the number and capacitance values ​​of the first shunt capacitors c2 and the second shunt capacitors c3 are equal;

[0014] The first end of the first inductor L1, the first end of the second inductor L2, and the first end of each of the first combining capacitors c1 are all connected to the RF input end, the second end of the first inductor L1, the first end of each of the first shunt capacitors c2, and the first end of the first resistor R1 are connected as an output end of the power division module, the second end of the second inductor L2, the first end of each of the second shunt capacitors c3, and the second end of the first resistor R1 are connected as a second output end of the power division module, and the second end of each of the first combining capacitors c1, the second end of each of the first shunt capacitors c2, and the second end of each of the second shunt capacitors c3 are all grounded.

[0015] Preferably, the first impedance matching module includes two two-stage L-type LC matching networks with the same structure; the first ends of the two two-stage L-type LC matching networks are respectively connected to the two output ends of the power division module, and the second ends of the two two-stage L-type LC matching networks are respectively connected to the gates of the two power amplifier tubes.

[0016] Preferably, each of the two-stage L-type LC matching networks includes a third inductor L3 and a fourth inductor L4, the first end of the third inductor L3 and the second end of the fourth inductor L4 are respectively connected to the first end of at least one capacitor whose second end is grounded, the second end of the third inductor L3 and the first end of the fourth inductor L4 are connected and commonly connected to the first end of at least one capacitor whose second end is grounded.

[0017] Preferably, the bias circuit includes two first bias circuits and two second bias circuits, the two first bias circuits are respectively connected to the gates of the two power amplifier tubes, the two second bias circuits are respectively connected to the drains of the two power amplifier tubes, the sources of the two power amplifier tubes are both grounded, and the drains of the two power amplifier tubes are also connected to the second impedance matching module.

[0018] Preferably, the second impedance matching module includes two first-level L-type LC matching networks with the same structure, the first ends of the two first-level L-type LC matching networks are respectively connected to the drains of the two power amplifier tubes, and the second ends of the two first-level L-type LC matching networks are both connected to the power synthesis module.

[0019] Preferably, each of the first-stage L-type LC matching networks includes a fifth inductor L5, a first end of the fifth inductor L5 is connected to the drain of the corresponding power amplifier tube, and a second end of the fifth inductor L5 is connected to the first end of at least one capacitor whose second end is grounded and the power synthesis module.

[0020] Preferably, the power synthesis module includes a second resistor R2, a sixth inductor L6, a seventh inductor L7, at least one third shunt capacitor c4, at least one fourth shunt capacitor c5 and at least one second combining capacitor c6; the inductance values ​​of the sixth inductor L6 and the seventh inductor L7 are equal, and the number and capacitance values ​​of the third shunt capacitor c4 and the fourth shunt capacitor c5 are equal;

[0021] The first end of the second resistor R2, the first end of each of the third shunt capacitors c4, and the first end of the sixth inductor L6 are all connected to the second end of one of the first-level L-type LC matching networks, the second end of the second resistor R2, the first end of each of the fourth shunt capacitors c5, and the first end of the seventh inductor L7 are all connected to the second end of another first-level L-type LC matching network, the second end of the sixth inductor L6, the second end of the seventh inductor L7, and the first end of each of the second combining capacitors c6 are all connected to the RF output end, and the second end of each of the third shunt capacitors c4, the second end of each of the fourth shunt capacitors c5, and the second end of each of the second combining capacitors c6 are all grounded.

[0022] In a second aspect, the present application provides a debugging method for optimizing the device parameters of the power synthesis module in the radio frequency power amplifier using the VDMOS device described above; the debugging method comprises the steps of:

[0023] A1. Determine the output impedance of the two power amplifier tubes;

[0024] A2. According to the measured output impedance, using a simulation method, obtain the device parameters of the power synthesis module that can match the output impedance of the two power amplifier tubes to 50Ω, recorded as the optimized device parameters;

[0025] A3. Based on the optimized device parameters, a real circuit of the RF power amplifier using the VDMOS device is constructed, and the real circuit is tested to further fine-tune the device parameters of the power synthesis module.

[0026] Beneficial effects: The RF power amplifier using VDMOS devices and the debugging method thereof provided in the present application use VDMOS devices as power amplifier tubes, including an RF input end, a power division module, a first impedance matching module, a power amplifier module, a second impedance matching module, a power synthesis module and an RF output end connected in sequence from front to back; the power division module is used to divide the input RF signal into two RF signals with the same power; the power amplifier module includes two power amplifier tubes and a bias circuit for providing a working voltage for the power amplifier tube; the first impedance matching module and the second impedance matching module are respectively used to achieve impedance matching of the input end and the output end of the two power amplifier tubes; the power synthesis module is used to synthesize the two RF signals output from the second impedance matching module into one output RF signal; the power amplifier tube is a VDMOS device, and a DC isolation structure is provided between any two adjacent modules in the power division module, the first impedance matching module, the power amplifier module, the second impedance matching module and the power synthesis module, which solves the problems of complex structure, low output power, poor frequency characteristics and the like of the RF power amplifier in the prior art, and has the advantages of simplified structure, high output power, good frequency characteristics, highly linear transconductance, large safe working area and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A circuit diagram of a radio frequency power amplifier using a VDMOS device provided in an embodiment of the present application.

[0028] Figure 2 It is a structural diagram of the power division module.

[0029] Figure 3 It is a structural schematic diagram of the first impedance matching module.

[0030] Figure 4 It is a structural diagram of the power amplifier module.

[0031] Figure 5 is a schematic structural diagram of a second impedance matching module.

[0032] Figure 6 It is a structural diagram of the power synthesis module.

[0033] Figure 7 A flowchart of a debugging method provided in an embodiment of the present application.

[0034] Explanation of reference numerals: 1. RF input terminal; 2. power division module; 3. first impedance matching module; 4. power amplifier module; 401. power amplifier tube; 402. first bias circuit; 403. second bias circuit; 5. second impedance matching module; 6. power synthesis module; 7. RF output terminal; 8. DC blocking capacitor. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0036] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0037] In modern communication systems, RF power amplifiers are one of the key components and are widely used in wireless communications, radar, broadcasting, etc. With the continuous development of communication technology, the performance requirements for RF power amplifiers are becoming higher and higher, especially in terms of high frequency, high power and high efficiency.

[0038] Traditional RF power amplifiers usually use bipolar transistors or ordinary MOS devices. However, these devices have some limitations in high-frequency and high-power applications. For example, bipolar transistors have large switching losses, low input impedance, high drive power, poor frequency characteristics, and secondary breakdown problems. Although ordinary MOS devices have improved in some aspects, they still have shortcomings in high-power applications.

[0039] The emergence of VDMOS devices has brought new hope to the design of RF power amplifiers. VDMOS devices have the advantages of both bipolar transistors and ordinary MOS devices, with the characteristics of low switching loss, high input impedance, low driving power, good frequency characteristics, and highly linear transconductance. In addition, VDMOS devices have a negative temperature coefficient, no secondary breakdown problem, and a large safe operating area, which is particularly suitable for high-frequency and high-power applications.

[0040] In practical applications, such as in wireless communication base stations, RF power amplifiers need to process high-power RF signals and amplify them to a sufficient power level to ensure effective signal transmission and coverage. Traditional RF power amplifiers often face problems such as low efficiency, high heat generation, and poor stability when processing high-power signals, making it difficult to meet the needs of modern communication systems.

[0041] In order to fully utilize the advantages of VDMOS devices, it is particularly important to design an RF power amplifier with a simple structure and high output power level. Through reasonable circuit design and optimization, efficient RF signal amplification can be achieved, ensuring the efficiency and stability of signal transmission, while reducing power loss and heat generation, and improving the overall performance of the system.

[0042] In this context, a new RF power amplifier design is proposed to address the limitations of existing technologies, give full play to the advantages of VDMOS devices, and achieve efficient and high-power RF signal amplification. This design ensures pure signal transmission between modules through reasonable module division and circuit optimization, avoids DC current interference and RF resonance, and thus improves the performance and reliability of the RF power amplifier.

[0043] Please refer to Figure 1-Figure 6 , a radio frequency power amplifier using a VDMOS device in some embodiments of the present application includes a radio frequency input terminal 1, a power division module 2, a first impedance matching module 3, a power amplifier module 4, a second impedance matching module 5, a power synthesis module 6 and a radio frequency output terminal 7 connected in sequence from front to back;

[0044] The power splitter module 2 is used to split the input RF signal into two RF signals with equal power;

[0045] The power amplifier module 4 includes two power amplifier tubes 401 (or referred to as radio frequency switch tubes) and a bias circuit for providing a working voltage for the power amplifier tubes 401;

[0046] The first impedance matching module 3 and the second impedance matching module 5 are used to achieve impedance matching of the input end and the output end of the two power amplifier tubes 401 respectively;

[0047] The power synthesis module 6 is used to synthesize the two RF signals output from the second impedance matching module 5 into one output RF signal;

[0048] The power amplifier tube 401 is a VDMOS device, and a DC isolation structure is provided between any two adjacent modules among the power division module 2, the first impedance matching module 3, the power amplifier module 4, the second impedance matching module 5 and the power synthesis module 6.

[0049] The RF power amplifier can divide the input RF signal into two RF signals with the same power through the power division module 2, so as to ensure that the two power amplifier tubes 401 receive signals with the same power, thereby realizing balanced amplification; the first impedance matching module 3 and the second impedance matching module 5 are used to realize impedance matching between the input and output ends of the two power amplifier tubes 401, so as to ensure the efficiency and stability of signal transmission; two VDMOS power amplifier tubes are used in the power amplifier module 4, and the VDMOS device has high input impedance, low switching loss and good frequency characteristics, and can realize efficient RF signal amplification; the two RF signals output from the second impedance matching module 5 are synthesized into one output RF signal through the power synthesis module 6; a DC isolation structure is set between each module to prevent the interference of DC current between each module, ensure the pure transmission of the signal, and avoid the occurrence of RF resonance phenomenon; through the above design, the RF power amplifier can make full use of the advantages of the VDMOS device to realize efficient RF signal amplification, and at the same time, the structure is simplified, and a higher output power level can be achieved.

[0050] This application uses VDMOS devices to fully utilize their high input impedance, low switching loss and good frequency characteristics to achieve efficient RF signal amplification. The reasonable design and optimization of the power division module 2, the first impedance matching module 3, the power amplifier module 4, the second impedance matching module 5 and the power synthesis module 6 ensure the efficiency and stability of signal transmission. The setting of the DC isolation structure effectively prevents the interference of DC current and ensures the pure transmission of the signal. Compared with traditional RF power amplifiers, the design of this application shows higher efficiency and stability in high frequency and high power applications, and solves the problems of low efficiency, high heat generation and poor stability in traditional designs.

[0051] In fact, at least one DC isolation structure is provided for each RF signal transmission line between two adjacent modules, for example Figure 1 In the embodiment, there are two RF signal transmission lines between two adjacent modules, so at least two DC isolation structures are set between two adjacent modules, wherein at least one (for example Figure 1 In the embodiment, a DC isolation structure is provided on each RF signal transmission line between two adjacent modules, but is not limited thereto).

[0052] Further, see Figure 1 , each DC blocking structure includes at least one DC blocking capacitor 8.

[0053] The function of the DC isolation capacitor 8 is to prevent the DC component from passing through, while allowing the AC signal (RF signal) to pass through, thereby achieving DC isolation between the modules. This design can prevent the DC bias voltage from having an adverse effect on the transmission of the RF signal, and ensure the transmission quality and stability of the RF signal between the modules. By setting at least one DC isolation capacitor 8 in each DC isolation structure, DC isolation between modules can be effectively achieved, the performance and reliability of the RF power amplifier can be improved, and the occurrence of RF resonance can be avoided, thereby effectively preventing the large current phenomenon caused by RF resonance at the static operating point of the VDMOS power amplifier tube when the gate voltage and drain-source voltage are given.

[0054] In a specific implementation, each DC isolation structure may include one or more DC isolation capacitors 8, which may be connected in series and / or in parallel to achieve the best DC isolation effect. For example, DC isolation capacitors 8 may be provided between the power division module 2 and the first impedance matching module 3, between the first impedance matching module 3 and the power amplifier module 4, between the power amplifier module 4 and the second impedance matching module 5, and between the second impedance matching module 5 and the power synthesis module 6. In this way, it is possible to ensure that the DC components between the modules are effectively isolated, and to avoid the influence of DC bias on the transmission of RF signals.

[0055] The selection and configuration of the DC blocking capacitor 8 need to consider the frequency characteristics and power requirements of the RF signal. Generally, the capacitance value of the DC blocking capacitor 8 should be large enough to ensure low impedance within the operating frequency range so as not to significantly affect the transmission of the RF signal. At the same time, the DC blocking capacitor 8 should have good high-frequency characteristics and low loss to ensure the transmission quality and efficiency of the RF signal.

[0056] In the process of solving the above technical problems, the setting of the DC blocking capacitor 8 between the modules plays a key role. By blocking the transmission of the DC component, the DC blocking capacitor 8 effectively prevents the DC bias voltage from interfering with the RF signal, ensuring the stable transmission of the RF signal. In addition, the DC blocking capacitor 8 can also avoid the occurrence of RF resonance, thereby preventing the VDMOS power amplifier tube from having a large current phenomenon at the static operating point. Compared with the prior art, this design has significant advantages and can improve the performance and reliability of the RF power amplifier.

[0057] In some embodiments, see Figure 2 The power division module 2 includes a first inductor L1, a second inductor L2, a first resistor R1, at least one first combined capacitor c1, at least one first shunt capacitor c2, and at least one second shunt capacitor c3; the inductance values ​​of the first inductor L1 and the second inductor L2 are equal, and the number and capacitance values ​​of the first shunt capacitors c2 and the second shunt capacitors c3 are equal;

[0058] The first end of the first inductor L1, the first end of the second inductor L2 and the first end of each first combining capacitor c1 are all connected to the RF input terminal 1, the second end of the first inductor L1, the first end of each first shunt capacitor c2 and the first end of the first resistor R1 are connected as an output end of the power division module 2, the second end of the second inductor L2, the first end of each second shunt capacitor c3 and the second end of the first resistor R1 are connected as the second output end of the power division module 2, and the second end of each first combining capacitor c1, the second end of each first shunt capacitor c2 and the second end of each second shunt capacitor c3 are all grounded.

[0059] The number and capacitance value of the first shunt capacitor c2 and the second shunt capacitor c3 are equal, and the inductance values ​​of the first inductor L1 and the second inductor L2 are equal. The matching of these components ensures that the input RF signal can be evenly divided into two RF signals with the same power. The first resistor R1 is connected between the output ends of the two signal branches, and plays the role of a balancing circuit, further ensuring the uniform distribution of the signal.

[0060] In a specific implementation, the capacitance values ​​of the first combined capacitor c1, the first shunt capacitor c2, and the second shunt capacitor c3 can be adjusted within a certain range to adapt to RF signals of different frequencies. The inductance values ​​of the first inductor L1 and the second inductor L2 can also be adjusted according to actual needs. The resistance value of the first resistor R1 can be selected according to the specific situation of the circuit to ensure uniform distribution of the signal and stability of the circuit.

[0061] Preferably, see Figure 2 The first end of the first inductor L1 is connected to the RF input terminal 1 through a first capacitor C1, and the first end of the second inductor L2 is connected to the RF input terminal 1 through a second capacitor C2; the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are equal.

[0062] The first capacitor C1 and the second capacitor C2 block the DC component from passing through, while allowing the AC signal (RF signal) to pass through, thereby preventing the DC bias voltage from adversely affecting the transmission of the RF signal and ensuring the transmission quality and stability of the RF signal.

[0063] In some embodiments, see Figure 3 The first impedance matching module 3 includes two two-stage L-type LC matching networks with the same structure; the first ends of the two two-stage L-type LC matching networks are respectively connected to the two output ends of the power division module 2 (the two ends of the first resistor R1), and the second ends of the two two-stage L-type LC matching networks are respectively connected to the gates of the two power amplifier tubes 401.

[0064] The two two-stage L-type LC matching networks in the first impedance matching module 3 achieve impedance matching between the output signal of the power division module 2 and the input end of the power amplifier tube 401 through their structural design. Each two-stage L-type LC matching network adjusts the impedance characteristics of the signal through a combination of inductance and capacitance, so that the signal can be effectively transmitted to the gate of the power amplifier tube 401, reducing reflection and loss, thereby improving the overall efficiency and performance of the RF power amplifier. Through the design of this matching network, the stability and consistency of the RF signal during transmission are ensured, solving the problems of low efficiency and poor performance caused by impedance mismatch.

[0065] In a specific implementation, the first ends of the two two-stage L-type LC matching networks are respectively connected to the two output ends of the power division module to ensure uniform distribution of the signal. Each two-stage L-type LC matching network includes two inductors and two capacitors, and the combination of inductors and capacitors can achieve different impedance matching effects by adjusting their values. Through this design, it is possible to flexibly adapt to different input impedance requirements of the power amplifier tube 401.

[0066] Further, see Figure 3 Each two-stage L-type LC matching network includes a third inductor L3 and a fourth inductor L4, a first end of the third inductor L3 and a second end of the fourth inductor L4 are respectively connected to a first end of at least one capacitor whose second end is grounded, and a second end of the third inductor L3 and a first end of the fourth inductor L4 are connected and commonly connected to a first end of at least one capacitor whose second end is grounded.

[0067] The third inductor L3 and the fourth inductor L4 are respectively connected to the grounded capacitor to form a two-stage L-type LC matching network. This configuration achieves impedance matching of the input signal through the combination of inductors and capacitors. The connection method of the third inductor L3 and the fourth inductor L4 ensures the stability and consistency of the signal during transmission, thereby improving the efficiency and performance of the power amplifier. Through this two-stage L-type LC matching network, the impedance matching problem in the RF power amplifier can be effectively solved to ensure efficient and stable signal transmission.

[0068] The performance parameters of each inductor and capacitor in the two-stage L-type LC matching network can be adjusted according to the frequency and power requirements in actual applications to achieve the best matching effect.

[0069] In some possible implementations, see Figure 3 , a first end of a third inductor L3 is connected to a first end of a third capacitor C3 and a first end of a fourth capacitor C4, and a second end of the third capacitor C3 and a second end of the fourth capacitor C4 are grounded;

[0070] The second end of the fourth inductor L4 is connected to the first end of a seventh capacitor C7 and the first end of an eighth capacitor C8, and the second end of the seventh capacitor C7 and the second end of the eighth capacitor C8 are grounded;

[0071] The second end of the third inductor L3 and the first end of the fourth inductor L4 are commonly connected to the first end of a fifth capacitor C5 and the first end of a sixth capacitor C6, and the second end of the fifth capacitor C5 and the second end of the sixth capacitor C6 are grounded.

[0072] Through this configuration, high-frequency noise can be effectively filtered out, the signal can be stabilized, and the input and output impedances can be matched, thereby improving the efficiency and performance of the power amplifier.

[0073] In some embodiments, see Figure 4 The bias circuit includes two first bias circuits 402 and two second bias circuits 403. The two first bias circuits 402 are respectively connected to the gates of the two power amplifier tubes 401, and the two second bias circuits 403 are respectively connected to the drains of the two power amplifier tubes 401. The sources of the two power amplifier tubes 401 are both grounded, and the drains of the two power amplifier tubes 401 are also connected to the second impedance matching module 5.

[0074] The first bias circuit 402 and the second bias circuit 403 are respectively used to provide bias voltages for the gate and drain of the power amplifier tube 401. Through this design, it is ensured that the power amplifier tube 401 can obtain a stable bias voltage when working, thereby ensuring its normal operation. The source electrodes of the two power amplifier tubes 401 are grounded, which further stabilizes the working state of the circuit. The drain is connected to the second impedance matching module 5, which ensures the effective transmission and impedance matching of the output signal of the power amplifier tube 401. These technical features work together to solve the problem of providing a stable bias voltage and achieving effective connection for the power amplifier tube, ensuring the normal operation and performance optimization of the RF power amplifier.

[0075] In a specific embodiment, the two first bias circuits 402 use a resistor voltage divider network to provide bias voltages for the gates of the two power amplifier tubes 401. The resistor voltage divider network is composed of two resistors in series, and the gate voltage can be accurately controlled by adjusting the resistance value. The two second bias circuits 403 use a voltage stabilizing circuit to provide a stable voltage for the drains of the two power amplifier tubes 401. The voltage stabilizing circuit can use a three-terminal voltage regulator or a Zener diode voltage stabilizing circuit to ensure the stability of the drain voltage. The source of the two power amplifier tubes 401 is directly grounded through a short wire, reducing the influence of parasitic inductance and resistance.

[0076] However, the structures of the first bias circuit 402 and the second bias circuit 403 are not limited thereto, and other existing technologies may also be used.

[0077] In some embodiments, see Figure 5The second impedance matching module 5 includes two first-level L-type LC matching networks with the same structure, the first ends of the two first-level L-type LC matching networks are respectively connected to the drains of the two power amplifier tubes 401, and the second ends of the two first-level L-type LC matching networks are both connected to the power synthesis module 6.

[0078] By connecting the drains of the two power amplifier tubes 401 to the first ends of the two first-stage L-type LC matching networks, the output impedance of the power amplifier tube 401 can be effectively adjusted and matched. The matched signal is then transmitted to the power synthesis module 6 through the second end of the first-stage L-type LC matching network, thereby achieving efficient power synthesis and high-quality output signals. This design solves the problem of impedance mismatch at the output end of the power amplifier tube through precise impedance matching, and improves the overall performance of the RF power amplifier.

[0079] In the first-level L-type LC matching network, the selection of the inductance and capacitance of the L-type network is crucial. The values ​​of the inductance and capacitance can be calculated and adjusted according to the output impedance and target impedance of the power amplifier tube 401. By accurately selecting the parameters of these components, the best impedance matching effect can be achieved. The first end of the first-level L-type LC matching network is connected to the drain of the power amplifier tube 401, so that the output impedance of the power amplifier tube 401 can be directly adjusted. The second end is connected to the power synthesis module 6 to ensure that the matched signal can be efficiently transmitted to the power synthesis module 6.

[0080] In actual applications, appropriate inductance and capacitance values ​​can be selected according to the specific power amplifier tube 401 model and operating frequency. For example, for certain specific frequency ranges, specific inductance and capacitance combinations can be selected to achieve the best matching effect. In addition, these parameters can be further optimized through simulation and testing to ensure the best performance under actual working conditions.

[0081] Specifically, each first-stage L-type LC matching network includes a fifth inductor L5, a first end of the fifth inductor L5 is connected to the drain of the corresponding power amplifier tube 401, and a second end of the fifth inductor L5 is connected to the first end of at least one capacitor whose second end is grounded and the power synthesis module 6.

[0082] The fifth inductor L5 is connected to the drain of the power amplifier tube 401 to play the role of impedance matching. The second end of the fifth inductor L5 is connected to the grounding capacitor and the power synthesis module 6. Through this connection mode, the output impedance of the power amplifier tube 401 can be effectively adjusted to match the impedance of the subsequent circuit, thereby improving the power transmission efficiency and signal quality. Through this design, the RF power amplifier can better process RF signals, reduce power loss, and improve overall performance.

[0083] Furthermore, the first-stage L-type LC matching network also includes a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11 and a twelfth capacitor C12, and both ends of the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12 are respectively connected to the second end of the fifth inductor L5 and the ground.

[0084] The introduction of the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12 further improves the structure of the first-level L-type LC matching network. These capacitors are connected to the second end of the fifth inductor L5 and the ground, which can better adjust and stabilize the impedance matching of the circuit, thereby improving the transmission efficiency of the RF signal and the overall performance of the power amplifier. Through the cooperation of these capacitors, the impedance matching problem can be effectively solved to ensure the efficient transmission and amplification of the RF signal.

[0085] In the first-level L-type LC matching network, the introduction of the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11 and the twelfth capacitor C12 provides a variety of possible implementations. For example, these capacitors can be arranged and combined differently according to specific circuit requirements to achieve the best impedance matching effect. The specific value of each capacitor can be adjusted according to the actual circuit parameters to achieve the best matching effect. The connection position relationship between the second end of the fifth inductor L5 and these capacitors can also be optimized according to actual needs to achieve better signal transmission effect.

[0086] The interaction between these capacitors and the fifth inductor L5 can effectively adjust the impedance matching of the circuit, thereby improving the transmission efficiency of the RF signal. This optimized design not only solves the impedance matching problem in the prior art, but also achieves more efficient signal transmission and amplification through a more sophisticated capacitor configuration. The specific capacitance and inductance values ​​can be adjusted according to the frequency and power requirements in the actual application to ensure the best circuit performance.

[0087] In some embodiments, see Figure 6 , the power synthesis module 6 includes a second resistor R2, a sixth inductor L6, a seventh inductor L7, at least one third shunt capacitor c4, at least one fourth shunt capacitor c5 and at least one second combining capacitor c6; the inductance values ​​of the sixth inductor L6 and the seventh inductor L7 are equal, and the number and capacitance values ​​of the third shunt capacitor c4 and the fourth shunt capacitor c5 are equal;

[0088] The first end of the second resistor R2, the first end of each third shunt capacitor c4 and the first end of the sixth inductor L6 are all connected to the second end of one of the first-level L-type LC matching networks, the second end of the second resistor R2, the first end of each fourth shunt capacitor c5 and the first end of the seventh inductor L7 are all connected to the second end of another first-level L-type LC matching network, the second end of the sixth inductor L6, the second end of the seventh inductor L7 and the first end of each second combining capacitor c6 are all connected to the RF output terminal 7, and the second end of each third shunt capacitor c4, the second end of each fourth shunt capacitor c5 and the second end of each second combining capacitor c6 are all grounded.

[0089] The power synthesis module 6 synthesizes the output signals of the two power amplifier tubes 401 by using a symmetrical inductor and capacitor network. The inductance values ​​of the sixth inductor L6 and the seventh inductor L7 are equal, and the number and capacitance values ​​of the third shunt capacitor c4 and the fourth shunt capacitor c5 are equal. This symmetrical design ensures the balance and stability in the signal synthesis process. The two ends of the second resistor R2 are respectively connected to the second ends of the two first-level L-type LC matching networks, which further stabilizes the signal synthesis process. Finally, the second end of the sixth inductor L6, the second end of the seventh inductor L7, and the first end of each second combining capacitor c6 are connected to the RF output terminal 7, realizing the synthesized output of the signal.

[0090] Further, the first end of the sixth inductor L6 is connected to the second end of one of the first-level L-type LC matching networks through the thirteenth capacitor C13 and the fourteenth capacitor C14 connected in parallel, and the first end of the seventh inductor L7 is connected to the second end of the other first-level L-type LC matching network through the fifteenth capacitor C15 and the sixteenth capacitor C16 connected in parallel; the capacitance values ​​of the thirteenth capacitor C13 and the fifteenth capacitor C15 are equal, and the capacitance values ​​of the fourteenth capacitor C14 and the sixteenth capacitor C16 are equal.

[0091] The functions of the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15 and the sixteenth capacitor C16 are to block the DC component from passing through while allowing the AC signal (RF signal) to pass through, thereby preventing the DC bias voltage from adversely affecting the transmission of the RF signal and ensuring the transmission quality and stability of the RF signal.

[0092] During the implementation of the present application, there is still the problem of optimizing the device parameters of the power synthesis module 6 in the RF power amplifier using VDMOS devices (mainly referring to the performance parameters of the capacitor, inductor and resistor therein) to achieve the output impedance matching of the two power amplifier tubes 401 to 50Ω, thereby improving the performance of the amplifier.

[0093] refer to Figure 7The present application provides a debugging method for optimizing the device parameters of the power synthesis module 6 in the radio frequency power amplifier using the VDMOS device mentioned above; the debugging method comprises the steps of:

[0094] A1. Measure the output impedance of the two power amplifier tubes 401;

[0095] A2. According to the measured output impedance, the device parameters of the power synthesis module 6 that can match the output impedance of the two power amplifier tubes 401 to 50Ω are obtained by simulation method, which are recorded as optimized device parameters;

[0096] A3. Based on the optimized device parameters, a real circuit of an RF power amplifier using a VDMOS device is built, and the real circuit is tested to further fine-tune the device parameters of the power synthesis module 6.

[0097] Through these steps, the device parameters of the power synthesis module 6 can be effectively optimized, so that the output impedance of the two power amplifier tubes 401 is matched to 50Ω, thereby improving the performance of the radio frequency power amplifier.

[0098] In solving the problem of optimizing the device parameters of the power synthesis module 6 in the RF power amplifier using VDMOS devices to achieve the output impedance matching of the two power amplifier tubes 401 to 50Ω, thereby improving the performance of the amplifier, each feature plays an important role. Measuring the output impedance of the power amplifier tube 401 is the basis, simulation testing is the key, and actual testing and fine-tuning are necessary steps to ensure the final effect. Compared with the prior art, the method of the present application can more accurately optimize the device parameters of the power synthesis module 6 by combining simulation and actual testing, thereby achieving better impedance matching effect and improving the performance of the RF power amplifier.

[0099] It should be noted that, in the above debugging process, in the RF power amplifier using VDMOS devices, the performance parameters of the devices except the power synthesis module 6 remain unchanged.

[0100] In step A1, the output impedance of the two power amplifier tubes 401 can be measured by using a network analyzer.

[0101] Wherein, step A2 comprises:

[0102] A201. According to the measured output impedance, determine the theoretical device parameters that can match the output impedance of the two power amplifier tubes 401 to 50Ω (the specific calculation method is prior art and will not be described in detail here);

[0103] A202. Based on the theoretical device parameters, construct a simulation circuit of an RF power amplifier using a VDMOS device;

[0104] A203. Perform simulation tests on the simulation circuit to fine-tune the device parameters of the power synthesis module 6 to obtain optimized device parameters that can match the output impedance of the two power amplifier tubes 401 to 50Ω.

[0105] Among them, simulation software such as ADS and HFSS can be used to construct and simulate circuits, and various simulation methods can be used, such as time domain simulation, frequency domain simulation, etc., to ensure the accuracy and reliability of the simulation results.

[0106] Wherein, step A3 comprises:

[0107] A301. Build several real circuits of RF power amplifiers using VDMOS devices based on optimized device parameters;

[0108] A302. The RF output terminals 7 of several real circuits are connected together to a combiner to form an RF power supply;

[0109] A303. Measure the performance parameters of the RF power supply, and fine-tune the device parameters of the power synthesis module 6 according to the performance parameters, so that the performance parameters of the RF power supply are optimal or meet the preset conditions.

[0110] Specifically, the performance parameter includes at least one of a maximum output power and an operating temperature;

[0111] The preset condition includes at least one of the maximum output power being not less than the preset power threshold and the operating temperature being not higher than the preset temperature threshold. The preset power threshold and the preset temperature threshold are set according to the specific performance of the power amplifier tube 401 and the number of real circuits; for example, when the output impedance of the power amplifier tube 401 is matched to 50Ω, the output power of a single tube is 300W (so that the theoretical output power of each real circuit is 600W), and when three real circuits are connected to a combiner to form an RF power supply, considering the transmission loss, the preset power threshold can be set to 1600W and the preset temperature threshold can be set to 60°C, but it is not limited thereto.

[0112] By building multiple real circuits and connecting their RF output terminals 7 to a combiner, a comprehensive RF power supply is formed. Then, by measuring the performance parameters of the RF power supply (such as maximum output power and operating temperature), the device parameters of the power synthesis module 6 are fine-tuned. This method can ensure that in actual applications, the performance parameters of the RF power amplifier are optimal or meet the preset conditions. In this way, the device parameters of the power synthesis module 6 can be effectively optimized, thereby improving the overall performance of the RF power amplifier.

[0113] The present application successfully solves the performance and overheating problems of the RF power amplifier at high power output by optimizing the structural parameters of the power synthesis module 6. Compared with the prior art, the technical solution of the present application has significant advantages. First, through precise measurement and simulation optimization, it is ensured that the structural parameters of the power synthesis module 6 can meet the preset conditions, thereby improving the efficiency and stability of the RF power amplifier. Secondly, through multiple iterations and experimental verification, the reliability and repeatability of the optimization results are ensured. Finally, through reasonable parameter adjustment, the optimization of the maximum output power and operating temperature is achieved, and the service life of the RF power amplifier is extended.

[0114] In a specific embodiment, the present application utilizes the above method to Figure 1 The device parameters of the power synthesis module 6 in the radio frequency power amplifier using VDMOS devices are optimized;

[0115] Among them, the two power amplifier tubes 401 are both VDMOS devices with model SD2933;

[0116] In the power division module 2, the capacitance values ​​of the first combining capacitor c1, the first branch capacitor c2 and the second branch capacitor c3 are all 82 pF, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are both 1.8 nF, the inductance values ​​of the first inductor L1 and the second inductor L2 are both 415 nH, and the resistance value of the first resistor R1 is 100 Ω;

[0117] In the first impedance matching module 3, the capacitance value of the third capacitor C3 is 100pF, the capacitance value of the fourth capacitor C4 is 68pF, the capacitance value of the fifth capacitor C5 is 120pF, the capacitance value of the sixth capacitor C6 is 240pF, the capacitance values ​​of the seventh capacitor C7 and the eighth capacitor C8 are both 100pF, the inductance value of the third inductor L3 is 47nH, and the inductance value of the fourth inductor L4 is 72nH;

[0118] In the second impedance matching module 5, the inductance value of the fifth inductor L5 is 108nH, and the capacitance values ​​of the ninth capacitor C9 to the twelfth capacitor C12 are all 220pF;

[0119] In the optimized power synthesis module 6, the resistance value of the second resistor R2 is 100Ω, the capacitance values ​​of the third shunt capacitor c4, the fourth shunt capacitor c5 and the second combining capacitor c6 are all 68 pF, the capacitance values ​​of the thirteenth capacitor C13 to the sixteenth capacitor C16 are all 4.7 nF, and the inductance values ​​of the sixth inductor L6 and the seventh inductor L7 are both 160 nH;

[0120] A DC-isolating capacitor 8 with a capacitance value of 1 nF is provided between each output end of the power division module 2 and each input end of the first impedance matching module 3, a DC-isolating capacitor 8 with a capacitance value of 33 nF is provided between each output end of the first impedance matching module 3 and the corresponding power amplifier tube 401, two DC-isolating capacitors 8 connected in parallel and with a capacitance value of 4.7 nF are provided between each input end of the second impedance matching module 5 and the corresponding power amplifier tube 401, and two DC-isolating capacitors 8 connected in parallel and with a capacitance value of 4.7 nF are provided between each output end of the second impedance matching module 5 and each input end of the power synthesis module 6;

[0121] The RF power supply is formed by using the real circuits of the three RF power amplifiers mentioned above and a combiner. It has been tested that its maximum output power exceeds 1600W and the operating temperature does not exceed 50℃.

[0122] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0123] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A radio frequency power amplifier using a VDMOS device, characterized in that: It comprises a radio frequency input end (1), a power division module (2), a first impedance matching module (3), a power amplifier module (4), a second impedance matching module (5), a power synthesis module (6) and a radio frequency output end (7) which are connected in sequence from front to back; The power division module (2) is used to divide the input radio frequency signal into two radio frequency signals with equal power; The power amplifier module (4) comprises two power amplifier tubes (401) and a bias circuit for providing an operating voltage for the power amplifier tubes (401); The first impedance matching module (3) and the second impedance matching module (5) are respectively used to achieve impedance matching at the input end and the output end of the two power amplifier tubes (401); The power synthesis module (6) is used to synthesize the two radio frequency signals output from the second impedance matching module (5) into one output radio frequency signal; The power amplifier tube (401) is a VDMOS device, and a DC isolation structure is provided between any two adjacent modules among the power division module (2), the first impedance matching module (3), the power amplifier module (4), the second impedance matching module (5) and the power synthesis module (6); The power division module (2) comprises a first inductor L1, a second inductor L2, a first resistor R1, at least one first combined capacitor c1, at least one first shunt capacitor c2 and at least one second shunt capacitor c3; the inductance values ​​of the first inductor L1 and the second inductor L2 are equal, and the number and capacitance values ​​of the first shunt capacitors c2 and the second shunt capacitors c3 are equal; The first end of the first inductor L1, the first end of the second inductor L2 and the first end of each of the first combining capacitors c1 are all connected to the RF input terminal (1); the second end of the first inductor L1, the first end of each of the first shunt capacitors c2 and the first end of the first resistor R1 are connected as an output terminal of the power division module (2); the second end of the second inductor L2, the first end of each of the second shunt capacitors c3 and the second end of the first resistor R1 are connected as a second output terminal of the power division module (2); the second end of each of the first combining capacitors c1, the second end of each of the first shunt capacitors c2 and the second end of each of the second shunt capacitors c3 are all grounded.

2. The radio frequency power amplifier using a VDMOS device according to claim 1, characterized in that: Each of the DC isolation structures comprises at least one DC isolation capacitor (8).

3. The radio frequency power amplifier using a VDMOS device according to claim 1, characterized in that: The first impedance matching module (3) comprises two two-stage L-type LC matching networks with the same structure; the first ends of the two two-stage L-type LC matching networks are respectively connected to the two output ends of the power division module (2), and the second ends of the two two-stage L-type LC matching networks are respectively connected to the gates of the two power amplifier tubes (401).

4. The radio frequency power amplifier using a VDMOS device according to claim 3, characterized in that: Each of the two-stage L-type LC matching networks includes a third inductor L3 and a fourth inductor L4, wherein a first end of the third inductor L3 and a second end of the fourth inductor L4 are respectively connected to a first end of at least one capacitor whose second end is grounded, and a second end of the third inductor L3 and a first end of the fourth inductor L4 are connected and commonly connected to a first end of at least one capacitor whose second end is grounded.

5. The radio frequency power amplifier using a VDMOS device according to claim 3, characterized in that: The bias circuit comprises two first bias circuits (402) and two second bias circuits (403); the two first bias circuits (402) are respectively connected to the gate electrodes of the two power amplifier tubes (401); the two second bias circuits (403) are respectively connected to the drain electrodes of the two power amplifier tubes (401); the source electrodes of the two power amplifier tubes (401) are both grounded; and the drain electrodes of the two power amplifier tubes (401) are also connected to the second impedance matching module (5).

6. The radio frequency power amplifier using a VDMOS device according to claim 5, characterized in that: The second impedance matching module (5) comprises two first-level L-type LC matching networks of the same structure, the first ends of the two first-level L-type LC matching networks are respectively connected to the drains of the two power amplifier tubes (401), and the second ends of the two first-level L-type LC matching networks are both connected to the power synthesis module (6).

7. The radio frequency power amplifier using a VDMOS device according to claim 6, characterized in that: Each of the first-stage L-type LC matching networks comprises a fifth inductor L5, a first end of the fifth inductor L5 being connected to the drain of the corresponding power amplifier tube (401), and a second end of the fifth inductor L5 being connected to the first end of at least one capacitor whose second end is grounded and the power synthesis module (6).

8. The radio frequency power amplifier using a VDMOS device according to claim 6, characterized in that: The power synthesis module (6) comprises a second resistor R2, a sixth inductor L6, a seventh inductor L7, at least one third shunt capacitor C4, at least one fourth shunt capacitor C5 and at least one second combining capacitor C6; The inductance values ​​of the sixth inductor L6 and the seventh inductor L7 are equal, and the number and capacitance values ​​of the third shunt capacitor C4 and the fourth shunt capacitor C5 are equal; The first end of the second resistor R2, the first end of each of the third shunt capacitors c4, and the first end of the sixth inductor L6 are all connected to the second end of one of the first-level L-type LC matching networks, the second end of the second resistor R2, the first end of each of the fourth shunt capacitors c5, and the first end of the seventh inductor L7 are all connected to the second end of another of the first-level L-type LC matching networks, the second end of the sixth inductor L6, the second end of the seventh inductor L7, and the first end of each of the second combining capacitors c6 are all connected to the RF output terminal (7), and the second end of each of the third shunt capacitors c4, the second end of each of the fourth shunt capacitors c5, and the second end of each of the second combining capacitors c6 are all grounded.

9. A debugging method, characterized in that: Used to optimize the device parameters of the power synthesis module (6) in the radio frequency power amplifier using VDMOS devices as described in any one of claims 1 to 8; the debugging method comprises the steps of: A1. Determine the output impedance of the two power amplifier tubes (401); A2. According to the measured output impedance, using a simulation method, obtain the device parameters of the power synthesis module (6) that can match the output impedance of the two power amplifier tubes (401) to 50Ω, which are recorded as optimized device parameters; A3. Based on the optimized device parameters, a real circuit of the radio frequency power amplifier using the VDMOS device is constructed, and the real circuit is tested to further fine-tune the device parameters of the power synthesis module (6).

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