Formation method of semiconductor structure

Abstract

The invention relates to a method for forming a semiconductor structure. The forming method of the semiconductor structure comprises the following steps that a substrate is provided, the substrate comprises an array area and a peripheral area, and the array area comprises a plurality of active columns which are arranged at intervals; forming a dielectric layer covering the array region and the peripheral region, an isolation layer covering the side wall and the top surface of the dielectric layer in the peripheral region, and a covering layer covering the isolation layer, wherein the width of the dielectric layer in the first direction is 40-100 nm; removing a part of the dielectric layer in the array region, and removing the covering layer in the peripheral region to expose the active columns; forming a conductive material layer covering the array region and the peripheral region; and removing part of the conductive material layer in the array region and all the conductive material layer in the peripheral region to form a conductive layer electrically connected with the active column. The manufacturing cost of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers, which includes an array area and a peripheral area outside the array area. The array area is composed of multiple storage cells, and multiple word lines and multiple bit lines electrically connected to the multiple storage cells, respectively. Each storage cell usually includes a switch element and a storage element electrically connected to the switch element. The word line voltage on the word line can control the opening and closing of the switch element, so that the data information stored in the storage element can be read through the bit line, or the data information can be written into the storage element.

[0003] In the manufacturing process of semiconductor structures such as DRAM, for example, in the process of forming word lines, it is usually necessary to use multiple layers of masks, and the alignment problem of the masks will affect the morphology and performance of structural components such as word lines. The use of too many masks will also increase the manufacturing cost of semiconductor structures and reduce the manufacturing efficiency of semiconductor structures. In addition, in the process of implementing the processing technology on the array area, due to the limitation of the processing technology, the film layer stacking at the middle position and the edge position of the array area will be unbalanced, which will easily affect the device structure at the edge position of the array area, such as making it easy for leakage problems to occur between the word lines at the edge position and the storage elements at the edge position, thereby reducing the performance of the semiconductor structure, and in severe cases, causing the semiconductor structure to be scrapped.

[0004] Therefore, how to improve the performance of semiconductor structures while reducing the manufacturing cost of semiconductor structures and improving the manufacturing yield of semiconductor structures is a technical problem that needs to be solved urgently. Summary of the invention

[0005] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, which is used to improve the performance of the semiconductor structure, reduce the manufacturing cost of the semiconductor structure, and increase the manufacturing yield of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a method for forming a semiconductor structure, comprising the following steps:

[0007] Providing a substrate, the substrate comprising an array region and a peripheral region located outside the array region along a first direction, the array region comprising a plurality of active pillars arranged at intervals, the first direction being parallel to a top surface of the substrate;

[0008] forming a dielectric layer covering the array region and the peripheral region, an isolation layer covering the sidewalls and top surface of the dielectric layer in the peripheral region, and a covering layer covering the isolation layer, wherein the width of the dielectric layer along the first direction is 40 nm to 100 nm;

[0009] Removing a portion of the dielectric layer in the array area and removing the cover layer in the peripheral area to expose the active pillars;

[0010] forming a conductive material layer covering the array region and the peripheral region;

[0011] A portion of the conductive material layer in the array region and the entire conductive material layer in the peripheral region are removed to form a conductive layer electrically connected to the active pillar.

[0012] In some embodiments, the specific steps of forming a dielectric layer covering the array region and the peripheral region, an isolation layer covering the sidewalls and top surface of the dielectric layer in the peripheral region, and a covering layer covering the isolation layer include:

[0013] Forming the active pillars covering the array region and the dielectric layer covering the peripheral region, wherein the top surface of the dielectric layer in the array region is located below the top surface of the dielectric layer in the peripheral region;

[0014] forming the isolation layer which is continuously distributed in the array region and the peripheral region and covers the surface of the dielectric layer;

[0015] forming a covering layer which is continuously distributed in the array region and the peripheral region and covers the surface of the isolation layer;

[0016] The covering layer and the isolation layer in the array area are removed, and a portion of the covering layer in the peripheral area is removed.

[0017] In some embodiments, the specific steps of forming the active pillars covering the array area and the dielectric layer covering the peripheral area include:

[0018] forming a first dielectric layer covering the surface of the active pillars in the array region and the surface of the substrate in the peripheral region;

[0019] forming a second dielectric layer covering the first dielectric layer;

[0020] A third dielectric layer covering the second dielectric layer is formed to form the dielectric layer including the first dielectric layer, the second dielectric layer and the third dielectric layer.

[0021] In some embodiments, the specific steps of removing the covering layer and the isolation layer in the array area and removing part of the covering layer in the peripheral area include:

[0022] Using a planarization process to remove all of the cover layer in the array area and to remove part of the cover layer in the peripheral area, exposing the isolation layer in the array area;

[0023] The isolation layer in the array area is removed to expose the dielectric layer in the array area.

[0024] In some embodiments, the specific steps of removing part of the dielectric layer in the array area and removing the cover layer in the peripheral area include:

[0025] A wet etching process is adopted to remove a portion of the dielectric layer in the array area and the covering layer in the peripheral area, thereby exposing the active pillars in the array area and the isolation layer in the peripheral area.

[0026] In some embodiments, the specific steps of removing part of the dielectric layer in the array area and removing the cover layer in the peripheral area include:

[0027] Part of the dielectric layer in the array area is removed, and the covering layer in the peripheral area is removed to expose the active pillars in the array area and the isolation layer in the peripheral area, and the top surface of the remaining dielectric layer in the array area is located below the top surface of the dielectric layer in the peripheral area.

[0028] In some embodiments, the peripheral region includes a first peripheral region adjacent to the array region and a second peripheral region outside the first peripheral region; the specific steps of removing a portion of the dielectric layer in the array region and removing the cover layer in the peripheral region include:

[0029] forming a photoresist layer on the substrate, wherein the photoresist layer includes an etching window exposing the array region and the first peripheral region;

[0030] A portion of the dielectric layer in the array area is removed along the etching window, and the covering layer in the first peripheral area is removed.

[0031] In some embodiments, before depositing the conductive material on the array region and the peripheral region, the method further includes the following steps:

[0032] A functional layer is formed covering the sidewalls of the active pillar.

[0033] In some embodiments, the specific steps of forming the conductive material layer covering the array region and the peripheral region include:

[0034] Conductive material is deposited in the array region and the peripheral region to form the conductive material layer, which covers the remaining surface of the dielectric layer in the array region, fills the gaps between adjacent active pillars, covers the functional layer, and covers the isolation layer in the peripheral region.

[0035] In some embodiments, the specific steps of forming a conductive layer electrically connected to the active pillar include:

[0036] Back-etch part of the conductive material layer in the array area and the entire conductive material layer in the peripheral area to expose the isolation layer in the peripheral area, and use the remaining conductive material layer in the array area as the conductive layer, the top surface of which is located below the top surface of the active column.

[0037] In some embodiments, before etching back a portion of the conductive material layer in the array area and the entire conductive material layer in the peripheral area, the following steps are further included:

[0038] The conductive material layer is planarized so that a top surface of the conductive material layer in the array region is flush with a top surface of the conductive material layer in the peripheral region.

[0039] In some embodiments, the peripheral region is located outside the array region along a first direction, the isolation layer of the peripheral region includes a first portion extending along a second direction, and a second portion connected to the first portion and extending along the first direction, the first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate;

[0040] The top surface of the conductive layer is flush with the top surface of the second portion; or, the top surface of the conductive layer is located below the top surface of the second portion.

[0041] In some embodiments, after removing part of the conductive material layer in the array area and all of the conductive material layer in the peripheral area, the method further includes the following steps:

[0042] A spacer layer is formed covering the conductive layer, the active pillar and the isolation layer.

[0043] In some embodiments, the active pillar includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a second direction, and the second direction is perpendicular to the top surface of the substrate;

[0044] The conductive layer is a word line covering the channel region.

[0045] In the method for forming a semiconductor structure provided by some embodiments of the present disclosure, in the process of exposing the active pillar, it is not necessary to use a mask covering the covering layer of the peripheral area, but to remove part of the dielectric layer of the array area and the covering layer of the peripheral area, thereby reducing the number of masks required in the manufacturing process of the semiconductor structure, thereby reducing the manufacturing cost of the semiconductor structure. At the same time, in the process of removing part of the dielectric layer of the array area, some embodiments of the present disclosure remove the covering layer of the peripheral area, and deposit the conductive material layer in the array area and the peripheral area at the same time. When the conductive layer is subsequently formed, part of the conductive material layer of the array area and all the conductive material layers of the peripheral area are removed, thereby avoiding the residue of the conductive material layer in the peripheral area, improving the electrical isolation effect between the conductive layer and the peripheral area, and thus improving the performance of the semiconductor structure. Moreover, in some embodiments of the present disclosure, the thickness of the dielectric layer is limited to the range of 40nm to 100nm, that is, the position of the conductive layer formed after back etching can be lower than the isolation layer, thereby further improving the electrical isolation effect between the conductive layer and the peripheral area, and will not cause a significant increase in the size of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Attached Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0047] Attached Figure 2 -Attached Fig.15 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The specific implementation of the method for forming a semiconductor structure provided by the present disclosure is described in detail below with reference to the accompanying drawings.

[0049] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure, Figure 2 -Attached Fig.15 Schematic diagram of the main process structure in the process of forming a semiconductor structure in the specific embodiment of the present disclosure. Figure 1-Figure 15 As shown, the method for forming the semiconductor structure comprises the following steps:

[0050] Step S11, providing a substrate 15, wherein the substrate 15 includes an array region 13 and a peripheral region 14 located outside the array region 13 along a first direction, wherein the array region 13 includes a plurality of active pillars 30 arranged at intervals, and the first direction is parallel to a top surface of the substrate 15;

[0051] Step S12, forming a dielectric layer 40 covering the array region 13 and the peripheral region 14, an isolation layer 41 covering the sidewalls and top surface of the dielectric layer 40 in the peripheral region 14, and a covering layer 42 covering the isolation layer 41, wherein a width D of the dielectric layer along the first direction is 40 nm to 100 nm;

[0052] Step S13, removing part of the dielectric layer 40 in the array area 13 and removing the cover layer 42 in the peripheral area 14 to expose the active pillars 30;

[0053] Step S14, forming a conductive material layer 130 covering the array region 13 and the peripheral region 14;

[0054] Step S15 , removing part of the conductive material layer 130 in the array region 13 and all of the conductive material layer 130 in the peripheral region 14 to form a conductive layer 140 electrically connected to the active pillar 30 .

[0055] In some embodiments, the specific steps of forming the dielectric layer 40 covering the array region 13 and the peripheral region 14, the isolation layer 41 covering the sidewalls and top surface of the dielectric layer 40 in the peripheral region 14, and the covering layer 42 covering the isolation layer 41 include:

[0056] Forming the active pillars 30 covering the array region 13 and the dielectric layer 40 covering the peripheral region 14, wherein the top surface of the dielectric layer 40 in the array region 13 is located below the top surface of the dielectric layer 40 in the peripheral region 14;

[0057] forming the isolation layer 41 which is continuously distributed in the array region 13 and the peripheral region 14 and covers the surface of the dielectric layer 40;

[0058] forming a covering layer 42 which is continuously distributed in the array region 13 and the peripheral region 14 and covers the surface of the isolation layer 41;

[0059] The cover layer 42 and the isolation layer 41 of the array region 13 are removed, and part of the cover layer 42 of the peripheral region 14 is removed. Figure 4 shown. Figure 2 is a schematic top view of a semiconductor structure formed in this specific embodiment, Figure 4 yes Figure 2 The cross-sectional schematic diagram at position aa after the covering layer 42 is formed.

[0060] In some embodiments, the specific steps of forming the active pillars 30 covering the array region 13 and the dielectric layer 40 covering the peripheral region 14 include:

[0061] forming a first dielectric layer covering the surface of the active pillars 30 in the array region 13 and the surface of the substrate 15 in the peripheral region 14;

[0062] forming a second dielectric layer covering the first dielectric layer;

[0063] A third dielectric layer covering the second dielectric layer is formed to form the dielectric layer 40 including the first dielectric layer, the second dielectric layer and the third dielectric layer.

[0064] The semiconductor structure described in this specific embodiment can be but is not limited to DRAM. This specific embodiment takes the semiconductor structure being DRAM as an example for explanation. The substrate 15 can be but is not limited to a silicon substrate. This specific embodiment takes the substrate 15 being a silicon substrate as an example for explanation. In other embodiments, the substrate 20 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The substrate 15 and the active pillars 30 on the substrate 15 can be formed by the following method: first, an initial substrate is formed; then, a first mask layer 32 is formed on the initial substrate, and the first mask layer 32 has an opening exposing the initial substrate; then, the initial substrate is etched along the opening to form a plurality of first grooves 31 extending along the first direction D1 and the third direction D3, and the plurality of first grooves 31 separate the initial substrate into a plurality of active pillars 30 arranged in a two-dimensional array along the first direction D1 and the third direction D3. The remaining initial substrate below the active pillars 30 serves as the substrate 15, such as Figure 2 and Figure 3 As shown. Among them, Figure 3 yes Figure 2 FIG. 1 is a schematic cross-sectional view of aa position in FIG. 1 after forming the active pillar 30. In an example, the depth of the first trench 31 along the second direction D2 may be In one example, the first direction D1 and the third direction D3 are both parallel to the top surface of the substrate 15, and the first direction D1 intersects with the third direction D3 (for example, perpendicularly or obliquely), and the second direction D2 is perpendicular to the top surface of the substrate 15. The top surface of the substrate 15 refers to the surface of the substrate 15 facing the active pillar 30.

[0065] After forming the active pillars 30, a first dielectric layer covering the surface of the active pillars 30 in the array region 13 and the surface of the substrate 15 exposed in the peripheral region 14 can be formed by in-situ water vapor growth (ISSG) or the like. In one example, the thickness of the first dielectric layer (e.g., the width of the first dielectric layer along the first direction D1) is 1nm to 5nm (e.g., 4nm). Next, a dielectric material such as silicon dioxide can be deposited in the array region 13 and the peripheral region 14 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the second dielectric layer that at least fills the first trench 31 between adjacent active pillars 30 and covers the first dielectric layer. In one example, the thickness of the second dielectric layer (e.g., the width of the second dielectric layer along the first direction D1) is 1nm to 5nm (e.g., 3.5nm). Afterwards, the third dielectric layer covering the second dielectric layer can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition again. In one example, the thickness of the third dielectric layer (e.g., the width of the third dielectric layer along the first direction D1) is 35 nm to 95 nm (e.g., 35 nm, 50 nm, 65 nm, 80 nm, 85 nm, or 90 nm). The first dielectric layer, the second dielectric layer, and the third dielectric layer together constitute the dielectric layer 40. In one example, the material of the first dielectric layer, the material of the second dielectric layer, and the material of the third dielectric layer are all the same (e.g., all are silicon dioxide), thereby simplifying subsequent processes and further reducing the manufacturing cost of the semiconductor structure.

[0066] Since the array region 13 includes a plurality of active pillars 30, along the second direction D2, the top surface of the active pillars 30 in the array region 13 is located above the top surface of the substrate 15 in the peripheral region 14, so that the dielectric layer 40 is stepped, and the height of the dielectric layer 40 in the array region 13 along the second direction D2 is higher than the height of the dielectric layer 40 in the peripheral region 14 along the second direction D2, that is, the top surface of the dielectric layer 40 in the array region 13 is higher than the top surface of the dielectric layer 40 in the peripheral region 14. Afterwards, after the isolation layer 41 is formed on the surface of the dielectric layer 40 by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, the isolation layer 41 is also stepped. In one example, the material of the isolation layer 41 may be a nitride material, such as silicon nitride. Next, the cover layer 42 covering the isolation layer 41 is formed, and a planarization process such as chemical mechanical polishing (CMP) is performed to make the top surface of the cover layer 42 flat. Figure 4In one example, the material of the cover layer 42 may be an oxide material, such as silicon dioxide. In one example, the thickness of the isolation layer 41 may be (For example ). The thickness of the covering layer can be (For example ).

[0067] In this specific embodiment, the thickness of the third dielectric layer can be adjusted to make the width of the dielectric layer 40 as a whole along the first direction D1 within the range of 40nm to 100nm, so that when the conductive material layer is subsequently etched back to form the conductive layer, the conductive layer position closest to the isolation layer 41 is lower than the isolation layer 41 along the second direction D2. With this structure, on the one hand, the distance between the active pillar 30 located at the edge of the array region 13 and the conductive structure (such as the lead structure, CMOS circuit structure) located in the peripheral region 14 can be increased, reducing the leakage problem between the array region 13 and the peripheral region 14, thereby improving the performance of the semiconductor structure; on the other hand, the distance between the conductive layer formed subsequently and the conductive structure located in the peripheral region 14 can also be increased, thereby reducing the leakage inside the semiconductor structure.

[0068] In some embodiments, the specific steps of removing the cover layer 42 and the isolation layer 41 in the array area 13 and removing part of the cover layer 42 in the peripheral area 14 include:

[0069] Using a planarization process to remove all of the cover layer 42 in the array region 13 and to remove part of the cover layer 42 in the peripheral region 14 , exposing the isolation layer 41 in the array region 13 ;

[0070] The isolation layer 41 in the array region 13 is removed to expose the dielectric layer 40 in the array region 13 .

[0071] In some embodiments, the specific steps of removing a portion of the dielectric layer 40 in the array area 13 and removing the cover layer 42 in the peripheral area 14 include:

[0072] A wet etching process is adopted to remove part of the dielectric layer 40 in the array region 13 and remove the cover layer 42 in the peripheral region 14 , thereby exposing the active pillars 30 in the array region 13 and the isolation layer 41 in the peripheral region 14 .

[0073] In some embodiments, the specific steps of removing a portion of the dielectric layer 40 in the array area 13 and removing the cover layer 42 in the peripheral area 14 include:

[0074] Part of the dielectric layer 40 in the array area 13 is removed, and the covering layer 42 in the peripheral area 14 is removed to expose the active pillars 30 in the array area 13 and the isolation layer 41 in the peripheral area 14, and the top surface of the remaining dielectric layer 40 in the array area 13 is located below the top surface of the dielectric layer 40 in the peripheral area 14.

[0075] In some embodiments, the peripheral region 14 includes a first peripheral region 141 adjacent to the array region 13, and a second peripheral region 142 located outside the first peripheral region 141; the specific steps of removing part of the dielectric layer 40 of the array region 13 and removing the cover layer 42 of the peripheral region 14 include:

[0076] forming a photoresist layer 72 on the substrate 15, wherein the photoresist layer 72 includes an etching window exposing the array region 13 and the first peripheral region 141;

[0077] A portion of the dielectric layer 40 in the array region 13 is removed along the etching window, and the cover layer 42 in the first peripheral region 141 is removed.

[0078] Specifically, the peripheral region 14 includes the first peripheral region 141 adjacent to the array region 13, and the second peripheral region 142 away from the array region 13 and adjacent to the first peripheral region 141. Figure 2As shown. In one example, the semiconductor structure further includes a plurality of bit lines 11 extending along the first direction D1 and arranged at intervals along the third direction D3, and a plurality of word lines 12 extending along the third direction D3 and arranged at intervals along the first direction D1, the bit lines 11 are electrically connected to the plurality of active pillars 30 arranged at intervals along the first direction D1, and the word lines 12 are electrically connected to the plurality of active pillars 30 arranged at intervals along the third direction D3. The word lines 12 and the bit lines 11 extend from the array region 13 to the first peripheral region 141, that is, the ends of the word lines 12 and the bit lines 11 are located in the first peripheral region 141. The first peripheral region 141 further includes a word line lead for leading out or leading in a signal of the word line 12, and a bit line lead for leading out or leading in a signal of the bit line 11. The second peripheral region 142 is used to form a control circuit (e.g., a CMOS circuit), and the control circuit transmits a control signal to the bit line lead and the word line lead through a bridge circuit located in the peripheral region 14. In one example, the second peripheral region 142 includes a peripheral active pillar 73 located on the substrate 15, and a peripheral isolation layer 80 covering the surface of the peripheral active pillar 73. Figure 7 As shown. Among them, Figure 7 yes Figure 2 The cross-sectional view of the position ee in the figure is before the dielectric layer 40 is formed. Subsequently, the dielectric layer 40, the isolation layer 41 and the cover layer 42 are simultaneously formed in the array region 13, the first peripheral region 141 and the second peripheral region 142. Figure 8 As shown. Among them, Figure 8 yes Figure 2 A schematic cross-sectional view at the ee position after the cover layer 42 is formed.

[0079] Afterwards, the isolation layer 41 can be used as a grinding stop layer, and a planarization process such as chemical mechanical polishing can be used to remove part of the cover layer 42, exposing the isolation layer 41 in the array region 13 and the isolation layer 41 in the second peripheral region 142, and making the top surface of the isolation layer 41 remaining in the array region 13 after the planarization process flush with the top surface of the cover layer 42 remaining in the peripheral region 14 (including the first peripheral region 141 and the second peripheral region 142), as shown in FIG. Figure 5 and 9 As shown. Among them, Figure 5 yes Figure 2 The cross-sectional view at position aa in the figure is a schematic diagram of the cover layer 42 after the planarization process. Fig. 9 yes Figure 2ee position in the middle is a schematic cross-sectional view after the cover layer 42 is planarized. Next, a stripping process may be used to remove the isolation layer 41 exposed in the array region 13 and the isolation layer 41 exposed in the second peripheral region 142 to expose the dielectric layer 40 in the array region 13. Figure 6 and Fig.10 As shown. Among them, Figure 6 yes Figure 2 The cross-sectional view at position aa in the figure is a schematic diagram after the isolation layer 41 is peeled off and exposed. Fig.10 yes Figure 2 A schematic cross-sectional view of the ee position in the middle after the isolation layer 41 is peeled off and exposed.

[0080] In order to protect the isolation structure such as the peripheral isolation layer 80 in the second peripheral region 142 and avoid damaging the second peripheral region 142, before etching back the dielectric layer 40, a second mask layer 70, a third mask layer 71 located above the second mask layer 70, and a photoresist layer 72 located above the third mask layer 71 may be formed above the array region 13 and the peripheral region 14. The photoresist layer 72 is patterned by a mask to form the etching window exposing the array region 13 and the first peripheral region 141, such as Fig.11 shown. Fig.11 They are shown respectively Figure 2 Schematic cross-sectional view of the positions aa and ee in FIG. 7 after the patterned photoresist layer 72 is formed. The third mask layer 71 and the second mask layer 70 are etched downward along the etching window to expose the dielectric layer 40 in the array region 13 and the cover layer 42 in the first peripheral region 141. Afterwards, a wet etching process can be used to back-etch away a portion of the dielectric layer in the array region 13 and all of the cover layer 42 in the first peripheral region 141 along the etching window. After removing the photoresist layer 72, the second mask layer 70 and the third mask layer 71, the following is obtained: Fig.12 The structure shown. Fig.12 They are shown respectively Figure 2 Schematic cross-sectional view of the positions aa and ee after removing the photoresist layer 72, the second mask layer 70 and the third mask layer 71. In one example, the etching parameters (such as etching time, etchant dosage, etc.) of the wet etching process can be adjusted so that the top surface of the dielectric layer 40 remaining in the array region 13 is lower than the top surface of the dielectric layer 40 in the first peripheral region 141, so as to control the depth of the conductive layer 140 formed subsequently.

[0081] In some embodiments, before depositing the conductive material on the array region 13 and the peripheral region 14, the following steps are further included:

[0082] A functional layer 131 is formed to cover the sidewalls of the active pillar 30. In one example, the functional layer 131 may be an oxide layer (eg, a silicon dioxide layer) formed by a deposition process or an in-situ water vapor growth process, and may subsequently serve as a gate dielectric layer.

[0083] In some embodiments, the specific steps of forming the conductive material layer 130 covering the array region 13 and the peripheral region 14 include:

[0084] Conductive material is deposited on the array region 13 and the peripheral region 14 to form the conductive material layer 130, wherein the conductive material layer 130 covers the remaining surface of the dielectric layer 40 in the array region 13, fills the gaps between adjacent active pillars 30, covers the functional layer 131, and covers the isolation layer 41 in the peripheral region 14. Fig.13 shown.

[0085] In some embodiments, the specific steps of forming the conductive layer 140 electrically connected to the active pillar 30 include:

[0086] Part of the conductive material layer 130 in the array area 13 and the entire conductive material layer 130 in the peripheral area 14 are etched back to expose the isolation layer 41 in the peripheral area 14, and the remaining conductive material layer 130 in the array area 13 is used as the conductive layer 140, and the top surface of the conductive layer 140 is located below the top surface of the active pillar 30.

[0087] In some embodiments, before etching back a portion of the conductive material layer 130 in the array region 13 and the entire conductive material layer 130 in the peripheral region 14, the following steps are further included:

[0088] The conductive material layer 130 is planarized so that a top surface of the conductive material layer 130 in the array region 13 is flush with a top surface of the conductive material layer 130 in the peripheral region 14 .

[0089] For example, during the deposition of the conductive material, the same mask as that used in etching back the dielectric layer 40 in the array region 13 may be used to further reduce the manufacturing cost of the semiconductor structure. A conductive material such as TiN or metal tungsten may be deposited in the array region 13 and the first peripheral region 141 using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process to form the conductive material layer 130. Next, a planarization process such as chemical mechanical polishing may be used to process the conductive material layer 130 so that the top surface of the conductive material layer 130 remaining in the array region 13 is flush with the top surface of the conductive material layer 130 remaining in the first peripheral region 141. Afterwards, the same photomask as that used in back-etching the dielectric layer 40 in the array region 13 can be used to back-etch away all of the conductive material layer 130 in the first peripheral region 141 and part of the conductive material layer 130 in the array region 13, for example, all of the conductive material layer 130 covering the surface of the isolation layer 41 is removed, thereby exposing the entire surface of the isolation layer 41 in the first peripheral region 141, that is, allowing the remaining conductive material layer 130 in the array region 13 to cover the channel region in the active pillar to form the conductive layer 140, and in the second direction D2, the position of the entire isolation layer 41 is higher than the conductive layer 140, as shown in FIG. Fig.14 shown.

[0090] Since the first peripheral region 141 is not shielded during the process of etching back the dielectric layer 40 in this specific embodiment, that is, there is no need to use a photoresist layer or a mask layer to cover the first peripheral region 141 during the process of etching back the dielectric layer 40, it is helpful to reduce the manufacturing cost of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure. At the same time, during the process of etching back the conductive material layer 130 in the array region 13 in this specific embodiment, the conductive material layer 130 in the first peripheral region 141 is removed synchronously, thereby reducing or even avoiding the residual conductive material layer 130 in the first peripheral region 141, so as to further improve the performance of the semiconductor structure. In addition, before back-etching the conductive material layer 130, the present specific embodiment performs a planarization treatment on the conductive material layer 130 so that the top surface of the conductive material layer 130 remaining in the array area 13 is flush with the top surface of the conductive material layer 130 remaining in the first peripheral area 141, thereby helping to control the etching amount of the conductive material layer 130 during the back-etching process. While ensuring that the conductive material layer 130 in the first peripheral area 141 is fully removed, the height of the conductive material layer 130 remaining in the array area 13 can be accurately controlled, thereby improving the controllability of the semiconductor structure process technology.

[0091] In some embodiments, the peripheral region 14 is located outside the array region 13 along the first direction D1, and the isolation layer 41 of the peripheral region 14 includes a first portion 411 extending along a second direction D2, and a second portion 412 connected to the first portion 411 and extending along the first direction D1, the first direction D1 is parallel to the top surface of the substrate 15, and the second direction D2 is perpendicular to the top surface of the substrate;

[0092] The top surface of the conductive layer 140 is flush with the top surface of the second part 412, thereby ensuring the electrical performance stability of the conductive layer 140 closest to the isolation layer 41; or, the top surface of the conductive layer 140 is located below the top surface of the second part 412, so as to further ensure that the conductive material layer 130 in the first peripheral area 141 can be fully removed, so as to further avoid the conductive material layer 130 remaining in the first peripheral area 141.

[0093] For example, during the deposition of the conductive material layer 130, the width of the conductive material layer 130 along the first direction D1 can be made equal to the width of the dielectric layer 40 formed in step S12 along the first direction D1, so that when the conductive material layer 130 is subsequently etched back, the conductive material layer 130 on the surface of the isolation layer 41 is completely removed, and the top surface of the formed conductive layer 140 is flush with the top surface of the second portion 412 of the isolation layer 41.

[0094] In some embodiments, after removing part of the conductive material layer 130 in the array region 13 and all of the conductive material layer 130 in the peripheral region 14, the following steps are further included:

[0095] A spacer layer 150 is formed covering the conductive layer 140, the active pillar 30 and the isolation layer 41. Fig.15 As shown, Fig.15 Implementation Figure 2 A schematic cross-sectional view of the position aa in FIG. 1 after forming the spacer layer 150. In one example, the material of the spacer layer 150 is an oxide material, such as silicon dioxide.

[0096] In some embodiments, the active pillar 30 includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a second direction D2, and the second direction D2 is perpendicular to the top surface of the substrate 15;

[0097] The conductive layer 140 is a word line covering the channel region.

[0098] In the method for forming a semiconductor structure provided in some embodiments of the present specific implementation, in the process of exposing the active pillar, there is no need to use a mask covering the covering layer of the peripheral area, but to remove part of the dielectric layer in the array area and the covering layer in the peripheral area, thereby reducing the number of masks required in the manufacturing process of the semiconductor structure, thereby reducing the manufacturing cost of the semiconductor structure. At the same time, in some embodiments of the present specific implementation, in the process of removing part of the dielectric layer in the array area, the covering layer in the peripheral area is removed, and the conductive material layer is deposited in the array area and the peripheral area at the same time. When the conductive layer is subsequently formed, part of the conductive material layer in the array area and all the conductive material layers in the peripheral area are removed, thereby avoiding the residue of the conductive material layer in the peripheral area, improving the electrical isolation effect between the conductive layer and the peripheral area, and thus improving the performance of the semiconductor structure. Moreover, in some embodiments of the present specific implementation, the thickness of the dielectric layer is limited to the range of 40nm to 100nm, that is, the position of the conductive layer formed after back etching can be lower than the isolation layer, thereby further improving the electrical isolation effect between the conductive layer and the peripheral area, and will not cause a significant increase in the size of the semiconductor structure.

[0099] The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: The steps include: Providing a substrate, the substrate comprising an array region and a peripheral region located outside the array region along a first direction, the array region comprising a plurality of active pillars arranged at intervals, the first direction being parallel to a top surface of the substrate; forming a dielectric layer covering the array region and the peripheral region, an isolation layer covering the sidewalls and top surface of the dielectric layer in the peripheral region, and a covering layer covering the isolation layer, wherein the width of the dielectric layer along the first direction is 40 nm to 100 nm; Removing a portion of the dielectric layer in the array area and removing the cover layer in the peripheral area to expose the active pillars; forming a conductive material layer covering the array region and the peripheral region; A portion of the conductive material layer in the array region and the entire conductive material layer in the peripheral region are removed to form a conductive layer electrically connected to the active pillar.

2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a dielectric layer covering the array region and the peripheral region, an isolation layer covering the sidewalls and top surface of the dielectric layer in the peripheral region, and a covering layer covering the isolation layer include: Forming the active pillars covering the array region and the dielectric layer covering the peripheral region, wherein the top surface of the dielectric layer in the array region is located below the top surface of the dielectric layer in the peripheral region; forming the isolation layer which is continuously distributed in the array region and the peripheral region and covers the surface of the dielectric layer; forming a covering layer which is continuously distributed in the array region and the peripheral region and covers the surface of the isolation layer; The covering layer and the isolation layer in the array area are removed, and a portion of the covering layer in the peripheral area is removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: The specific steps of forming the active pillars covering the array area and the dielectric layer covering the peripheral area include: forming a first dielectric layer covering the surface of the active pillars in the array region and the surface of the substrate in the peripheral region; forming a second dielectric layer covering the first dielectric layer; A third dielectric layer covering the second dielectric layer is formed to form the dielectric layer including the first dielectric layer, the second dielectric layer and the third dielectric layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: The specific steps of removing the covering layer and the isolation layer in the array area and removing part of the covering layer in the peripheral area include: Using a planarization process to remove all of the cover layer in the array area and to remove part of the cover layer in the peripheral area, exposing the isolation layer in the array area; The isolation layer in the array area is removed to expose the dielectric layer in the array area.

5. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of removing part of the dielectric layer in the array area and removing the cover layer in the peripheral area include: A wet etching process is adopted to remove a portion of the dielectric layer in the array area and the covering layer in the peripheral area, thereby exposing the active pillars in the array area and the isolation layer in the peripheral area.

6. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of removing part of the dielectric layer in the array area and removing the cover layer in the peripheral area include: Part of the dielectric layer in the array area is removed, and the covering layer in the peripheral area is removed to expose the active pillars in the array area and the isolation layer in the peripheral area, and the top surface of the remaining dielectric layer in the array area is located below the top surface of the dielectric layer in the peripheral area.

7. The method for forming a semiconductor structure according to claim 1, wherein: The peripheral region includes a first peripheral region adjacent to the array region, and a second peripheral region outside the first peripheral region; The specific steps of removing part of the dielectric layer in the array area and removing the cover layer in the peripheral area include: forming a photoresist layer on the substrate, wherein the photoresist layer includes an etching window exposing the array region and the first peripheral region; A portion of the dielectric layer in the array area is removed along the etching window, and the covering layer in the first peripheral area is removed.

8. The method for forming a semiconductor structure according to claim 1, wherein: Before depositing the conductive material on the array area and the peripheral area, the method further includes the following steps: A functional layer is formed covering the sidewalls of the active pillar.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The specific steps of forming a conductive material layer covering the array area and the peripheral area include: Conductive material is deposited in the array region and the peripheral region to form the conductive material layer, which covers the remaining surface of the dielectric layer in the array region, fills the gaps between adjacent active pillars, covers the functional layer, and covers the isolation layer in the peripheral region.

10. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming a conductive layer electrically connected to the active pillar include: Back-etch part of the conductive material layer in the array area and the entire conductive material layer in the peripheral area to expose the isolation layer in the peripheral area, and use the remaining conductive material layer in the array area as the conductive layer, the top surface of which is located below the top surface of the active column.

11. The method for forming a semiconductor structure according to claim 1, wherein: Before etching back part of the conductive material layer in the array area and all of the conductive material layer in the peripheral area, the following steps are also included: The conductive material layer is planarized so that a top surface of the conductive material layer in the array region is flush with a top surface of the conductive material layer in the peripheral region.

12. The method for forming a semiconductor structure according to claim 1, wherein: The peripheral region is located outside the array region along a first direction, the isolation layer of the peripheral region includes a first portion extending along a second direction, and a second portion connected to the first portion and extending along the first direction, the first direction is parallel to the top surface of the substrate, and the second direction is perpendicular to the top surface of the substrate; The top surface of the conductive layer is flush with the top surface of the second portion; Alternatively, a top surface of the conductive layer is located below a top surface of the second portion.

13. The method for forming a semiconductor structure according to claim 1, wherein: After removing part of the conductive material layer in the array area and all of the conductive material layer in the peripheral area, the method further includes the following steps: A spacer layer is formed covering the conductive layer, the active pillar and the isolation layer.

14. The method for forming a semiconductor structure according to claim 1, wherein: The active pillar includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along a second direction, wherein the second direction is perpendicular to the top surface of the substrate; The conductive layer is a word line covering the channel region.

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