Random access memory structure and manufacturing method thereof

Abstract

The invention provides a random access memory structure and a manufacturing method thereof. The device comprises a substrate which comprises an array region and a logic region which are adjacently arranged, the substrate is provided with a step structure, and the step structure is provided with a first step surface corresponding to the array region and a second step surface corresponding to the logic region; the first conductive channel extends from the first step surface to the first metal wiring layer in the array region; the second conductive channel extends from the second step surface to the second metal wiring layer in the logic region; the random access memory unit is arranged on the first step surface and is in contact with the first conductive channel; and the top metal layer is at least in contact with one side, far away from the first conductive channel, of the random access memory unit. According to the random access memory structure, the number of photomasks is reduced, the technological process is simplified, and therefore the manufacturing cost of the random access memory structure is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a random access memory structure and a manufacturing method thereof. Background Art

[0002] The MRAM memory storage unit MTJ is usually composed of three basic units: a ferromagnetic layer, an insulating tunneling layer, and a fixed layer. When the magnetic moment directions of the ferromagnetic layer and the fixed layer are opposite, the memory device exhibits a high resistance state Rap. When the magnetic moment directions of the two layers are the same, it exhibits a low resistance state Rp. By distinguishing between high and low resistance states, the storage of information "1" and "0" is achieved. As a new type of memory, MRAM has great advantages over traditional Flash storage in terms of read and write speed and device reliability. However, the main disadvantages of existing technologies that restrict the development of MRAM are low array density and high manufacturing costs.

[0003] Therefore, it is necessary to reduce the number of process steps by optimizing the process integration solution, thereby further reducing the manufacturing cost. Summary of the invention

[0004] The main purpose of the present invention is to provide a random access memory structure and a manufacturing method thereof, so as to solve the problem of high manufacturing cost of forming a random access memory structure in the prior art.

[0005] To achieve the above-mentioned object, according to one aspect of the present invention, there is provided a random access memory structure, comprising: a substrate, the substrate comprising an array area and a logic area adjacently arranged, the substrate having a step structure, the step structure having a first step surface corresponding to the array area and a second step surface corresponding to the logic area; a first conductive path, the first conductive path extending from the first step surface to a first metal wiring layer in the array area; a second conductive path extending from the second step surface to a second metal wiring layer in the logic area; a random access memory unit, the random access memory unit being arranged on the first step surface and in contact with the first conductive path; and a top metal layer, the top metal layer being in contact with at least one side of the random access memory unit away from the first conductive path.

[0006] Furthermore, it also includes: a top metal layer is arranged in contact with a side of the random access memory unit away from the first conductive channel and the second conductive channel respectively.

[0007] Furthermore, it also includes: a blocking layer, which is respectively arranged in contact with the random access memory unit and the first conductive channel.

[0008] Furthermore, the random access memory cell includes any one of a magnetic random access memory cell, a phase change random access memory cell and a resistive random access memory cell.

[0009] To achieve the above-mentioned object, according to one aspect of the present invention, a method for manufacturing a random access memory structure is provided, the manufacturing method comprising: providing a substrate, the substrate comprising an array area and a logic area adjacently arranged, and having a first conductive channel in the array area, having a second conductive channel in the logic area, and the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step; etching at least a portion of the substrate corresponding to the array area to form a step structure in the substrate, the step structure having a first step surface corresponding to the array area and a second step surface corresponding to the logic area, and the first conductive channel extends from the first step surface to a first metal wiring layer in the array area, and the second conductive channel extends from the second step surface to a second metal wiring layer in the logic area; forming a random access memory unit on the first step surface, the random access memory unit being arranged in contact with the first conductive channel; and forming a first metal layer arranged in contact with at least one side of the random access memory unit away from the first conductive channel.

[0010] Furthermore, the step of forming the step structure includes: setting a first mask plate on the above-mentioned substrate, the first mask plate having a hollow area, and the hollow area is at least set corresponding to the array area; etching the substrate corresponding to the hollow area to remove part of the substrate corresponding to the array area to form a step structure.

[0011] Furthermore, the method further includes: forming a second metal layer which is respectively arranged in contact with a side of the random access memory unit away from the first conductive channel and the second conductive channel.

[0012] Furthermore, the step of forming a random access memory unit includes: forming a random access memory unit film layer on at least the first step surface; setting a second mask plate on the random access memory unit film layer, the second mask plate having a preset pattern and exposing at least the remaining portion of the random access memory unit film layer except for the corresponding preset pattern; etching the random access memory unit film layer according to the preset pattern sequence to remove the exposed random access memory unit film layer to form a random access memory unit.

[0013] Furthermore, after the step of forming the step structure and before the step of forming the random access memory unit, the manufacturing method also includes: forming a blocking material layer on the first step surface and the second step surface; in the step of forming the random access memory unit, forming a random access memory unit film layer on the side of the blocking material layer away from the first conductive channel, and sequentially etching the random access memory unit film layer to form the random access memory unit and the blocking layer.

[0014] Furthermore, after the step of forming the barrier material layer and before the step of forming the random access memory unit and the barrier layer, the step of forming the random access memory unit film layer includes: forming a lower electrode material layer covering the barrier material layer; removing part of the lower electrode material layer by chemical mechanical polishing so that the remaining lower electrode material layer located in the array area has a first thickness in the first direction; thinning the remaining lower electrode material layer located in the array area so that the lower electrode material layer after thinning has a second thickness in the first direction, and the first thickness is greater than the second thickness; forming an intermediate material layer covering at least the thinned lower electrode material layer and an upper electrode material layer covering the intermediate material layer, and the thinned lower electrode material layer, the intermediate material layer and the upper electrode material layer form the random access memory unit film layer.

[0015] The technical solution of the present invention is applied to provide a random access memory structure. Since the substrate of the random access memory structure includes an array area and a logic area arranged adjacent to each other, and the substrate has a step structure, the step structure can have a first step surface corresponding to the array area and a second step surface corresponding to the logic area. Furthermore, since the substrate also has a first conductive channel and a second conductive channel, wherein the first conductive channel is located in the array area, and the second conductive channel is located in the logic area, and the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step, and the substrate also has a first metal wiring layer located in the array area and a second metal wiring layer located in the logic area correspondingly arranged, when the array area and the logic area correspond to the step structure, the first conductive channel extends from the first step surface to the first metal wiring layer in the array area, and the second conductive channel extends from the second step surface to the second metal wiring layer in the logic area, and then a random access memory unit contacting with the first conductive channel can be arranged on the first step surface, and at least a top metal layer contacting with the random access memory unit is arranged. That is, the present application can realize the formation of the first conductive channel and the second conductive channel located in the random access memory unit in the same step. Compared with the prior art that needs to form the bottom through hole corresponding to the first conductive channel and the top through hole corresponding to the second conductive channel through different etching steps, the present application reduces the number of etching masks, thereby greatly reducing the production cost of the random access memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 A cross-sectional structural schematic diagram of a random access memory structure according to an embodiment of the present application is shown;

[0018] Figure 2 A schematic cross-sectional structure diagram of a substrate provided in a random access memory structure according to an embodiment of the present invention is shown;

[0019] Figure 3 Shown in Figure 2 A schematic cross-sectional structure diagram of a step structure formed in a substrate shown;

[0020] Figure 4 Shown in Figure 3 A schematic cross-sectional structure diagram of a lower electrode material layer, a random access memory unit film layer and an upper electrode material layer is formed on the structure shown;

[0021] Figure 5 Shows the etching Figure 4 The structure shown forms a random access memory unit and a cross-sectional structural schematic diagram of a protective layer;

[0022] Figure 6 Shown in Figure 5 A schematic cross-sectional structure diagram of an insulating dielectric layer is formed on the structure shown;

[0023] Figure 7 A schematic cross-sectional structure diagram of forming a top metal layer is shown;

[0024] Figure 8 Shown in Figure 3 A schematic cross-sectional structure diagram of a barrier material layer and a lower electrode material layer formed on the structure shown;

[0025] Fig. 9 Shows the Figure 8 A schematic diagram of the cross-sectional structure of the lower electrode material layer in the structure shown after chemical mechanical polishing;

[0026] Fig.10 Shown in Fig. 9 A schematic diagram of a cross-sectional structure after further etching back the lower electrode material layer based on the structure shown;

[0027] Fig.11 Shown in Fig.10 A schematic cross-sectional structure diagram of a random access memory unit film layer and an upper electrode material layer formed on the structure shown;

[0028] Fig.12 Shows the etching Fig.11 The structure shown is a schematic cross-sectional structure diagram of forming a random access memory unit and forming a protective layer;

[0029] Fig.13 Shown in Fig.12 A schematic cross-sectional structure diagram of an insulating dielectric layer is formed on the structure shown.

[0030] The above drawings include the following reference numerals:

[0031] 10. substrate; 20. first metal wiring layer; 30. second metal wiring layer; 40. first conductive channel; 50. second conductive channel; 51. random access memory unit film layer; 60. lower electrode material layer; 70. middle material layer; 80. upper electrode material layer; 90. random access memory unit; 100. protective layer; 110. insulating dielectric layer; 120. top metal layer; 130. barrier material layer. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] As mentioned in the background technology, the main disadvantages of the existing technologies that restrict the development of MRAM in the prior art are low array density and high manufacturing cost. In order to solve the above technical problems, the inventors of this application provide a random access memory structure and a manufacturing method thereof.

[0036] In some optional embodiments, a random access memory structure is provided, which includes: a substrate, the substrate includes an array area and a logic area arranged adjacent to each other, the substrate has a step structure, the step structure has a first step surface corresponding to the array area and a second step surface corresponding to the logic area; a first conductive path, the first conductive path extends from the first step surface to a first metal wiring layer in the array area; a second conductive path extends from the second step surface to a second metal wiring layer in the logic area; a random access memory unit, the random access memory unit is arranged on the first step surface, and the first conductive path is contacted; a top metal layer, the top metal layer is contacted with at least one side of the random access memory unit away from the first conductive path.

[0037] The first direction is a direction perpendicular to the first step surface, the first conductive channel has a first height in the first direction, the second conductive channel has a second height in the first direction, the first height is less than the second height, and optionally, the height difference between the first height and the second height can be 50nm to 200nm. Further, the materials of the first conductive channel and the second conductive channel can be independently selected from any one or more of titanium (Ti), tungsten (W), tantalum (Ta), tantalum nitride (TaN) and titanium nitride (TiN).

[0038] It should be noted that the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step, and then the step structure is formed by etching.

[0039] Furthermore, the random access memory structure also includes a protective layer and an insulating dielectric layer, wherein the protective layer is arranged on the periphery and the first step surface of the random access memory unit, that is, the magnetoresistive random access memory unit has an exposed surface on the side away from the first conductive channel, and the dielectric insulating layer is arranged on the side of the protective layer away from the substrate, so that in the process of forming a top metal layer on the side of the magnetoresistive random access memory unit away from the first conductive channel, the top metal layer can be electrically connected to the exposed surface of the magnetoresistive random access memory unit, and by arranging the insulating dielectric layer, the sum of the thickness of the protective layer and the insulating dielectric layer in the direction perpendicular to the first step surface is consistent with the thickness of the magnetoresistive random access memory unit, so that at least a top metal layer with uniform thickness can be formed in the array area corresponding to the first step surface.

[0040] According to the present application, since the substrate of the random access memory structure includes an array area and a logic area adjacent to each other, and the substrate has a step structure, the step structure can have a first step surface corresponding to the array area and a second step surface corresponding to the logic area. Furthermore, since the substrate also has a first conductive channel and a second conductive channel, wherein the first conductive channel is located in the array area, and the second conductive channel is located in the logic area, and the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step, and the substrate is also correspondingly provided with a first metal wiring layer located in the array area and a second metal wiring layer located in the logic area, thereby In the case where the column area and the logic area correspond to the above-mentioned step structure, the above-mentioned first conductive channel extends from the above-mentioned first step surface to the first metal wiring layer in the array area, and the second conductive channel extends from the above-mentioned second step surface to the second metal wiring layer in the logic area, so that in the first direction perpendicular to the first step surface, the first conductive channel has a first height in the first direction, and the second conductive channel has a second height in the first direction, and the first height is less than the second height, and then a random access memory unit contacting the above-mentioned first conductive channel can be arranged on the above-mentioned first step surface, and at least a top metal layer contacting the random access memory unit can be arranged. That is, through the above-mentioned random access memory structure of the present application, the first conductive channel and the second conductive channel located in the random access memory unit can be formed in the same step, so that compared with the prior art that needs to form the bottom through hole corresponding to the first conductive channel and the top through hole corresponding to the second conductive channel through different etching steps, the present application reduces the number of masks, thereby greatly reducing the manufacturing cost of the random access memory structure.

[0041] In some optional implementations, the random access memory structure further includes: a top metal layer is disposed in contact with a side of the random access memory unit away from the first conductive channel and the second conductive channel respectively.

[0042] Specifically, in an optional embodiment, the random access memory structure includes a substrate having a step structure, a first conductive channel located in an array area of ​​the substrate and a second conductive channel located in a logic area of ​​the substrate, a random access memory unit contacting the first conductive channel, and a top metal layer contacting the random access memory unit.

[0043] Specifically, in another optional embodiment, the top metal layer in the random access memory structure is not only arranged in contact with the random access memory unit, but also arranged in contact with the second conductive path located in the logic area. Through this embodiment, the array area and the logic area in the random access memory structure are electrically connected.

[0044] In some optional implementations, the random access memory structure further includes: a blocking layer, wherein the blocking layer is respectively disposed in contact with the random access memory unit and the first conductive channel.

[0045] Specifically, in an optional embodiment, the random access memory structure includes a substrate with a step structure, a first conductive channel located in an array area of ​​the substrate, a second conductive channel located in a logic area of ​​the substrate, a barrier layer contacting the first conductive channel, a random access memory unit contacting the barrier layer, and a top metal layer contacting at least the random access memory unit. In the above embodiment, by providing a barrier layer between the first conductive channel and the random access memory unit, the quality of each film layer of the formed random access memory unit can be better.

[0046] Specifically, in another optional embodiment, the random access memory structure not only has a barrier layer that is respectively in contact with the first conductive channel and the random access memory unit, but also the top metal layer in the random access memory structure is also respectively in contact with the upper electrode of the random access memory unit and the second conductive channel located in the logic area. In this embodiment, by providing the barrier layer, the quality of each film layer of the formed random access memory unit is better, and because the top metal layer is respectively in contact with the upper electrode and the second conductive channel, the electrical connection between the array area and the logic area in the random access memory structure is achieved.

[0047] In some optional implementations, the random access memory cell includes any one of a magnetic random access memory cell, a phase change random access memory cell and a resistive random access memory cell.

[0048] Specifically, any one of the above-mentioned magnetic random access memory unit, phase change random access memory unit and resistive random access memory unit can be replaced with a random access memory unit mentioned in any embodiment of the present application, so as to obtain a random access memory structure under different requirements.

[0049] Wherein, in the case where the random access memory unit is the magnetic random access memory unit, the random access memory unit may include a lower electrode, a magnetic tunnel junction and an upper electrode stacked in sequence along a side away from the substrate, wherein the magnetic tunnel junction includes a free magnetic layer, a tunnel gate layer and a fixed magnetic layer stacked in sequence, and the lower electrode is arranged in contact with the first conductive channel, and the material of the tunnel gate layer may include but is not limited to magnesium oxide or aluminum oxide. In this structure, the polarization direction of the magnetic tunnel junction can be driven to change by an external magnetic field or electric field, so that the free magnetic layer and the fixed magnetic layer of the magnetic tunnel junction appear in two states of parallel and anti-parallel, and because the magnetic resistance (TMR) corresponding to the parallel and anti-parallel is very different, low resistance and high resistance can be used as two different states of "0" and "1".

[0050] Wherein, in the case where the random access memory unit is the phase change random access memory unit, the phase change random access memory unit may include a lower electrode, a phase change layer and an upper electrode which are sequentially stacked along a side away from the substrate, wherein the lower electrode is arranged in contact with the first conductive channel, and the material of the phase change layer may include but is not limited to chalcogenide (represented by Intel), and a synthetic material containing germanium, antimony and tellurium (GST), such as Ge2Sb2Te5 (represented by STMicroelectronics), etc. In this structure, since the material corresponding to the phase change layer can be transformed between crystallization (low resistance state) and amorphization (high resistance state), the difference in conductivity after transformation between the crystalline state and the amorphous state of the material corresponding to the phase change layer can be used to store information.

[0051] Wherein, in the case where the random access memory unit is the resistive random access memory unit, the resistive random access memory unit may include a lower electrode, a thin dielectric layer and an upper electrode stacked in sequence along a side away from the substrate, wherein the thin dielectric layer serves as an ion transport and storage medium, wherein the thin dielectric layer may include a binary transition metal oxide (TMO), a perovskite compound, a solid electrolyte and an organic dielectric material, etc., wherein the binary transition metal oxide may include but is not limited to any one of nickel oxide (NiO), titanium oxide (TiO2) and zinc oxide (ZnO). In this structure, the high and low resistance states of the structure can be detected by forming and disconnecting filaments (conductive filaments formed by ion transport between the upper and lower electrodes) in the thin dielectric layer.

[0052] In addition, in some optional implementations, in order to align the random access memory unit and the first conductive via, an alignment mark is provided in the substrate near a side of the random access memory unit, and the alignment mark is usually arranged at the periphery of the chip.

[0053] The exemplary embodiments of the method for making the random access memory structure provided by the present invention will be described in more detail below. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0054] In some optional embodiments, such as Figure 1 As shown, the inventor of the present application provides a method for manufacturing a random access memory structure, the manufacturing method comprising: providing a substrate 10, the substrate 10 comprising an array area and a logic area adjacently arranged, and having a first conductive channel 40 in the array area and a second conductive channel 50 in the logic area; etching at least a portion of the substrate 10 corresponding to the array area to form a step structure in the substrate 10, the step structure having a first step surface corresponding to the array area and a second step surface corresponding to the logic area, and the first conductive channel 40 extends from the first step surface to the first metal wiring layer 20 of the array area, and the second conductive channel 50 extends from the second step surface to the second metal wiring layer 30 of the logic area; forming a random access memory unit 90 on the first step surface, the random access memory unit 90 being arranged in contact with the first conductive channel 40; forming a top metal layer 120 at least in contact with a side of the random access memory unit 90 away from the first conductive channel 40. Optionally, a barrier material layer 130 may also be included between the random access memory unit 90 and the first conductive channel 40. Optionally, the random access memory structure further includes a protection layer 100 , which covers the sidewalls and the first step surface of the random access memory unit 90 , wherein the dotted line in the figure can be understood as a boundary line between the array area and the logic area.

[0055] Specifically, in the above implementation, if Figure 2 As shown, a metal wiring layer is also provided in the substrate 10, and the metal wiring layer includes a first metal wiring layer 20 located in the array area and a second metal wiring layer 30 located in the logic area. Furthermore, the array area has a first conductive channel 40 in contact with the first metal wiring layer 20, and the logic area has a second conductive channel 50 in contact with the second metal wiring layer 30. After etching the portion of the substrate 10 corresponding to the array area, a step structure is formed in the substrate 10, so that the array area has a first step surface corresponding to the step structure, and the logic area has a second step surface corresponding to the step structure, so that the first conductive channel 40 extends from the first step surface to the first metal wiring layer 20 in the array area, and the second conductive channel 50 extends from the second step surface to the second metal wiring layer 30 in the logic area, as shown in FIG. Figure 3 shown.

[0056] It should be noted that if Figure 2 The first conductive channel 40 and the second conductive channel 50 shown above are formed in the same etching step and the same filling step. Specifically, the substrate 10 provided first includes an array area and a logic area, and the array area has a first metal wiring layer 20, and the logic area has a second metal wiring layer 30. In order to form the first conductive channel 40 and the second conductive channel 50, a photolithography process is first used to set a mask on the surface of the substrate 10 to form a first pattern on the surface of the substrate 10 corresponding to the array area, and a second pattern on the surface of the substrate 10 corresponding to the logic area, and then etching is performed according to the first pattern and the second pattern to form a first through hole extending from the surface of the substrate 10 to the first metal wiring layer 20 in the substrate 10 corresponding to the array area, and a second through hole extending from the surface of the substrate 10 to the second metal wiring layer 30 in the substrate 10 corresponding to the logic area. Then, a metal material is deposited on the surface of the substrate 10 by a deposition process, and at least the metal material fills the first through hole and the second through hole. Furthermore, a chemical mechanical polishing process can be used to remove the metal material outside the first through hole and the second through hole to form a first conductive channel 40 and a second conductive channel 50. Furthermore, at least a portion of the substrate corresponding to the array area is etched to form a conductive channel 40 in the substrate. Figure 3 The step structure shown.

[0057] Through the above-mentioned manufacturing method, the first conductive channel 40 is used as the bottom conductive channel in the random access memory structure, and the second conductive channel 50 is used as the top conductive channel in the random access memory structure. Usually, at least two etchings are used in different process steps to form the above-mentioned bottom conductive channel and top conductive channel, which will lead to higher manufacturing costs. However, in the present application, the above-mentioned first conductive channel 40 and the second conductive channel 50 are formed in the same process step, and only one etching is needed to achieve the purpose of using the first conductive channel 40 as the bottom conductive channel of the random access memory structure and the second conductive channel 50 as the top conductive channel of the random access memory structure, and then a random access memory unit 90 is formed on the above-mentioned first conductive channel 40 and is arranged in contact with the above-mentioned first conductive channel 40, and a top metal layer 120 is formed that is arranged in contact with at least the random access memory unit 90. Therefore, through the present application, the number of etching times and the number of masks corresponding to the etching can be reduced, thereby greatly reducing the manufacturing cost of the random access memory structure.

[0058] In some optional embodiments, such as Figure 3 As shown, the steps of forming the above-mentioned step structure include: setting a first mask plate on the above-mentioned substrate 10, the first mask plate having a hollow area, and the hollow area is at least set corresponding to the array area; etching the substrate corresponding to the hollow area to remove the part of the substrate 10 corresponding to the array area to form a step structure.

[0059] Specifically, Figure 3 As shown, in the above embodiment, in order to make the first conductive channel 40 serve as the bottom conductive channel in the random access memory structure, and to make the second conductive channel 50 serve as the top conductive channel in the random access memory structure, the above-mentioned first mask plate is set and etched, so that a step structure is first formed in the array area and the logic area, so that in the direction perpendicular to the first step surface, the first conductive channel 40 has a first height, the second conductive channel 50 has a second height, and the first height is smaller than the second height, so that a random access memory unit can be set on the first conductive channel 40 with the first height, so that the first conductive channel 40 with the first height serves as the bottom conductive channel of the random access memory structure.

[0060] Optionally, in order to align the formed random access memory unit with the first conductive channel 40, when setting the above-mentioned first mask plate, the hollow area in the above-mentioned first mask plate includes a first hollow area and a second hollow area, wherein the first hollow area corresponds to the above-mentioned array area and is used to form the above-mentioned step structure, and the second hollow area corresponds to the substrate 10 located outside the array area and the logic area, and is used to form an alignment mark. In this step, the same mask plate can be used to simultaneously implement the etching of the step structure and the etching of the alignment mark, so that the bottom conductive channel (first conductive channel 40), the top conductive channel (second conductive channel 50) and the alignment mark of the random access memory structure are simultaneously formed in the same process step, further simplifying the process flow and reducing the manufacturing cost of the random access memory structure.

[0061] Furthermore, in order to electrically connect the array area and the logic area of ​​the random access memory structure, on the basis of forming the top metal layer 120 that is in contact with the side of the random access memory unit away from the first conductive path 40, after the step of forming the random access memory unit 90 on the first step surface, the above-mentioned manufacturing method further includes: forming the top metal layer 120 that is in contact with the side of the random access memory unit away from the first conductive path and the second conductive path, respectively, such as Figure 1 shown.

[0062] In some optional embodiments, such as Figure 4 and Figure 5 As shown, the steps of forming a random access memory unit include: forming a random access memory unit film layer 51 at least on the first step surface, such as Figure 4As shown; a second mask is set on the random access memory unit film layer 51, the second mask has a preset pattern, and at least exposes the remaining portion of the random access memory unit film layer 51 except for the corresponding preset pattern; the random access memory unit film layer 51 is etched according to the preset pattern sequence to remove the exposed random access memory unit film layer 51, forming a random access memory unit 90, as shown Figure 5 shown.

[0063] In the above implementation, if Figure 4 As shown, in order to form a random access memory structure on the first conductive channel 40, a random access memory unit film layer 51 can be formed at least on the first step surface, wherein the random access memory unit film layer 51 can include a stacked lower electrode material layer 60, an intermediate material layer 70, and an upper electrode material layer 80; then, by providing a second mask having a corresponding pattern (preset pattern) of the random access memory unit, when etching is performed according to the second mask, the random access memory unit film layer 51 corresponding to the preset pattern on the first conductive channel 40 can be retained, and the remaining random access memory unit film layer 51 on the first step surface is removed, thereby forming the above-mentioned random access memory unit 90. Optionally, after the above-mentioned random access memory unit 90 is formed, a protective layer 100 is formed on the side of the random access memory unit 90 away from the substrate 10, as shown in FIG. Figure 5 Further, Figure 6 As shown, in Figure 5 The protective layer 100 shown in the figure is away from the substrate 10 to form an insulating dielectric layer 110. Further, a portion of the insulating dielectric layer 110 is removed by chemical mechanical polishing to form a flat upper surface. Figure 7 As shown, a top metal layer 120 is formed on a side of the insulating dielectric layer 110 away from the protection layer 100 .

[0064] Optionally, the random access memory unit film layer 51 can also be set on the first step surface and the second step surface, and then after etching according to the second mask plate, only the random access memory unit film layer 51 corresponding to the preset pattern located on the first conductive channel 40 is retained, and the remaining random access memory unit film layer 51 located on the first step surface and the second step surface is removed, thereby forming the random access memory unit 90.

[0065] In some optional embodiments, in order to form a good quality random access memory unit on the first conductive channel 40, after the step of forming the step structure and before the step of forming the random access memory unit, the manufacturing method further includes: forming a barrier material layer 130 on the first step surface and the second step surface, such as Figure 8In the step of forming a random access memory unit, a random access memory unit film layer is formed on the side of the barrier material layer 130 away from the first conductive channel 40, and the random access memory unit film layer is sequentially etched to form a random access memory unit and a barrier layer.

[0066] Optionally, the barrier material layer 130 is a conductive material layer, and the material of the barrier material layer 130 may be selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and tungsten nitride (WN).

[0067] In some optional embodiments, such as Figure 8 Wherever you go Fig.11 As shown, after the step of forming the barrier material layer 130 and before the step of forming the random access memory unit and the barrier layer, the step of forming the random access memory unit film layer includes: forming a lower electrode material layer 60 covering the barrier material layer 130, as shown in FIG. Figure 8 As shown; chemical mechanical polishing is used to remove part of the lower electrode material layer 60, so that the remaining lower electrode material layer 60 located in the array area has a first thickness in the first direction, such as Fig. 9 As shown; thinning the remaining lower electrode material layer 60 in the array region so that the lower electrode material layer 60 after thinning has a second thickness in the first direction, the first thickness is greater than the second thickness, as shown Fig.10 As shown; forming an intermediate material layer 70 covering at least the lower electrode material layer 60 after thinning and an upper electrode material layer 80 covering the intermediate material layer 70, the lower electrode material layer 60, the intermediate material layer 70 and the upper electrode material layer 80 after thinning form a random access memory unit film layer 51, as Fig.11 shown.

[0068] Optionally, the material of the lower electrode material layer 60 can be selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and tungsten nitride (WN). It should be noted that the material of the barrier material layer 130 is different from that of the lower electrode material layer 60 in the random access memory cell.

[0069] Specifically, in the case where the random access memory unit is a magnetic random access memory unit, the intermediate material layer 70 is a material film layer corresponding to the magnetic tunnel junction, that is, the intermediate material layer 70 is a material layer corresponding to the free magnetic layer, the material layer corresponding to the tunnel gate layer and the material layer corresponding to the fixed magnetic layer stacked in sequence; in the case where the random access memory unit is a phase change random access memory unit, the intermediate material layer 70 is a material layer corresponding to the phase change layer; in the case where the random access memory unit is a resistive random access memory unit, the intermediate material layer 70 is a material layer corresponding to the thin dielectric layer.

[0070] In the above implementation, if Fig. 9 As shown, in order to facilitate the etching process of the lower electrode material, after the lower electrode material layer 60 is formed, the lower electrode material layer 60 is first planarized by chemical mechanical polishing so that the lower electrode material layer 60 has a flat surface. In particular, in order to facilitate the chemical mechanical polishing process to control the thickness of the lower electrode material layer 60, the planarization process removes the lower electrode material layer 60 located in the logic area, so that the blocking material layer 130 located in the logic area is exposed, and the lower electrode material layer 60 located in the array area is retained. Then, after the chemical mechanical polishing step, the lower electrode material layer 60 located in the array area is thinned by etching, as shown in FIG. Fig.10 As shown, the thinned lower electrode material layer 60 is used to form the lower electrode of the magnetoresistive random access memory unit. In particular, after the chemical mechanical polishing process is used to remove part of the lower electrode material layer 60, if part of the lower electrode material layer 60 is still retained on the barrier material layer 130 in the logic area, the remaining lower electrode material layer 60 on the barrier material layer 130 in the logic area is removed during the thinning process to expose the barrier material layer 130 in the logic area, and then the intermediate material layer 70 and the upper electrode material layer 80 are deposited in sequence, so that the lower electrode material layer 60, the intermediate material layer 70 and the upper electrode material layer 80 are stacked in sequence to form a random access memory unit film layer 51, as shown in FIG. Fig.11 shown.

[0071] Optionally, after forming the upper electrode material layer 80 , a hard mask layer may be formed on the upper electrode material layer 80 and used as a sacrificial layer for etching to form the random access memory unit film layer 51 , so as to remove the hard mask layer during the formation of the random access memory unit film layer 51 .

[0072] Furthermore, in some embodiments, by first depositing a barrier material layer and a lower electrode material layer, and then planarizing and etching back, and then forming the various film layers corresponding to the above-mentioned random access memory unit on the lower electrode material layer after etching back, the various film layers corresponding to the random access memory unit can have a smoother surface, which is beneficial to the subsequent formation of the random access memory structure and performance improvement.

[0073] Further, the random access memory unit film layer 51 is etched to form the random access memory unit 90, and a protection layer 100 covering the first step surface, the random access memory unit 90 and the second step surface is formed, so that the protection layer 100 covers the exposed surface after the random access memory unit 90 is formed, as shown in FIG. Fig.12 As shown, after the random access memory unit 90 is formed by etching, in the step of forming the top metal layer 120, an insulating dielectric layer 110 is formed on the protective layer 100, as shown in FIG. Fig.13 As shown; further, the insulating dielectric layer 110 and the protective layer 100 are sequentially etched to expose the surface of the random access memory unit 90 away from the first conductive channel 40, and to expose the second conductive channel 50 on the second step surface. Optionally, this process can be obtained by chemical mechanical polishing; then a top metal layer 120 is formed on the exposed surface of the random access memory unit 90 away from the first conductive channel 40; or further, a top metal layer 120 is formed on the exposed surface of the random access memory unit 90 away from the first conductive channel 40 and the exposed second conductive channel 50, as shown in FIG. Figure 1 shown.

[0074] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0075] According to the present application, since the substrate of the random access memory structure includes an array area and a logic area adjacent to each other, and the substrate has a step structure, the step structure can have a first step surface corresponding to the array area and a second step surface corresponding to the logic area. Furthermore, since the substrate also has a first conductive channel and a second conductive channel, wherein the first conductive channel is located in the array area and the second conductive channel is located in the logic area, and the substrate also has a first metal wiring layer located in the array area and a second metal wiring layer located in the logic area correspondingly arranged, when the array area and the logic area correspond to the above-mentioned step structure, the above-mentioned first conductive channel extends from the above-mentioned first step surface to the first metal wiring layer in the array area, and the second conductive channel extends from the above-mentioned second step surface to the second metal wiring layer in the logic area, so that in a first direction perpendicular to the first step surface, the first conductive channel has a first height in the first direction, and the second conductive channel has a second height in the first direction, and the first height is less than the second height, and then a random access memory unit contacting with the above-mentioned first conductive channel can be arranged on the above-mentioned first step surface, and at least a top metal layer contacting with the random access memory unit can be arranged. That is, through the above-mentioned random access memory structure of the present application, it is possible to form a first conductive channel and a second conductive channel located in a random access memory unit in the same step. Compared with the prior art that requires different etching steps to form a bottom through hole corresponding to the first conductive channel and a top through hole corresponding to the second conductive channel, the present application reduces the number of etching masks, thereby greatly reducing the production cost of the random access memory structure.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A random access memory structure, characterized in that: include: A substrate, the substrate comprising an array region and a logic region adjacently arranged, the substrate having a step structure, the step structure having a first step surface corresponding to the array region and a second step surface corresponding to the logic region; A first conductive path, the first conductive path extending from the first step surface to a first metal wiring layer in the array region; a second conductive path, the second conductive path extending from the second step surface to a second metal wiring layer in the logic area; A random access memory unit, wherein the random access memory unit is disposed on the first step surface and is in contact with the first conductive channel; A top metal layer is disposed in contact with at least one side of the random access memory unit away from the first conductive channel.

2. The random access memory structure according to claim 1, characterized in that: Also includes: The top metal layer is disposed in contact with a side of the random access memory unit away from the first conductive channel and the second conductive channel respectively.

3. The random access memory structure according to claim 1 or 2, characterized in that: Also includes: A barrier layer is disposed in contact with the random access memory unit and the first conductive channel respectively.

4. The random access memory structure according to claim 1 or 2, characterized in that: The random access memory cell includes any one of a magnetic random access memory cell, a phase change random access memory cell and a resistive random access memory cell.

5. A method for manufacturing a random access memory structure, characterized in that: The production method comprises: Providing a substrate, the substrate comprising an array region and a logic region adjacently arranged, wherein the array region has a first conductive channel, the logic region has a second conductive channel, and the first conductive channel and the second conductive channel are formed in the same etching step and the same filling step; At least a portion of the substrate corresponding to the array area is etched to form a step structure in the substrate, wherein the step structure has a first step surface corresponding to the array area and a second step surface corresponding to the logic area, and the first conductive path extends from the first step surface to the first metal wiring layer of the array area, and the second conductive path extends from the second step surface to the second metal wiring layer of the logic area; A random access memory unit is formed on the first step surface, wherein the random access memory unit is arranged in contact with the first conductive channel; A top metal layer is formed to contact at least one side of the random access memory cell away from the first conductive path.

6. The method according to claim 5, characterized in that: The steps of forming the step structure include: A first mask plate is arranged on the substrate, wherein the first mask plate has a hollow area, and the hollow area is arranged at least corresponding to the array area; The substrate corresponding to the hollow area is etched to remove a portion of the substrate corresponding to the array area to form the step structure.

7. The manufacturing method according to claim 5, characterized in that: Also includes: A top metal layer is formed to be respectively disposed in contact with a side of the random access memory cell away from the first conductive path and the second conductive path.

8. The production method according to any one of claims 5 to 7, characterized in that: The steps of forming the random access memory cell include: forming a random access memory unit film layer at least on the first step surface; A second mask is arranged on the random access memory unit film layer, wherein the second mask has a preset pattern and at least exposes the remaining portion of the random access memory unit film layer except for the portion corresponding to the preset pattern; The random access memory unit film layer is etched sequentially according to the preset pattern to remove the exposed random access memory unit film layer and form the random access memory unit.

9. The manufacturing method according to claim 8, characterized in that: After the step of forming the step structure, Before forming the random access memory unit, the manufacturing method further includes: forming a barrier material layer on the first step surface and the second step surface; In the step of forming the random access memory unit, the random access memory unit film layer is formed on the side of the barrier material layer away from the first conductive channel, and the random access memory unit film layer is sequentially etched to form the random access memory unit and the barrier layer.

10. The manufacturing method according to claim 9, characterized in that: After the step of forming the barrier material layer and before the step of forming the random access memory unit and the barrier layer, the step of forming the random access memory unit film layer comprises: forming a lower electrode material layer covering the barrier material layer; Removing part of the lower electrode material layer by chemical mechanical polishing, so that the remaining lower electrode material layer located in the array region has a first thickness in a first direction, wherein the first direction is a direction perpendicular to the first step surface; Thinning the remaining lower electrode material layer in the array region so that the lower electrode material layer after thinning has a second thickness in the first direction, and the first thickness is greater than the second thickness; An intermediate material layer at least covering the thinned lower electrode material layer and an upper electrode material layer covering the intermediate material layer are formed, and the thinned lower electrode material layer, the intermediate material layer and the upper electrode material layer form the random access memory unit film layer.

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