Forming method of silicon carbide LDMOS structure, silicon carbide LDMOS structure and silicon carbide LDMOS device

Abstract

The invention discloses a silicon carbide LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure and a forming method thereof. The forming method comprises the following steps: forming a first well region; a second well region is formed, the second well region and the first well region are partially overlapped, and the injection depth of the second well region is smaller than that of the first well region; forming a third region, the third region being contained in the first well region and partially overlapping the second well region, and the injection depth of the third region being less than the injection depth of the second well region; a source electrode region is manufactured on the surface of the second well region, the source electrode region comprises an N + region and a P + region, and the source electrode region and the first well region are partially overlapped; manufacturing a drain region on the surface of the third region; and manufacturing a grid electrode region on the surface between the source electrode region and the third region, and forming electrodes of a grid electrode, a source electrode and a drain electrode. The method has the advantages that the product obtained by the method has the characteristics of high pressure resistance and small size, the manufacturing process is simple, and the yield of finished products is improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for forming a silicon carbide LDMOS semiconductor device structure, a device silicon carbide LDMOS structure, and a silicon carbide LDMOS semiconductor device. Background Art

[0002] The half-bridge circuit is a common electronic circuit structure, usually composed of two transistors and a load. Depending on the needs of the circuit, a voltage regulator diode or a Zener diode may be added. In the half-bridge circuit, the two transistors are usually turned on alternately, thereby generating an oscillating signal as an output voltage provided to the load.

[0003] Based on the customary drawing method of circuit diagrams, the two transistors are usually called High Side MOS (also known as upper tube) and Low Side MOS (also known as lower tube). In power drive or motor drive application scenarios, it is difficult to integrate upper and lower tubes that can withstand voltages above 600V (especially above 1200V). Even if they are made, their size is large and the process used is complicated. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention designs a structure of a lower tube and a corresponding manufacturing method based on the characteristics of the lower tube in the half-bridge circuit by utilizing the high critical breakdown electric field characteristics of SiC materials, so as to realize the characteristics of the lower tube in the half-bridge circuit being able to withstand high voltage and high current density.

[0005] First, the present application provides a method for forming a silicon carbide LDMOS structure, comprising:

[0006] Growing an epitaxial layer on a substrate, wherein the epitaxial layer is of P type;

[0007] Implanting N-type ions at a central position on the surface of the epitaxial layer to form a first well region;

[0008] Implanting P-type ions at an edge position of the surface of the epitaxial layer to form a second well region, wherein the second well region partially overlaps with the first well region, and an implantation depth of the second well region is less than an implantation depth of the first well region;

[0009] Implanting N-type ions on the surface of the epitaxial layer to form a third region, wherein the third region is included in the first well region and partially overlaps with the second well region, and the implantation depth of the third region is less than the implantation depth of the second well region, and the implantation concentration of the third region matches the implantation concentration of the second well region;

[0010] A source region is formed on the surface of the second well region, wherein:

[0011] The source region includes an N+ region and a P+ region, and

[0012] The source region partially overlaps with the first well region;

[0013] Fabricating a drain region on the surface of the third region;

[0014] A gate region is fabricated on the surface between the source region and the third region, and electrodes of the gate, source and drain are formed.

[0015] In the above method, the implantation depth of the first well region is 1 μm-5 μm.

[0016] In the above method, the implantation depth of the second well region is 1 μm-4 μm.

[0017] In the above method, the implantation depth of the third region is 0 μm-2 μm.

[0018] In the above method, the net doping concentration ratio of the third region, the second well region, the first well region and the epitaxial layer is 1:2:2:1.

[0019] In the above method, the material of the substrate includes silicon carbide (SiC).

[0020] The present application also provides a silicon carbide LDMOS device structure, including:

[0021] substrate;

[0022] A P-type epitaxial layer grown on the substrate;

[0023] A first well region is located in the middle of the P-type epitaxial layer and has a depth less than that of the P-type epitaxial layer;

[0024] A second well region is located at one side of the P-type epitaxial layer and partially overlaps with the first well region, the depth of the second well region is less than the depth of the first well region, and a source region is formed on the surface of the second well region, the source region includes an N+ region and a P+ region, and the N+ region partially overlaps with the first well region;

[0025] A third region is located in the first well region and partially overlaps with the second well region, the depth of the third region is less than the depth of the second well region, and a drain region is formed on the surface of the third region;

[0026] A gate region is fabricated on the surface between the source region and the third region, and electrodes of the gate, source and drain are formed.

[0027] In the above device structure, the first well region is formed by ion implantation, and the implantation depth is 1 μm-5 μm.

[0028] In the above device structure, the second well region is formed by ion implantation, and the implantation depth is 1 μm-4 μm.

[0029] In the above device structure, the third region is formed by ion implantation, and the implantation depth is 0 μm-2 μm.

[0030] In the above device structure, the net doping concentration ratio of the third region, the second well region, the first well region and the epitaxial layer is 1:2:2:1.

[0031] The present application also provides a silicon carbide LDMOS device, comprising the above-mentioned semiconductor device structure.

[0032] Compared with the prior art, the manufacturing process of the method for forming a semiconductor device structure proposed in the present invention is simple and efficient. The manufactured semiconductor device structure has the characteristics of high withstand voltage and small size. It is convenient to integrate with the upper tube in the half-bridge circuit to obtain a high withstand voltage and high current density LDMOS (Laterally Diffused Metal Oxide Semiconductor). BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A flowchart of a forming method according to some embodiments of the present application is shown;

[0034] Figure 2-7 Shown according to Figure 1 The schematic diagram shows the structural changes of the semiconductor device when the semiconductor device is manufactured by the forming method shown. DETAILED DESCRIPTION

[0035] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0036] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise clearly and specifically defined, the meaning of "plurality" is two or more.

[0038] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0039] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0040] The term "and / or" in this article is just a description of the association relationship between related objects, indicating that there can be three types of relationships:

[0041] In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of types. For example, at least one of A, B, and C may mean any one or more elements selected from the set consisting of A, B, and C.

[0042] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0043] The embodiments of the present application will be described in further detail below in conjunction with the accompanying drawings.

[0044] Figure 1 A flow chart of a method for forming a silicon carbide LDMOS structure according to some embodiments of the present application is shown.

[0045] As shown in the figure, a method for forming a semiconductor device structure proposed in the present application includes the following steps S1-S5:

[0046] S1, please refer to Figure 2 . An epitaxial layer 1 is grown on the substrate 8 to obtain a base for making a MOSFET device. Among them, the material of the substrate 8 can be an N-type substrate or a P-type substrate according to the type of semiconductor device, and this application does not impose any special restrictions on this. Exemplarily, in some embodiments, the material of the substrate 8 can include any one of silicon (Si), silicon carbide (SiC), gallium nitride (GaN) and gallium arsenide (GaAs). Preferably, the embodiment of the present application uses silicon carbide (SiC) material as the material of the substrate 8, so that the high critical breakdown electric field characteristics of the SiC material can be utilized to further improve the high voltage resistance and high current density characteristics of the SiC device. The material of the epitaxial layer 1 can be a P-type epitaxial material, and the doping concentration of the P-type material can be set according to the design intention. Furthermore, a dielectric layer 2 can be grown on the surface of the epitaxial layer 1 to serve as a masking layer for subsequent injection processes. This application does not limit the material type and thickness of the dielectric layer 2, and those skilled in the art can set it according to actual conditions and needs. Exemplarily, the material of the dielectric layer 2 can be silicon dioxide, and the thickness of the silicon dioxide layer can be In other embodiments, other materials may be used to form a masking layer. For example, an injection mask may be formed on the surface area of ​​the epitaxial layer 1. The specific type of the injection mask is not limited in this application. For example, the injection mask may be a photoresist or a hard mask.

[0047] S2, patterning the dielectric layer 2, etching the central area thereof, exposing the epitaxial layer 1. In the exposed epitaxial layer 1 area (combined with Figure 3 It can be seen that N-type ions are implanted in this region (basically at the center of the surface of the epitaxial layer 1) with an implantation depth of 1 micron to 5 microns, thereby forming a first well region (N-WELL) 3. In order to make the implanted ions evenly distributed, a multiple (for example, 3) implantation process can be used.

[0048] S3, at the edge position of the surface of the epitaxial layer 1 (please refer to Figure 4) is injected with P-type ions to form a second well region (P-WELL) 4. It can be understood that the edge position is intended to indicate that there is an overlap between the first well region 3 and the second well region 4, and the degree of overlap can be a heavy overlap, that is, the second well region 4 penetrates more than half of the first well region 3. The part of the second well region 4 that does not overlap with the first well region 3 is located on one side of the first well region 3, and its outermost edge can overlap with the side wall of the epitaxial layer 1, that is, one side of the second well region 4 is in the first well region 3, and the other side is the side wall of the epitaxial layer 1. In addition, the injection depth of the second well region 4 is less than the injection depth of the first well region 3, and can generally be 1 micron to 4 microns.

[0049] S4, please refer to Figure 5 . Continue to inject N-type ions on the surface of the epitaxial layer 1 to form a third region (N-TOP) 5. The third region 5 is completely located in the first well region 3 and partially overlaps with the second well region 4. And the injection depth of the third region 5 is less than the injection depth of the second well region 4. Specifically, its injection depth can be an injection depth of 0 microns-2 microns. Moreover, the injection concentration of the third region 5 matches the injection concentration of the second well region 4, so that the N-type ions and P-type ions in the overlapping area of ​​the third region 5 and the second well region 4 can offset each other partially, so that the characteristics of N-type ions are displayed in the overlapping area. Similarly, the ion injection concentration of the overlapping part of the second well region 4 and the first well region 3 also needs to be adapted so that the characteristics of P-type ions are displayed in the overlapping area.

[0050] Furthermore, the doping concentrations of the third region 5, the second well region 4, the first well region 3 and the epitaxial layer 1 may be carried out at a suitable concentration ratio to obtain a charge balance between the regions. Preferably, the net doping concentration ratio may be 1:2:2:1.

[0051] S5, fabricating a source region on the surface of the second well region 4. Specifically, the ion concentration of a small portion of the surface of the second well region 4 is changed by injecting N-type ions and P-type ions, so that in subsequent process steps, a metal-like conductive surface can be fabricated in the source region by depositing / sputtering Ni (nickel) metal, annealing, etc.

[0052] a. The source region includes an N+ region 6 and a P+ region 7, and the source region partially overlaps with the first well region 3. Figure 6As shown, the so-called partial overlap means that the side 31 of the first well region 3 can intersect with the N+ region 6, or intersect with the P+ region 7, but the side 31 will not overlap with the outer boundary of the N+ region 6 or the P+ region 7. In this way, the P+ region 7 injected with P-type ions, the second well region 4 and the epitaxial layer 1 can remain continuous and unbroken, thereby ensuring that the silicon carbide LDMOS structure proposed in the present application is effectively and reliably connected to the "GND" of the integrated half-bridge circuit after being integrated as a low-side LDMOS and a high-side LDMOS.

[0053] b. Fabricate the drain region 10 on the surface of the third region 5. Similarly, in this step, N-type ions are injected into the drain region to change the ion concentration of a small portion of the surface of the third region 5, so that the drain of the structure can form a better ohmic contact.

[0054] c. The gate region 11 is manufactured according to conventional processes, and the source region and the drain region 10 are respectively subjected to metallization treatment and metal deposition and other process steps, thereby forming Figure 7 The source electrode 12 and the drain electrode 13 are shown.

[0055] The above has completed a basic semiconductor device structure, which has a simple structure and has the characteristics of high current density and high voltage resistance. On this basis, it can be further packaged to form an independent semiconductor device. It is particularly suitable for packaging Low side MOS (low side MOS tube, as the lower tube) and High side MOS (high side MOS tube, as the upper tube) together to form a half-bridge circuit and packaged as an integrated chip. The half-bridge chip obtained by this method has the characteristics of high voltage resistance (generally 600V-3300V) and small size.

[0056] In addition, the manufacturing process is simple and efficient, which is conducive to improving the yield rate of finished products.

[0057] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0058] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A method for forming a silicon carbide LDMOS structure, characterized in that: include: Growing an epitaxial layer on a substrate, wherein the epitaxial layer is of P type; Implanting N-type ions at a central position on the surface of the epitaxial layer to form a first well region; Implanting P-type ions at an edge position of the surface of the epitaxial layer to form a second well region, wherein the second well region partially overlaps with the first well region, and an implantation depth of the second well region is less than an implantation depth of the first well region; Implanting N-type ions on the surface of the epitaxial layer to form a third region, wherein the third region is included in the first well region and partially overlaps with the second well region, and the implantation depth of the third region is less than the implantation depth of the second well region, and the implantation concentration of the third region matches the implantation concentration of the second well region; A source region is formed on the surface of the second well region, wherein: The source region includes an N+ region and a P+ region, and the source region partially overlaps with the first well region; Fabricating a drain region on the surface of the third region; A gate region is fabricated on the surface between the source region and the third region, and electrodes of the gate, source and drain are formed.

2. The method according to claim 1, characterized in that The implantation depth of the first well region is 1 μm-5 μm.

3. The method according to claim 1, characterized in that The implantation depth of the second well region is 1 μm-4 μm.

4. The method according to claim 1, characterized in that: The implantation depth of the third region is 0 μm-2 μm.

5. The method according to claim 1, characterized in that A net doping concentration ratio of the third region, the second well region, the first well region, and the epitaxial layer is 1:2:2:

1.

6. The method according to claim 1, characterized in that The material of the substrate includes silicon carbide (SiC).

7. A silicon carbide LDMOS structure, characterized in that: include: substrate; A P-type epitaxial layer grown on the substrate; A first well region is located in the middle of the P-type epitaxial layer and has a depth less than that of the P-type epitaxial layer; A second well region is located at one side of the P-type epitaxial layer and partially overlaps with the first well region, the depth of the second well region is less than the depth of the first well region, and a source region is formed on the surface of the second well region, the source region includes an N+ region and a P+ region, and the N+ region partially overlaps with the first well region; A third region is located in the first well region and partially overlaps with the second well region, the depth of the third region is less than the depth of the second well region, and a drain region is formed on the surface of the third region; A gate region is fabricated on the surface between the source region and the third region, and electrodes of the gate, source and drain are formed.

8. The semiconductor device structure according to claim 7, characterized in that: The first well region is formed by ion implantation, and the implantation depth is 1 μm-5 μm.

9. The semiconductor device structure according to claim 7, characterized in that: The second well region is formed by ion implantation, and the implantation depth is 1 μm-4 μm.

10. The semiconductor device structure according to claim 7, characterized in that: The third region is formed by ion implantation, and the implantation depth is 0 μm-2 μm.

11. The semiconductor device structure according to claim 7, characterized in that: A net doping concentration ratio of the third region, the second well region, the first well region, and the epitaxial layer is 1:2:2:

1.

12. A silicon carbide LDMOS device, characterized in that: Comprising the silicon carbide LDMOS structure as claimed in any one of claims 7 to 11.

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