Groove power device and preparation method thereof

Abstract

The invention discloses a trench power device and a preparation method of the trench power device, the trench power device comprises a substrate and an epitaxial layer, and further comprises at least one trench gate structure, the surface, close to the substrate, of the trench gate structure is in contact with a first epitaxial layer, and the trench gate structure comprises a gate and a gate oxide layer; the Schottky diode structure is located on one side, in the second direction, of the trench gate structure, the Schottky diode structure comprises an insulating layer and a plurality of doping layers which are arranged in a laminated mode in the first direction, the insulating layer is located on one side, close to the substrate, of the doping layer, any two adjacent doping layers have different doping types, and the doping types of the insulating layer and the doping layers are different. The doped layer having the maximum distance from the substrate in the first direction is a first doped layer, any one of the other doped layers is a second doped layer, the second doped layer is in contact with the grid electrode, and the insulating layer is in contact with the gate oxide layer. The problems that in the prior art, a grid electrode of a groove power device is resistant to static breakdown, and electric leakage of the device in an on state is large are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular, to a trench power device and a method for preparing the trench power device. Background Art

[0002] Power MOSFET has the characteristics of low forward voltage drop, high switching speed, and easy gate control, and has become an important semiconductor device in power electronics applications. The gate antistatic ability of power MOSFET is directly related to the chip area and gate oxide thickness. Compared with Si MOS devices, SiC MOS devices are limited by material and process characteristics, with small chip area, thin gate oxide thickness, and poor gate antistatic breakdown ability. As SiC MOS devices are increasingly widely used, new SiC MOS with high antistatic ability continue to emerge. The problem of large leakage of new SiC MOS devices in the on state cannot be ignored. Summary of the invention

[0003] The present application provides a trench power device and a method for preparing the trench power device, so as to solve the problems in the related art of poor anti-static breakdown capability of the gate of the trench power device and large leakage current of the device in the on state.

[0004] According to one aspect of the present application, a trench power device is provided, comprising: a substrate; an epitaxial layer, the epitaxial layer is located on one side of the substrate, the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer has a first doping type, the second epitaxial layer has a second doping type, the epitaxial layer has a first surface away from the substrate, the first direction is the direction from the substrate to the epitaxial layer; at least one trench gate structure, the trench gate structure is located in the epitaxial layer, the surface of the trench gate structure away from the substrate is located in the first surface, the trench gate structure is close to the surface of the substrate and contacts the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is located at the gate The gate oxide layer is located on two surfaces opposite to each other in a second direction on a side of the gate electrode close to the substrate, and the second direction is parallel to the first surface; a Schottky diode structure, the Schottky diode structure is located on one side of the trench gate structure in the second direction, the Schottky diode structure includes an insulating layer and a plurality of doped layers stacked along the first direction, the insulating layer is located on a side of the doped layer close to the substrate, any two adjacent doped layers have different doping types, wherein the doped layer having the maximum distance from the substrate in the first direction is a first doped layer, and any one of the remaining doped layers is a second doped layer, the second doped layer is in contact with the gate electrode, and the insulating layer is in contact with the gate oxide layer.

[0005] Optionally, the second doping layer is located on a side of the remaining doping layers close to the substrate, and the second doping layer is in contact with the insulating layer.

[0006] Optionally, the number of the doping layers is n, wherein n is greater than or equal to four.

[0007] Optionally, the insulating layer has a first thickness in the first direction, the gate oxide layer located on the sidewall of the gate has a second thickness in the second direction, and the first thickness is greater than the second thickness.

[0008] Optionally, the doping layer having the first doping type in the doping layer is a first type doping layer, and the doping layer having the second doping type in the doping layer is a second type doping layer, the doping concentration of the first type doping layer is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the second type doping layer is greater than the doping concentration of the second epitaxial layer.

[0009] Optionally, the plurality of doped layers have a plurality of first widths in the second direction close to a surface of the substrate, and the plurality of first widths decrease gradually along the first direction.

[0010] Optionally, the device further includes: an implantation region, the implantation region is located in the second epitaxial layer, the implantation region is in contact with a surface of the trench gate structure facing away from the Schottky diode structure, and the implantation region has the first doping type.

[0011] According to another aspect of the present application, a method for preparing a trench power device is provided, which is used to prepare any one of the trench power devices, and the preparation method includes: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer including a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface facing away from the substrate, and the first direction is the direction from the substrate to the epitaxial layer; forming at least one trench gate structure in the epitaxial layer, the surface of the trench gate structure facing away from the substrate is located in the first surface, the trench gate structure is close to the surface of the substrate and contacts the first epitaxial layer, and the trench gate structure includes a gate and a gate oxide layer, the gate oxide layer is located on two surfaces of the gate that are opposite to each other in a second direction and the gate oxide layer is located on a side of the gate that is close to the substrate, the second direction is parallel to the first surface; a Schottky diode structure is formed on one side of the trench gate structure in the second direction, the Schottky diode structure includes an insulating layer and a plurality of doped layers stacked along the first direction, the insulating layer is located on a side of the doped layer that is close to the substrate, any two adjacent doped layers have different doping types, wherein the doped layer that has the maximum distance from the substrate in the first direction is the first doped layer, one of the remaining doped layers is the second doped layer, the second doped layer is in contact with the gate, and the insulating layer is in contact with the gate oxide layer.

[0012] Optionally, the steps of forming the trench gate structure include: forming a first trench in the epitaxial layer by an etching process, wherein the bottom surface of the first trench exposes the first epitaxial layer; forming a first insulating layer covering the sidewalls and the bottom surface in the first trench, and the remaining area in the first trench is a second trench; forming the gate on the sidewalls of the second trench; forming a second insulating layer on the sidewalls of the gate, wherein the first insulating layer located on the side of the gate close to the substrate, the first insulating layer located on the side of the gate, and the second insulating layer located on the other side of the gate constitute the gate oxide layer.

[0013] Optionally, the remaining area in the second groove is the third groove, and the steps of forming the Schottky diode structure include: forming the first doping layer on the bottom surface of the third groove, the first doping layer is in contact with the gate and the insulating layer respectively, and the remaining area in the third groove is the fourth groove; forming the second insulating layer on the side wall of the fourth groove, and the remaining area in the fourth groove is the fifth groove; using multiple deposition processes to form multiple layers of the doping layer in the fifth groove, wherein any two adjacent layers of the doping layer have different doping types.

[0014] By applying the technical solution of the present application, a trench power device is provided, in which a Schottky diode structure is located on one side of the trench gate structure in the second direction, so that a Schottky barrier diode (SBD) is integrated in the trench power device, and the gate can be protected. Specifically, the Schottky diode structure includes multiple doping regions and any two adjacent doping layers have different doping types, so that the Schottky diode structure includes at least one PN junction, and the second doping layer in the multiple doping layers is connected to the gate to form a conduction circuit. If the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, thereby improving the antistatic ability of the trench gate structure. In addition, only the second doping layer is connected to the gate, which reduces the contact area between the gate and the Schottky diode structure, so that the trench power device has a smaller leakage current in the turned-on state, thereby reducing the conduction loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a schematic cross-sectional structure diagram of a trench power device according to an embodiment of the present application;

[0017] Figure 2 is a schematic cross-sectional structure diagram of another trench power device according to an embodiment of the present application;

[0018] Figure 3 is a flow chart of a method for preparing a trench power device provided in an embodiment of the present application;

[0019] Figure 4 It is a schematic diagram of a cross-sectional structure of a substrate provided in a method for preparing a trench MOS device provided in an embodiment of the present application;

[0020] Figure 5 is Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the epitaxial layer is shown;

[0021] Figure 6 is Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the first trench is formed in the epitaxial layer shown;

[0022] Figure 7 is Figure 6 The schematic cross-sectional structure diagram of the substrate after the first insulating layer and the second trench are formed on the bottom surface and the sidewall of the first trench;

[0023] Figure 8 is Figure 7 The schematic cross-sectional structure diagram of the substrate after the sidewall of the second trench forms a gate is shown;

[0024] Fig. 9 A schematic diagram of a basic structure obtained in each step of the preparation method for forming a first insulating layer and a gate provided in an embodiment of the present application is shown;

[0025] Fig.10 is Fig. 9 A schematic diagram of the cross-sectional structure of the substrate after the second doping layer and the fourth trench are formed in the trench shown;

[0026] Fig.11 is Fig.10 A schematic cross-sectional structure diagram of the substrate after the second insulating layer and the fifth trench are formed in the fourth trench;

[0027] Fig.12 A schematic diagram of a basic structure obtained in each step of the preparation method for forming a second insulating layer provided in an embodiment of the present application is shown;

[0028] Fig.13 is Fig.12 A schematic cross-sectional structure diagram of the substrate after multiple doping layers are formed in the fifth trench shown;

[0029] Fig.14 is Fig.13 A schematic diagram of the cross-sectional structure of the substrate after the implantation region is formed in the substrate shown;

[0030] Fig.15 is Fig.14 A schematic diagram of the cross-sectional structure of the substrate after a dielectric material layer is formed on the substrate shown;

[0031] Fig.16 is Fig.15 The cross-sectional structure diagram of the substrate after a plurality of through holes are formed in the dielectric material layer is shown.

[0032] The above drawings include the following reference numerals:

[0033] 10. substrate; 20. epitaxial layer; 201. first surface; 21. first epitaxial layer; 22. second epitaxial layer; 30. trench gate structure; 31. gate; 311. gate material region; 32. gate oxide layer; 40. Schottky diode structure; 41. insulating layer; 42. doped layer; 421. first doped layer; 422. second doped layer; 51. first conductive portion; 511. first through hole; 52. second conductive portion; 521. second through hole; 53. conductive layer; 54. third conductive portion; 541. third through hole; 60. implantation region; 70. insulating portion; 71. dielectric material layer; 81. first trench; 82. second trench; 83. third trench; 84. fourth trench; 85. fifth trench; 91. first insulating layer; 911. first insulating region; 92. second insulating layer; 921. second insulating region. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] As described in the background technology, in the prior art, SiC MOS devices have a thin gate oxide layer, a poor anti-static breakdown capability of the device gate, and a large leakage current when the device is turned on, which increases the loss of the device. In order to solve the above problems, the present application provides a trench power device and a method for preparing a trench power device.

[0038] According to an embodiment of the present application, a trench power device is provided, such as Figure 1 to Figure 2 As shown, the trench power device includes: a substrate 10; an epitaxial layer 20, the epitaxial layer 20 is located on one side of the substrate 10, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22 stacked along a first direction A, the first epitaxial layer 21 has a first doping type, the second epitaxial layer 22 has a second doping type, the epitaxial layer 20 has a first surface 201 away from the substrate 10, and the first direction A is the direction from the substrate 10 to the epitaxial layer 20; at least one trench gate structure 30, the trench gate structure 30 is located in the epitaxial layer 20, the surface of the trench gate structure 30 away from the substrate 10 is located in the first surface 201, the surface of the trench gate structure 30 close to the substrate 10 is in contact with the first epitaxial layer 21, the trench gate structure 30 includes a gate 31 and a gate oxide layer 32, the gate oxide layer 32 is located at the gate 31 in the second The gate oxide layer 32 is located on two surfaces opposite to each other in a direction B on a side of the gate electrode 31 close to the substrate 10, and the second direction B is parallel to the first surface 201; a Schottky diode structure 40, the Schottky diode structure 40 is located on one side of the trench gate structure 30 in the second direction B, the Schottky diode structure 40 includes an insulating layer 41 and a multi-layer doped layer 42 stacked along a first direction A, the insulating layer 41 is located on a side of the doped layer 42 close to the substrate 10, and any two adjacent doped layers 42 have different doping types, wherein the doped layer 42 having the maximum distance from the substrate 10 in the first direction A is a first doped layer 421, and any one of the remaining doped layers 42 is a second doped layer 422, the second doped layer 422 is in contact with the gate electrode 31, and the insulating layer 41 is in contact with the gate oxide layer 32.

[0039] In the above trench power device, the Schottky diode structure is located on one side of the trench gate structure in the second direction, so that the Schottky barrier diode (SBD) is integrated into the trench power device, which can protect the gate. Specifically, the Schottky diode structure includes multiple doping regions and any two adjacent doping layers have different doping types, so that the Schottky diode structure includes at least one PN junction, and the second doping layer in the multiple doping layers is connected to the gate to form a conduction circuit. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, thereby improving the antistatic ability of the trench gate structure. In addition, only the second doping layer is connected to the gate, which reduces the contact area between the gate and the Schottky diode structure, so that the trench power device has a smaller leakage current in the turned-on state, thereby reducing the conduction loss of the device.

[0040] Specifically, the breakdown voltage of the Schottky diode structure is greater than the gate turn-on voltage and less than the gate oxide layer breakdown voltage. Under normal working conditions, the on and off of the trench power device will not be affected by the Schottky diode structure; if the gate voltage exceeds the safe range, the integrated Schottky diode structure will turn on, and the current will be released through the PN junction in the Schottky diode structure, protecting the gate oxide layer from breakdown.

[0041] The thickness of the second epitaxial layer is 0.5 μm to 1.5 μm, and the depth of the trench gate structure in the first direction is less than 2 μm, wherein the depth of the trench gate structure in the first direction is greater than the thickness of the second epitaxial layer, so as to form a MOS structure.

[0042] In some optional embodiments, the material of the gate includes doped polysilicon material, wherein the doping type includes P-type doping and N-type doping.

[0043] Specifically, by adjusting the type and concentration of doping elements, the work function of polysilicon can be precisely adjusted, thereby achieving precise control of the threshold voltage; polysilicon is process compatible with silicon and can be annealed at high temperatures, which helps to reduce defects at the contact surface between the gate and the trench and improve the reliability and stability of the device; during the high-temperature process, polysilicon can maintain stable performance and machinability, is not prone to melting or deformation, and will not have problems such as wafer breakage, thereby ensuring the preparation quality of the device.

[0044] In some optional embodiments, the second doping layer and the gate have different doping types.

[0045] Specifically, the contact between the gate and doping region of different doping types accelerates the speed of carriers and effectively improves the conductivity. In addition, the gate material has a high carrier affinity and has a strong attraction to carriers, which can generate carrier transport characteristics at the contact interface, thereby improving the performance of the device.

[0046] Exemplarily, the gate material is N-type polysilicon, and the doping region material in contact with the gate is P-type silicon carbide. Among them, N-type polysilicon has a higher electron mobility, and can improve the conductivity of the contact surface with P-type silicon carbide. N-type polysilicon has a higher hole affinity and a lower electron affinity, which can make the holes in P-type silicon carbide have a stronger attraction, produce a stronger transmission characteristic at the contact surface, and improve the performance of the device.

[0047] In some optional embodiments, the doping type of the second doping layer is P type.

[0048] Specifically, the contact between the P-type doped region and the conductive part can improve the conductivity between the conductive part and the Schottky diode structure. When the P-type semiconductor contacts the metal, the free electrons in the metal will diffuse into the semiconductor and form a charge balance with the holes in the P-type doped region, so that the contact between the P-type doped region and the conductive part has a very small contact resistance, thus providing a good conductive channel and improving the conductive performance.

[0049] In some optional embodiments, the trench power device further includes: a plurality of conductive parts, the plurality of conductive parts at least contacting the first doping layer and the gate, wherein isolation regions are provided between the conductive parts.

[0050] Specifically, the plurality of conductive portions are source electrodes of a trench power device, wherein, Figure 1 to Figure 2 As shown, the multiple conductive parts may include a first conductive part 51 and a second conductive part 52. The first conductive part 51 contacts the first doped layer 421. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on, and the current will flow into the Schottky diode structure through the second doped layer 422 and flow out through the first conductive part 51, so that the current is released; the second conductive part 52 contacts the gate 31 to provide the device with a gate voltage. The gate is connected to the source metal in series through the integrated SBD, which can ensure the normal operation of the device. In the case of high static electricity, the SBD is turned on, and the current is released through the source, and static electricity will not break through the gate oxide.

[0051] In some specific embodiments, such as Figure 1 to Figure 2 As shown, the device further includes an insulating portion 70, which is located in the isolation region between the plurality of conductive portions. The insulating portion 70 prevents the conductive portions from being short-circuited, thereby forming a protection circuit.

[0052] Specifically, the material of the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0053] In some specific embodiments, such as Figure 1 to Figure 2 As shown, the trench power device further includes a conductive layer 53 . The conductive layer 53 is located on a side of the substrate 10 away from the epitaxial layer 20 , and can serve as a drain electrode of the trench power device.

[0054] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to any one of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals or alloy materials. The conductive part includes a layer of conductive material or multiple layers of conductive materials. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0055] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, wherein the thickness of each layer is 0.1μm~0.2μm / 0.1μm~0.2μm / 0.1μm~0.2μm / 3μm~6μm, respectively, the first conductive part contacts the first doped layer to form an ohmic contact, the second conductive part contacts the gate to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0056] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the second doping layer 422 is located on a side of the remaining doping layers 42 close to the substrate 10 , and the second doping layer 422 is in contact with the insulating layer 41 .

[0057] Specifically, in the Schottky diode structure, multiple doped layers can form at least one PN junction. When there is one PN junction, the second doped layer is in contact with the insulating layer and the gate, respectively, and the first doped layer and the second doped layer form a PN junction; when there are multiple PN junctions, the multiple PN junctions form a series relationship, and the second doped layer is in contact with the insulating layer and the gate, respectively, then the current can flow through the multiple series-connected PN junctions, thereby making full use of the series relationship of the multiple PN junctions, reducing cost waste, and at the same time, saving chip area.

[0058] In some optional embodiments, the number of the doped layers is n, where n is greater than or equal to four.

[0059] Specifically, the breakdown voltage of the Schottky diode structure can be adjusted by setting the number of doping layers to protect the trench gate structure in different applications. This is because any two adjacent doping layers have different doping types, so that multiple groups of PN junctions in series can be formed in the Schottky diode structure. For example, the doping layer has 4 layers, the first doping layer and the second doping layer form the first group of PN junctions, the third doping layer and the fourth doping layer form the second group of PN junctions, and the first group of PN junctions and the second group of PN junctions form a series relationship. Trench power devices have different requirements for the breakdown voltage of Schottky diodes in different applications. For example, the application requires the Schottky diode structure to have a breakdown voltage of 36V. If the breakdown voltage of each group of PN junctions is the same and is 12V, then a Schottky diode structure with 3 groups of PN junctions in series is required to protect the gate oxide layer from breakdown.

[0060] In some optional embodiments, the thickness of the insulating layer in the first direction is a first thickness, the gate oxide layer located on the sidewall of the gate has a second thickness in the second direction, and the first thickness is greater than the second thickness.

[0061] Specifically, the insulating layer can isolate multiple doped layers and control the direction of current. The insulating layer has a thicker thickness, which can increase the current isolation between the doped layer and the first epitaxial layer. At the same time, it can ensure the anti-breakdown capability of the bottom of the trench, improve the breakdown performance of the device, and increase the reliability of the trench power device.

[0062] In some optional implementations, the gate oxide layer on the side of the gate close to the substrate has a third thickness in the first direction, and the third thickness is greater than the second thickness, wherein the second thickness is 50 μm to 100 μm.

[0063] Specifically, in the trench power device, electric field concentration is likely to occur at the bottom of the trench gate due to the gate oxide quality and the trench corner, resulting in deterioration of the breakdown characteristics of the gate oxide layer at the bottom of the trench. In the above embodiment, by increasing the thickness of the first region of the gate oxide layer located at the bottom of the gate, the voltage resistance performance of the bottom of the trench is increased, which not only realizes the protection of the gate, but also avoids the voltage resistance failure of the gate oxide at the bottom of the trench, thereby improving the reliability of the trench gate structure, and further increasing the reliability of the trench power device.

[0064] In some specific embodiments, the first thickness and the third thickness are equal.

[0065] Specifically, during the preparation of the trench power device, the same deposition process can be used to form an insulating layer at the bottom of the trench and a gate oxide layer at the bottom of the gate, which simplifies the process and improves the reliability of the device.

[0066] In some optional embodiments, the doping layer having the first doping type in the doping layer is a first type doping layer, the doping layer having the second doping type in the doping layer is a second type doping layer, the doping concentration of the first type doping layer is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the second type doping layer is greater than the doping concentration of the second epitaxial layer.

[0067] Specifically, in trench power devices, the epitaxial layer, as the voltage-resistant layer of the MOS structure, should have a lower doping concentration to ensure the voltage-resistant performance of the epitaxial layer, so the epitaxial layer has a smaller doping concentration. The doping concentration of the doping concentration cannot be lower than the doping concentration of the epitaxial layer to ensure that the Schottky diode structure can be normally turned on when the gate voltage exceeds the safe range, so as to protect the trench gate structure.

[0068] The doping concentration range of the first type doping layer and the second type doping layer is 1.0×10 17 cm -3 ~1.0×10 19 cm -3 .

[0069] In an embodiment of the present application, if the first doping type is P-type, the second doping type is N-type, or the first doping type is N-type, the second doping type is P-type, wherein N-type doping is the addition of pentavalent elements into the semiconductor material, and the pentavalent elements include but are not limited to phosphorus, arsenic and antimony; P-type doping is the addition of trivalent elements into the semiconductor material, and the trivalent elements include but are not limited to boron, aluminum and gallium. The specific doping elements are not specifically limited in this application.

[0070] Specifically, the doping concentration of the first doping type layer and the second doping type layer and the breakdown voltage of the PN formed by the two satisfy the formula: , where k is a constant, is the breakdown voltage of the PN junction, is the doping concentration of the first doping type layer, The above formula shows that the breakdown voltage of the PN junction is inversely proportional to the product of the doping concentrations of the first doping type layer and the second doping type layer, that is, when the doping concentrations of the first doping type layer and the second doping type layer increase, the breakdown voltage of the PN junction decreases.

[0071] In addition, the doping concentration of the first doping type layer and the doping concentration of the second doping type layer can also be adjusted by the above formula, so that the Schottky diode structure has different breakdown voltages to meet the gate protection requirements of different products. It should be noted that the above formula is a simplified formula, and the breakdown voltage of the PN junction is also affected by factors such as the properties, temperature and structure of the semiconductor material. Those skilled in the art will make adjustments according to the specific circumstances of the actual application.

[0072] In some optional embodiments, such as Figure 2 As shown, the multi-layer doped layer 42 has a plurality of first widths H in the second direction B near the surface of the substrate 10 , and the plurality of first widths H decrease along the first direction A.

[0073] Specifically, in the above embodiment, the multiple first widths H of the multi-layer doped layer 42 are decreasing along the second direction B, which can reduce the leakage current of the Schottky diode. When the PN junction is reverse biased, minority carriers will generate reverse leakage current due to diffusion and drift. The leakage current of the PN junction is proportional to the contact area of ​​the P region and the N region. Therefore, if the multiple first widths H decrease along the second direction B, the leakage current of the multiple groups of PN junctions decreases along the second direction B, thereby reducing the leakage current of the Schottky diode structure.

[0074] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the device further includes an implantation region 60 , which is located in the second epitaxial layer 22 and contacts a surface of the trench gate structure 30 away from the Schottky diode structure 40 , and has a first doping type.

[0075] Specifically, the injection region and the second epitaxial layer have different doping types, and both the injection region and the second epitaxial layer are in contact with the gate oxide of the trench gate structure, that is, the injection region, the second epitaxial layer and the trench gate structure constitute a MOS structure, wherein, by controlling the magnitude of the gate voltage, a channel is formed in the region where the second epitaxial layer contacts the gate oxide layer, thereby controlling the flow of electrons (or holes).

[0076] The doping concentration of the implanted region is 1.0×10 20 cm -3 ~1.0×10 21 cm -3 The specific concentration is not limited in this application.

[0077] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the conductive portion 50 further includes a third conductive portion 54 , and the third conductive portion 54 is in contact with the implantation region 60 .

[0078] Specifically, the third conductive portion serves as a source and can provide current for the MOS structure.

[0079] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the MOS device further includes an insulating portion 70, which is located in the spacing region. The insulating portion 70 serves to isolate the plurality of conductive portions.

[0080] Specifically, the material of the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0081] The insulating part includes a layer of material or multiple layers of material, and the thickness of the insulating part is 0.3 μm to 2 μm, which is not specifically limited in this application.

[0082] According to another aspect of the present application, a method for preparing a trench power device is provided, which is used to prepare any trench power device, such as Figure 3 As shown, the preparation method comprises:

[0083] Step S101: providing a substrate;

[0084] Step S102: forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface facing away from the substrate, and the first direction being a direction from the substrate to the epitaxial layer;

[0085] Step S103: forming at least one trench gate structure in the epitaxial layer, wherein a surface of the trench gate structure facing away from the substrate is located in the first surface, and a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is located on two surfaces of the gate opposite to each other in a second direction and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface;

[0086] Step S104: forming a Schottky diode structure on one side of the trench gate structure in the second direction, wherein the Schottky diode structure comprises an insulating layer and a plurality of doped layers stacked along a first direction, wherein the insulating layer is located on a side of the doped layer close to the substrate, and any two adjacent doped layers have different doping types, wherein the doped layer having the maximum distance from the substrate in the first direction is the first doped layer, and one of the remaining doped layers is the second doped layer, wherein the second doped layer is in contact with the gate, and the insulating layer is in contact with the gate oxide layer.

[0087] The above-mentioned preparation method of the embodiment of the present application is adopted, on the basis of the traditional trench power device, multiple epitaxial processes are adopted to realize the integration of Schottky diode structure on one side of the gate, and the antistatic ability of the gate is improved. Among them, a trench gate structure and a Schottky diode structure are formed in the trench, and the Schottky diode structure includes multiple doping regions and any two adjacent doping layers have different doping types, so that at least one PN junction is included in the Schottky diode structure, and the second doping layer in the multi-layer doping layer is connected to the gate to form a conduction circuit. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, and improve the antistatic ability of the trench gate structure. In addition, only the second doping layer is connected to the gate, which reduces the contact area between the gate and the Schottky diode structure, so that the trench power device has a smaller leakage current in the turned-on state, reducing the conduction loss of the device. In addition, the adjustment is made by adjusting the epitaxial doping concentration to meet the protection requirements of different gates.

[0088] The following will describe in more detail the exemplary embodiments of the method for preparing the trench power device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0089] First, if Figure 4 As shown, step S101 is performed: providing a substrate 10 .

[0090] Specifically, the materials of the substrate 10 include silicon carbide, silicon, gallium nitride, gallium oxide, gallium arsenide, aluminum nitride and the like, and those skilled in the art can reasonably select them according to actual needs, and no specific limitation is made without application. The substrate has a first doping type.

[0091] Exemplarily, the substrate includes a doped SiC substrate to form an ohmic contact at the source, which can reduce the forward voltage drop of the diode structure and increase the breakdown voltage.

[0092] After providing the substrate, as Figure 5 As shown, step S102 is performed: an epitaxial layer 20 is formed on one side of the substrate 10 .

[0093] Specifically, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22 which are stacked, the first epitaxial layer 21 has a first doping type, and the second epitaxial layer 22 has a second doping type. The thickness of the second epitaxial layer is 0.5 μm to 1.5 μm.

[0094] In other optional embodiments, the process of forming the first epitaxial layer 21 and the second epitaxial layer 22 includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, so it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate and has low cost. The deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0095] After the epitaxial layer is formed, step S103 is performed: forming a trench gate structure.

[0096] Specifically, the steps of forming the trench gate structure may include: first, Figure 6 As shown, a first trench 81 is formed in the epitaxial layer 20 by an etching process, and the bottom surface of the first trench 81 exposes the first epitaxial layer 21; then, as shown in FIG. Figure 7 As shown in FIG. 1 , a first insulating layer 91 covering the sidewalls and the bottom surface is formed in the first trench 81, and the remaining area in the first trench 81 is the second trench 82; then, as shown in FIG. Figure 8 As shown, the gate 31 is formed on the sidewall of the second trench 82 .

[0097] In some specific embodiments, such as Fig. 9 As shown, the specific steps of forming the gate 31 and the first insulating layer 91 in the above steps may include:

[0098] Step S1031: Fig. 9As shown in (a), a first trench 81 is formed in the epitaxial layer 20 by an etching process, and a bottom surface of the first trench 81 exposes a portion of the first epitaxial layer 21, wherein: Fig. 9 (a) with Figure 6 The same preparation steps;

[0099] Step S1032: Fig. 9 As shown in (b), an insulating material is filled in the first trench 81 by a deposition process to form a first insulating region 911;

[0100] Step S1033: Fig. 9 As shown in (c), a second trench 82 is formed in the first insulating region 911 by an etching process, and the remaining first insulating region constitutes a first insulating layer 91, wherein: Fig. 9 (c) with Figure 7 The same preparation steps;

[0101] Step S1034: Fig. 9 As shown in (d), a deposition process is used to fill the second trench 82 with a gate material to form a gate material region 311;

[0102] Step S1035: Fig. 9 As shown in (e), a third trench 83 is formed in the gate material region 311 by an etching process. The third trench 83 exposes the first insulating layer 91 at the bottom, and the remaining gate material constitutes the gate 31. Fig. 9 (e) with Figure 8 The preparation steps are the same.

[0103] Then, if Fig.10 As shown, a portion of the first insulating layer 91 located at the bottom of the third trench 83 constitutes an insulating layer 41, a second doping layer 422 is formed at the bottom of the third trench 83, and the second doping layer 422 is in contact with the gate 31 and the insulating layer 41 respectively, and the remaining area in the third trench 83 is a fourth trench 84; then, as shown Fig.11 As shown, a second insulating layer 92 is formed on the side wall of the gate 31, wherein a portion of the first insulating layer 91 located on the side of the gate 31 close to the substrate 10, a portion of the first insulating layer 91 located on the side of the gate 31, and the second insulating layer 92 located on the other side of the gate 31 constitute a gate oxide layer 32, and the gate oxide layer 32 and the gate constitute a trench gate structure 30.

[0104] More specifically, if Fig.12 As shown, the specific steps of forming the second insulating layer 92 may include:

[0105] Step S1041: Fig.12 As shown in (a), the epitaxial growth process is used in Fig.10The fourth trench 84 is filled with insulating material to form a second insulating region 921;

[0106] Step S1042: Fig.12 As shown in (b), a fifth trench 85 is formed in the second insulating region 921 by an etching process, and the remaining second insulating region 921 constitutes a second insulating layer 92, wherein: Fig.12 (b) with Fig.11 The preparation steps are the same.

[0107] The depth of the first trench is less than 2 μm, and the bottom surface of the first trench exposes the first epitaxial layer. In addition, the thickness of the first insulating layer located at the bottom surface of the first trench in the first direction is greater than the thickness of the first insulating layer located at the side wall of the first trench in the second direction, so as to ensure the anti-puncture capability of the bottom of the trench, and the thickness of the first insulating layer located at the side wall of the first trench in the second direction is 50 nm to 100 nm.

[0108] Specifically, the above-mentioned etching process includes but is not limited to dry etching and wet etching, wherein dry etching includes physical etching, chemical etching and chemical-physical etching, and physical etching includes ion beam etching, plasma etching, reactive ion etching, etc. Technical personnel in this field can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0109] In some optional embodiments, the gate material includes doped polysilicon material, wherein the doping type includes P-type doping and N-type doping. By adjusting the type and concentration of the doping element, the work function of polysilicon can be accurately adjusted, thereby achieving precise control of the threshold voltage; polysilicon is compatible with silicon processes and can be annealed at high temperatures, which helps to reduce defects in the contact surface between the gate and the groove and improve the reliability and stability of the device; during the high-temperature process, polysilicon can maintain stable performance and processability, is not prone to melting or deformation, and will not have problems such as wafer breakage, thereby ensuring the preparation quality of the device.

[0110] After the trench gate structure is formed, step S104 is performed: forming a Schottky diode structure.

[0111] Specifically, the step of forming the Schottky diode structure may include: then, as Fig.13 As shown, in Fig.11 or Fig.12 In the fifth trench 85 shown in (b), a plurality of doping layers 42 are formed by multiple epitaxial growth processes, wherein any two adjacent doping layers 42 have different doping types, and the doping layers 42 include a first doping layer 421 and a second doping layer 422, wherein the first doping layer 421 is the doping layer 42 with the maximum distance from the substrate 10, and the second doping layer 422 is the doping layer 42 with the minimum distance from the substrate 10.

[0112] In the above preparation method, the Schottky diode structure and the trench gate structure are formed in the same first trench, that is, the integrated Schottky diode structure is located in the trench cell structure, which reduces the chip area and reduces the manufacturing cost.

[0113] The process of forming the doped region includes but is not limited to a deposition process and an epitaxial growth process.

[0114] In some optional embodiments, such as Fig.14 As shown, the preparation method further includes step S105: forming an implantation region 60.

[0115] Specifically, the process of forming the second implantation region includes an ion implantation process. The implantation region and the second epitaxial layer have different doping types, and both the implantation region and the second epitaxial layer are in contact with the gate oxide of the trench gate structure, that is, the implantation region, the second epitaxial layer and the trench gate structure constitute a MOS structure, wherein, by controlling the magnitude of the gate voltage, a channel is formed in the region where the second epitaxial layer contacts the gate oxide layer, thereby controlling the flow of electrons (or holes). The doping concentration of the implantation region is 1.0×10 20 cm -3 ~1.0×10 21 cm -3 The specific concentration is not limited in this application.

[0116] In some optional implementations, the preparation method further includes step S106: forming a conductive portion.

[0117] Specifically, the steps of forming the conductive part include: first, Fig.15 As shown, in Fig.14 A dielectric material layer 71 is formed on the substrate as shown; then, Fig.16 As shown, a plurality of through holes penetrating the dielectric material layer 71 are formed in the dielectric material layer 71 by etching process, wherein the plurality of through holes include a first through hole 511, a second through hole 521 and a third through hole 541, the first through hole 511 exposes the first doping layer 421, the second through hole 521 exposes the gate 31, the third through hole 541 exposes the implantation region 60, and the remaining dielectric material layer 71 constitutes the insulating portion 70; then, as shown Figure 1 As shown, a plurality of conductive parts are formed in a plurality of through holes by a deposition process, a first conductive part 51 is formed in the first through hole 511 , a second conductive part 52 is formed in the second through hole 521 , and a third conductive part 54 is formed in the third through hole 541 .

[0118] In the above embodiment, Figure 1 As shown, the preparation method further includes step S107: forming a conductive layer 53.

[0119] Specifically, a deposition process is used to deposit a conductive material on a side of the substrate 10 facing away from the epitaxial layer 20 to form the conductive layer 53 .

[0120] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to any one of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals or alloy materials. The conductive part includes a layer of conductive material or multiple layers of conductive materials. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0121] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, wherein the thickness of each layer is 0.1μm~0.2μm / 0.1μm~0.2μm / 0.1μm~0.2μm / 3μm~6μm, respectively, the first conductive part contacts the first doped layer to form an ohmic contact, the second conductive part contacts the gate to form an ohmic contact, the third conductive part contacts the injection region to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0122] Specifically, the material of the dielectric material or the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0123] The following will further illustrate a trench power device formed by the method for preparing a trench power device of the present application in conjunction with an embodiment.

[0124] The method for preparing a trench power device provided in this embodiment comprises the following steps:

[0125] Provide an N-type SiC substrate 10, such as Figure 4 As shown;

[0126] A first N-type epitaxial layer 21 and a second P-type epitaxial layer 22 are formed on an N-type SiC substrate 10 by using a double epitaxial growth process. The first N-type epitaxial layer 21 and the second P-type epitaxial layer 22 constitute an epitaxial layer 20. Figure 5 As shown;

[0127] A first trench 81 is formed in the epitaxial layer 20 by an etching process. Fig. 9 (a) as shown;

[0128] The first trench 81 is filled with silicon oxide by a deposition process to form a first insulating region 911. Fig. 9(b) as shown;

[0129] The second trench 82 is formed in the first insulating region 911 by an etching process, and the remaining first insulating region 911 constitutes the first insulating layer 91. Fig. 9 (c) as shown;

[0130] The N-type polysilicon material is filled in the second trench 82 by a deposition process to form a gate material region 311. Fig. 9 (d) as shown;

[0131] A trench is formed in the gate material region 311 by an etching process, and the remaining gate material region constitutes the gate 31. The remaining region in the second trench 82 is the third trench 83. Fig. 9 (e) as shown;

[0132] Using epitaxial growth process Fig. 9 A P-type second doping layer 422 is formed in the third trench 83 shown in (e), and the remaining area of ​​the third trench 83 constitutes a fourth trench 84. Fig.10 As shown;

[0133] The fourth trench 84 is filled with silicon oxide by a deposition process to form a second insulating region 921. Fig.12 (a) as shown;

[0134] The fifth trench 85 is formed in the second insulating region 921 by an etching process. The fifth trench 85 exposes the second doping layer 422. The remaining second insulating region 921 constitutes the second insulating layer 92. Fig.12 (b) as shown;

[0135] Using epitaxial growth process Fig.12 In the fifth trench 85 shown in (b), a stacked N-type doping layer 42, a P-type doping layer 42, an N-type doping layer 42 and a P-type first doping layer 421 are formed respectively, as shown in FIG. Fig.13 As shown;

[0136] An N-type implantation region 60 is formed in the second epitaxial layer 22 near the trench gate structure 30 by an ion implantation process. Fig.14 As shown;

[0137] The deposition process is used in Fig.14 A silicon oxide layer is formed on the substrate as shown to form a dielectric material layer 71, as shown in FIG. Fig.15 As shown;

[0138] A plurality of through holes penetrating the dielectric material layer 71 are formed in the dielectric material layer 71 by etching process, wherein the plurality of through holes include a first through hole 511, a second through hole 521 and a third through hole 541, wherein the first through hole 511 exposes the first doping layer 421, the second through hole 521 exposes the gate 31, and the third through hole 541 exposes the implantation region 60. Fig.16 As shown;

[0139] A deposition process is used to fill a plurality of through holes with Ni / Ti / TiN / Al material layers to form a plurality of conductive portions, wherein a first conductive portion 51 is formed in the first through hole 511, a second conductive portion 52 is formed in the second through hole 521, and a third conductive portion 54 is formed in the third through hole 541. Figure 1 As shown;

[0140] A conductive layer 53 of Ni / Ti / Ni / Ag structure is formed on the side of the substrate 10 away from the epitaxial layer 20 by a deposition process. Figure 1 shown.

[0141] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0142] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A trench power device, characterized in that: include: substrate; An epitaxial layer, the epitaxial layer is located on one side of the substrate, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer has a first doping type, the second epitaxial layer has a second doping type, the epitaxial layer has a first surface away from the substrate, and the first direction is a direction from the substrate to the epitaxial layer; at least one trench gate structure, the trench gate structure is located in the epitaxial layer, the surface of the trench gate structure facing away from the substrate is located in the first surface, the surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is located on two surfaces of the gate opposite to each other in a second direction and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface; A Schottky diode structure, wherein the Schottky diode structure is located on one side of the trench gate structure in the second direction, and the Schottky diode structure includes an insulating layer and a plurality of doped layers stacked along the first direction, wherein the insulating layer is located on a side of the doped layer close to the substrate, and any two adjacent doped layers have different doping types, wherein the doped layer having the maximum distance from the substrate in the first direction is the first doped layer, and any one of the remaining doped layers is the second doped layer, wherein the second doped layer is in contact with the gate, and the insulating layer is in contact with the gate oxide layer.

2. The trench power device according to claim 1, characterized in that: The second doping layer is located on a side of the remaining doping layers close to the substrate, and the second doping layer is in contact with the insulating layer.

3. The trench power device according to claim 1, characterized in that: The number of the doped layers is n, wherein n is greater than or equal to four.

4. The trench power device according to claim 1, characterized in that: The thickness of the insulating layer in the first direction is a first thickness, the gate oxide layer located on the sidewall of the gate has a second thickness in the second direction, and the first thickness is greater than the second thickness.

5. The trench power device according to claim 1, characterized in that: The doping layer having the first doping type in the doping layer is a first type doping layer, and the doping layer having the second doping type in the doping layer is a second type doping layer, the doping concentration of the first type doping layer is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the second type doping layer is greater than the doping concentration of the second epitaxial layer.

6. The trench power device according to claim 1, characterized in that: The multiple layers of the doped layers have a plurality of first widths in the second direction near the surface of the substrate, and the plurality of first widths decrease along the first direction.

7. The trench power device according to any one of claims 1 to 6, characterized in that: The device further comprises: An implantation region, wherein the implantation region is located in the second epitaxial layer, and the implantation region is in contact with a surface of the trench gate structure that is away from the Schottky diode structure, and the implantation region has the first doping type.

8. A method for preparing a trench power device, characterized in that: Used to prepare the trench power device according to any one of claims 1 to 7, the preparation method comprising: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface facing away from the substrate, and the first direction being a direction from the substrate to the epitaxial layer; At least one trench gate structure is formed in the epitaxial layer, wherein a surface of the trench gate structure facing away from the substrate is located in the first surface, and a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate oxide layer is located on two surfaces of the gate that are opposite in a second direction and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface; A Schottky diode structure is formed on one side of the trench gate structure in the second direction, and the Schottky diode structure includes an insulating layer and a plurality of doped layers stacked along the first direction, the insulating layer is located on a side of the doped layer close to the substrate, and any two adjacent doped layers have different doping types, wherein the doped layer having the maximum distance from the substrate in the first direction is the first doped layer, and one of the remaining doped layers is the second doped layer, the second doped layer is in contact with the gate, and the insulating layer is in contact with the gate oxide layer.

9. The preparation method according to claim 8, characterized in that: The step of forming the trench gate structure comprises: forming a first trench in the epitaxial layer by an etching process, wherein a bottom surface of the first trench exposes the first epitaxial layer; forming a first insulating layer covering the sidewalls and the bottom surface in the first trench, and the remaining area in the first trench is a second trench; forming the gate on a sidewall of the second trench; A second insulating layer is formed on the side wall of the gate, wherein the first insulating layer on the side of the gate close to the substrate, the first insulating layer on the side of the gate and the second insulating layer on the other side of the gate constitute the gate oxide layer.

10. The preparation method according to claim 9, characterized in that: The remaining area in the second trench is a third trench, and the steps of forming the Schottky diode structure include: forming the first doping layer on the bottom surface of the third trench, the first doping layer is in contact with the gate and the insulating layer respectively, and the remaining area in the third trench is the fourth trench; forming the second insulating layer on the sidewall of the fourth trench, and the remaining area in the fourth trench is the fifth trench; A plurality of doping layers are formed in the fifth trench by using a multiple deposition process, wherein any two adjacent doping layers have different doping types.

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