Display device

Abstract

A display device is provided. The display device includes: display pixels formed in an image display area of a display panel; a gate driving circuit formed in the image display area and configured to supply a gate signal to the display pixels; a display driving circuit configured to supply a data voltage to the data lines in the image display area through fan-out lines arranged in the non-display area of the display panel, and configured to supply a gate control signal to the gate driving circuit through gate control lines arranged in the non-display area; and a driving voltage line arranged in the non-display area and configured to supply a driving voltage to the gate driving circuit, in which at least one of the gate control lines intersects one or more of the fan-out lines in one side direction of the image display area corresponding to an arrangement direction of the display driving circuit.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to a display device. Background Art

[0002] As the information society develops, consumer demand for display devices for displaying images in various forms is increasing. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among the flat panel display devices, the light emitting display device may include a light emitting element, wherein each of the pixels of the display panel may emit light by itself, thereby displaying an image without a backlight unit or the like.

[0004] The display device may include a display area and a non-display area around the display area. A pixel circuit for displaying an image may be located in the display area. On the other hand, various drive circuits for driving the pixel circuit may be located in the non-display area corresponding to the dead zone of the display device. Recently, a display device with a relatively wide display surface at a limited size may be desired. To this end, a method for minimizing or reducing the border area including the dead zone may be desired.

[0005] However, in mobile display devices such as smartphones and tablet PCs, there may be limitations in reducing the dead zone since drive circuits and various lines are concentratedly arranged in one narrow side direction compared to large-screen display devices such as monitors.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some embodiments of the present disclosure include a line arrangement structure that may be able to reduce a dead area of ​​a display panel used in a mobile display device such as a smartphone or a tablet PC.

[0008] Aspects of some embodiments of the present disclosure may also include a display device capable of preventing or reducing the occurrence of electromagnetic coupling between lines that overlap or intersect each other.

[0009] However, aspects according to embodiments of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure relates by referring to the detailed description of the present disclosure given below.

[0010] According to some embodiments of the present disclosure, a display device includes: display pixels formed in an image display area of ​​a display panel; a gate driving circuit formed in the image display area to supply a gate signal to the display pixels; a display driving circuit that supplies a data voltage to a data line in the image display area through a fan-out line arranged in a non-display area of ​​the display panel, and supplies a gate control signal to the gate driving circuit through a gate control line arranged in the non-display area; and a driving voltage line arranged in the non-display area to supply a driving voltage to the gate driving circuit, wherein at least one of the gate control lines intersects with one or more of the fan-out lines in a side direction of the image display area corresponding to the arrangement direction of the display driving circuit.

[0011] According to some embodiments of the present disclosure, a display device includes: a display panel, which includes an image display area and a non-display area; display pixels, which are formed in the image display area; a gate driving circuit, which is formed in the image display area to supply a gate signal to the display pixel; a display driving circuit, which supplies a data voltage to a data line in the image display area through a fan-out line arranged in the non-display area, and supplies a gate control signal to the gate driving circuit through a gate control line arranged in the non-display area; and a driving voltage line, which is arranged in the non-display area to supply a driving voltage to the gate driving circuit, wherein at least one of the gate control lines intersects with one or more of the fan-out lines in a side direction of the image display area corresponding to the arrangement direction of the display driving circuit, and at least one of the driving voltage lines intersects with one or more of the fan-out lines in a side direction of the image display area corresponding to the arrangement direction of the display driving circuit.

[0012] According to some embodiments, at least one of the gate control lines intersects one or more of the data lines in the image display area in a lateral direction corresponding to an arrangement direction of the display driving circuit.

[0013] According to some embodiments, the gate control line includes a gate start signal transmission line and multiple clock signal transmission lines, and the gate start signal transmission line and one or more of the multiple clock signal transmission lines intersect with one or more data lines or intersect with one or more fan-out lines.

[0014] In a display device according to some embodiments of the present disclosure, a dead zone caused by an embedded circuit (eg, a gate driving circuit (or a scan driving circuit)) applied to a display panel of a mobile display device can be reduced by forming the embedded circuit in the display area.

[0015] Furthermore, by improving the arrangement structure of the lines overlapping or intersecting each other, the occurrence of electromagnetic coupling between the lines overlapping or intersecting each other can be prevented or reduced, and the reliability can be relatively improved.

[0016] However, the features of the embodiments according to the present disclosure are not limited to those specifically described herein. The above and other features of the embodiments according to the present disclosure will become more apparent to those skilled in the art by referring to the claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0018] Figure 1 is a perspective view illustrating a display device according to some embodiments;

[0019] Figure 2 is a plan view illustrating a display device according to some embodiments;

[0020] Figure 3 is a side view illustrating a display device according to some embodiments;

[0021] Figure 4 is a schematic diagram illustrating how Figures 1 to 3 A layout view of the display panel shown in ;

[0022] Figure 5 is an illustration of some embodiments wherein Figure 4 A layout view of an enlarged AA region where data lines, gate control lines, and power lines intersect;

[0023] Figure 6 It is a specific illustration according to some embodiments Figure 5 The image shown in shows a layout view of the area;

[0024] Figure 7 is a diagram showing the formation of a partition for each block according to some embodiments Figures 4 to 6 a view of a gate drive circuit in an image display area;

[0025] Figure 8 is a diagram illustrating a method according to some embodiments Figure 5 A layout view of a more magnified intersection area of ​​data lines, gate control lines, and power lines;

[0026] Fig. 9 is a specific illustration of some embodiments of the present invention Figure 8 A layout view of a BB region where a data line intersects a gate control line;

[0027] Fig.10 is a diagram illustrating a method according to some embodiments Fig. 9 A cross-sectional view of a section taken along line CC' shown in FIG.

[0028] Fig.11 is a schematic diagram illustrating how Figures 1 to 3 A layout view of the display panel shown in ;

[0029] Fig.12 is an illustration of some embodiments wherein Fig.11 A layout view of an enlarged EE area where data lines, gate control lines, and power lines intersect;

[0030] Fig.13 is a specific illustration of some embodiments of the present invention Fig.12 A layout view of an EE region where a data line intersects a gate control line;

[0031] Fig.14 is a diagram illustrating a method according to some embodiments Fig.13 A cross-sectional view of a section taken along line FF' shown in FIG.

[0032] Fig.15 and Fig.16 is a perspective view illustrating a display device according to some embodiments of the present disclosure; and

[0033] Fig.17 and Fig.18 is a perspective view illustrating a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] Aspects of some embodiments of the present disclosure will now be more fully described below with reference to the accompanying drawings in which aspects of some embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be exhaustive and comprehensive, and will fully convey the scope of the present disclosure to those skilled in the art.

[0035] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0036] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0037] Each of the features of the various embodiments of the present disclosure can be combined or combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together in a related manner.

[0038] Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings.

[0039] Figure 1 is a perspective view illustrating a display device according to some embodiments. Figure 2 is a plan view illustrating a display device according to some embodiments, and Figure 3 is a side view illustrating a display device according to some embodiments.

[0040] refer to Figures 1 to 3 , the display device 10 according to some embodiments can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). Alternatively, the display device 10 according to some embodiments can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 according to some embodiments can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). Alternatively, the display device 10 according to some embodiments can be applied to an instrument panel of a vehicle, a central dashboard of a vehicle, a central information display (CID) located on the dashboard of a vehicle, an interior mirror display instead of a side mirror of a vehicle, or a display located on the rear surface of a front seat as entertainment for a rear seat of a vehicle.

[0041] The display device 10 according to some embodiments may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro light-emitting diode or a nano light-emitting diode (LED). Hereinafter, it is mainly described that the display device 10 according to some embodiments is an organic light-emitting display device, but the scope of application is not limited thereto.

[0042] The display device 10 according to some embodiments includes a display panel 100 , a display driving circuit 200 , a circuit board 300 , and a touch driving circuit 400 .

[0043] The display panel 100 may be formed in a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Here, the corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) meet are rounded with a curvature (e.g., a set or predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape with rounded corners, and may be other polygonal shapes, circular shapes, or elliptical shapes with rounded corners. The display panel 100 may be formed to be flat, but is not limited thereto according to embodiments of the present disclosure. For example, the display panel 100 includes a bent portion formed at the left and right distal ends and having a constant curvature or a variable curvature. In addition, the display panel 100 may be flexibly formed to be bent, curved, folded, or curled.

[0044] The display panel 100 includes a main area MA and a sub area SBA.

[0045] The main area MA includes a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA includes pixels for displaying an image. The sub-area SBA may protrude from one side of the main area MA in the second direction (Y-axis direction).

[0046] exist Figure 1 and Figure 2 The sub-area SBA is shown as being expanded, but the sub-area SBA can be Figure 3 , and in this case, the sub-region SBA may be arranged in the rear surface direction of the display panel 100. When the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the third direction (Z-axis direction) which is the thickness direction of the substrate SUB. The display driving circuit 200 may be located in the sub-region SBA.

[0047] refer to Figure 3 The display panel 100 includes a display module DU and a touch sensing unit TSU. The display module DU includes a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML and an encapsulation layer TFEL. The touch sensing unit TSU is formed on the front surface of the display module DU.

[0048] The thin film transistor layer TFTL may be located on the substrate SUB. The thin film transistor layer TFTL may be located in the main area MA and the sub-area SBA. The thin film transistor layer TFTL includes a thin film transistor.

[0049] The light emitting element layer EML may be located on the thin film transistor layer TFTL. The light emitting element layer EML may be located in the display area DA of the main area MA. The light emitting element layer EML includes a light emitting element located in the light emitting portion.

[0050] The encapsulation layer TFEL may be located on the light emitting element layer EML. The encapsulation layer TFEL may be located in the display area DA and the non-display area NDA of the main area MA. The encapsulation layer TFEL includes at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0051] The touch sensing unit TSU may be formed or mounted on the encapsulation layer TFEL. The touch sensing unit TSU may be located on the display area DA of the main area MA. The touch sensing unit TSU may sense a touch of a body part such as a finger or an electronic pen by using a touch electrode.

[0052] A cover window (not shown) for protecting the upper portion of the display panel 100 may be located on the touch sensing unit TSU. The cover window may be attached to the touch sensing unit TSU by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may also be made of an inorganic material such as glass, or may also be made of an organic material such as a plastic or polymer material. In order to prevent or reduce degradation of the visibility of an image due to reflection of external light, a polarizing layer may be additionally located between the touch sensing unit TSU and the cover window.

[0053] The display driving circuit 200 may generate signals and voltages for driving the display panel 100. The display driving circuit 200 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but the embodiments of the present disclosure are not limited thereto. For example, the display driving circuit 200 may be attached to the circuit board 300 in a chip on film (COF) manner.

[0054] The circuit board 300 may be attached to one end of the sub-area SBA formed in the display panel 100. Therefore, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 200. The display panel 100 and the display driving circuit 200 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0055] The touch driving circuit 400 may be located on the circuit board 300 instead of the display panel 100. In this case, the touch driving circuit 400 may be formed as an integrated circuit (IC) and attached to the circuit board 300.

[0056] The touch drive circuit 400 may be electrically connected to the touch electrodes of the touch sensing unit TSU. The touch drive circuit 400 applies a touch drive signal to the touch electrodes of the touch sensing unit TSU, and measures the charge change amount of the mutual capacitance of each of the touch nodes formed by the touch electrodes. For example, the touch drive circuit 400 measures the change in capacitance of a plurality of touch nodes according to the change in voltage magnitude or current amount of the touch sensing signal received through the touch electrodes. In this way, the touch drive circuit 400 may determine whether a user's touch is made, whether a user's approach is made, etc. according to the charge change amount of the mutual capacitance of each of the plurality of touch nodes. The user's touch indicates that the user's finger or an object such as an electronic pen is in direct contact with one surface of the cover window located on the touch sensing unit TSU. The user's approach indicates that the user's finger or an object such as an electronic pen is hovering over one surface of the cover window.

[0057] Figure 4 is a schematic diagram illustrating how Figures 1 to 3 For example, Figure 4 2 is a layout view illustrating a display area DA and a non-display area NDA of a display module DU before forming a touch sensing unit TSU.

[0058] The display area DA, which is an area configured to display an image, may be defined as a central area of ​​the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a gate driving circuit 210, a plurality of data lines DL, and a plurality of power lines VL.

[0059] The gate drive circuit 210 may be formed and located in the Y-axis direction or the X-axis direction in the display area DA. For example, the gate drive circuit 210 may be formed and located in the Y-axis direction, which is the direction in which the gate lines GL are spaced apart from each other. The gate drive circuit 210 sequentially generates a plurality of gate signals (or scan signals) based on the gate control signal received from the display drive circuit 200, and sequentially supplies the gate signals to the plurality of gate lines GL. In this case, the gate drive circuit 210 may sequentially supply the gate signals to the gate lines GL that are spaced apart from each other in the Y-axis direction and extend in the X-axis direction and are arranged in parallel.

[0060] In the display area DA where the gate driving circuit 210 is formed, the gate lines GL are arranged in the X-axis direction, and the data lines DL are arranged in the Y-axis direction to intersect with the gate lines GL. A plurality of pixels SP are respectively located at the intersection areas of the gate lines GL arranged in parallel in the X-axis direction and the data lines DL arranged in parallel in the Y-axis direction. Here, the plurality of pixels SP may be defined as the minimum unit for outputting image display light.

[0061] The gate driving circuit 210 sequentially generates gate signals in units of at least one frame period based on the gate control signal received through the gate control line GCL, and supplies the gate signals to the gate lines GL in the order arranged in the Y-axis direction. The plurality of gate lines GL can supply the gate signals provided from the gate driving circuit 210 to the plurality of pixels SP.

[0062] The plurality of data lines DL may supply data voltages received from the display driving circuit 200 to the plurality of pixels SP. The plurality of data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0063] The plurality of power lines VL may supply a power voltage supplied from the display driving circuit 200 or the power supply unit to the plurality of pixels SP. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, and a reference voltage. The plurality of power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0064] The non-display area NDA may be an area surrounding the display area DA (eg, in the periphery of the display area DA or outside the footprint of the display area DA). The non-display area NDA may include a fan-out line FOL as an extension line of the data line DL, a gate control line GCL, and a driving voltage line VVL.

[0065] The fan-out lines FOL may extend from the display driving circuit 200 to the data lines DL of the display area DA. Each of the fan-out lines FOL may supply a data voltage received from the display driving circuit 200 to each of the data lines DL.

[0066] The gate control line GCL may extend from the display driving circuit 200 to the gate driving circuit 210 of the display area DA. The gate control line GCL may supply a gate control signal received from the display driving circuit 200 to the gate driving circuit 210. For example, the gate control line GCL may include a gate start signal transmission line and a plurality of clock signal transmission lines. The gate start signal from the display driving circuit 200 is supplied to the gate driving circuit 210 through the gate start signal transmission line. In addition, respective clock signals having different phases are supplied to the gate driving circuit 210 through respective clock signal transmission lines.

[0067] The driving voltage line VVL may extend from the power supply terminal of the display driving circuit 200 or the power supply unit to the gate driving circuit 210 of the display area DA. The driving voltage line VVL supplies the high potential driving voltage and the low potential driving voltage supplied from the display driving circuit 200 or the power supply unit to the gate driving circuit 210. For example, the driving voltage line VVL may include a high potential driving voltage line and a low potential driving voltage line. The high potential driving voltage is supplied to the gate driving circuit 210 through the high potential driving voltage line. In addition, the low potential driving voltage is supplied to the gate driving circuit 210 through the low potential driving voltage line.

[0068] In the display module DU used in a mobile display device such as a smartphone or a tablet PC, since the data lines DL and the gate control lines GCL as well as the power lines VL and the driving voltage lines VVL are centrally located in one side direction adjacent to the display driving circuit 200, some lines may intersect each other.

[0069] For example, the gate control line GCL that transmits the gate control signal to the gate driving circuit 210 may be arranged to intersect with one or more fan-out lines FOL that are extension lines of the data lines DL in one lateral direction of the display panel 100 corresponding to the arrangement direction of the display driving circuit 200. For example, the driving voltage line VVL that supplies the driving voltage to the gate driving circuit 210 may be arranged to intersect with one or more fan-out lines FOL that are extension lines of the data lines DL in one lateral direction of the display panel 100 corresponding to the arrangement direction of the display driving circuit 200. Different from this, one or more of the gate control line GCL or the driving voltage line VVL may also be arranged to intersect with at least one data line DL in the display area DA.

[0070] The sub-area SBA may include a display driving circuit 200, a display pad area DPA, and a first touch pad area TPA1 and a second touch pad area TPA2. Figure 4 As shown in , the display pad area DPA may include a plurality of display pads DP, the first touch pad area TPA1 may include a plurality of first touch pads TP1, and the second touch pad area TPA2 may include a plurality of second touch pads TP2.

[0071] The display driving circuit 200 can supply a gate control signal to the gate driving circuit 210 through the gate control line GCL. Here, the gate control signal may include a plurality of clock signals having a phase different from that of the gate start signal. In addition, the display driving circuit 200 can also output a driving voltage (or a high potential driving voltage and a low potential driving voltage) for driving the gate driving circuit 210 through the driving voltage line VVL.

[0072] In addition, the display driving circuit 200 can supply the data voltage to the data line DL through the fan-out line FOL. The data voltage can be supplied to the plurality of pixels SP, and the brightness of the plurality of pixels SP can be determined. Here, the power supply unit can be built into the display driving circuit 200, and the power supply unit can also be built into different main processors, etc.

[0073] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be located at the edge of the sub-area SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using an anisotropic conductive layer or a low resistance and high reliability material such as SAP.

[0074] The display pad area DPA may include a plurality of display pad portions. The plurality of display pad portions may be connected to the touch drive circuit 400 and different host processors through the circuit board 300. The plurality of display pad portions may be connected to the circuit board 300 to receive digital video data and supply the digital video data to the display drive circuit 200.

[0075] Figure 5 is an illustration of some embodiments wherein Figure 4 A layout view of the enlarged AA region where the data lines, gate control lines, and power lines intersect. Figure 6 It is a specific illustration according to some embodiments Figure 5 The image shown in shows a layout view of the area.

[0076] refer to Figure 5 and Figure 6 The gate driving circuit 210 is located in the display area DA, and a plurality of pixels SP are arranged on the front surface of the display area DA including the gate driving circuit 210, and the plurality of pixels SP are each divided into a first display pixel SP1, a second display pixel SP2, and a third display pixel SP3.

[0077] The first display pixel SP1, the second display pixel SP2, and the third display pixel SP3 may be defined as one unit pixel UP. Each unit pixel UP may be defined as the first display pixel SP1, the second display pixel SP2, and the third display pixel SP3, which are the smallest units capable of displaying white. As another example, each unit pixel UP may be defined as the first to fourth display pixels, which are the smallest units capable of displaying white. In this case, the fourth display pixel may emit light of the same color as the color of any one of the first to third display pixels. Different from this, the fourth display pixel may also be formed without a color filter to emit white light.

[0078] Each unit pixel UP may be arranged in a vertical or horizontal matrix along the X-axis and Y-axis directions of the display area DA. In addition, each unit pixel UP may also be arranged in a zigzag form. For example, each unit pixel UP may also be arranged in a The matrix structure is arranged in the display area DA.

[0079] The first display pixel SP1 may include a first light emitting unit ELU1 emitting first light and a first pixel driving unit DDU1 for applying a driving current to a light emitting element of the first light emitting unit ELU1. The first light may be light in a red wavelength band. For example, the main peak wavelength of the first light may be between about 600nm and 750nm.

[0080] The second display pixel SP2 may include a second light emitting unit ELU2 emitting a second light and a second pixel driving unit DDU2 for applying a driving current to a light emitting element of the second light emitting unit ELU2. The second light may be light in a green wavelength band. For example, the main peak wavelength of the second light may be between about 480 nm and 560 nm.

[0081] The third display pixel SP3 may include a third light emitting unit ELU3 emitting the third light and a third pixel driving unit DDU3 for applying a driving current to the light emitting element of the third light emitting unit ELU3. The third light may be light in a blue wavelength band. For example, the main peak wavelength of the third light may be between about 370nm and 460nm.

[0082] In each unit pixel UP, the first pixel driving unit DDU1 and the second pixel driving unit DDU2 may be positioned adjacent to each other in a diagonal direction, and the first pixel driving unit DDU1 and the third pixel driving unit DDU3 may be arranged in the X-axis direction. Similarly, the second pixel driving unit DDU2 and the third pixel driving unit DDU3 may be arranged in a diagonal direction. In this case, each unit pixel UP may be arranged in a zigzag form.

[0083] The first light emitting unit ELU1, the second light emitting unit ELU2 and the third light emitting unit ELU3 may have an octagonal plane shape, but are not limited thereto. The first light emitting unit ELU1, the second light emitting unit ELU2 and the third light emitting unit ELU3 may have a quadrilateral plane shape such as a rhombus or a polygonal plane shape other than a quadrilateral and an octagon.

[0084] Due to the arrangement positions and plane shapes of the first light-emitting unit ELU1, the second light-emitting unit ELU2, the third light-emitting unit ELU3 and another adjacent second light-emitting unit ELU2, the distance D12 between the center C1 of the first light-emitting unit ELU1 and the center C2 of the second light-emitting unit ELU2, the distance D23 between the center C2 of the second light-emitting unit ELU2 and the center C3 of the third light-emitting unit ELU3, the distance D34 between the center C3 of the third light-emitting unit ELU3 and the center C4 of another adjacent second light-emitting unit ELU2, and the distance D14 between the center C1 of the first light-emitting unit ELU1 and the center C4 of another adjacent second light-emitting unit ELU2 may be substantially the same.

[0085] As described above, the gate driving circuit 210 is arranged in the display area DA in the Y-axis direction, and each pixel SP may overlap on the front surface of the gate driving circuit 210. Figure 4 and Figure 5 As shown in , the gate control line GCL is connected between the gate driving circuit 210 and the display driving circuit 200. In this case, the gate control line GCL extends from the input terminal of one side surface of the gate driving circuit 210 to the sub-area SBA in which the display driving circuit 200 is arranged along the non-display area NDA of the display panel 100. In this case, according to the arrangement position of the gate driving circuit 210 located in the display area DA, the data line DL or the fan-out line FOL as an extension line of the data line DL may intersect with the gate control line GCL. In other words, the gate control line GCL may intersect with the data line DL, or may intersect with the fan-out line FOL as an extension line of the data line DL.

[0086] Similarly, the driving voltage line VVL is connected between the gate driving circuit 210 and the display driving circuit 200 or the power supply terminal of the power supply unit. In this case, the driving voltage line VVL also extends from the input terminal of one side surface of the gate driving circuit 210 to the sub-area SBA in which the display driving circuit 200 is arranged along the non-display area NDA of the display panel 100. Therefore, according to the arrangement position of the gate driving circuit 210 located in the display area DA, the data line DL or the fan-out line FOL as an extension line of the data line DL may intersect with the driving voltage line VVL.

[0087] Figure 7 is a diagram showing the formation of a partition for each block according to some embodiments Figures 4 to 6 The image shows a view of the gate drive circuit in the area.

[0088] refer to Figure 7 , the gate driving circuit 210 located in the display area DA may include a plurality of display stages STA1, STA2, . . . , STAn (n is a positive integer).

[0089] The plurality of display stages STA1, STA2, ..., STAn may be connected to at least one of the respective clock signal transmission lines CKL1, CKL2, CKL3, and CKL4, and may receive at least one clock signal having a different phase from the display driving circuit 200. In addition, the plurality of display stages STA1, STA2, ..., STAn operate by receiving a high potential driving voltage and a low potential driving voltage through a high potential driving voltage line VDD and a low potential driving voltage line VSS among the driving voltage lines VVL.

[0090] The first display stage STA1 among the plurality of display stages STA1 , STA2 , . . . , STAn may be connected to the gate start signal transmission line STRL which is one of the gate control lines GCL and may receive a gate start signal from the display driving circuit 200 .

[0091] A plurality of display stages STA1, STA2, ..., STAn are sequentially (or subordinately) connected from the first display stage STA1 to the last n-th display stage STAn. Therefore, the plurality of display stages STA1, STA2, ..., STAn may sequentially generate gate signals starting from the first display stage STA1, and sequentially send the gate signals to the first gate line GL1 to the n-th gate line GLn.

[0092] As an example, the first display level STA1 generates a gate signal in response to a gate start signal and a first clock signal, and supplies the gate signal to the first gate line GL1 and the second display level STA2 of the next level. Subsequently, the second display level STA2 generates a gate signal in response to the gate signal and the second clock signal of the first display level STA1 of the previous level, and supplies the gate signal to the second gate line GL2 and the third display level STA3 of the next level. In this order, until the last n-th display level STAn, the gate signal is supplied to the n-th gate line GLn. A plurality of display levels STA1, STA2, ..., STAn can sequentially supply gate signals to the first gate line GL1 to the n-th gate line GLn in units of at least one frame period.

[0093] Figure 8 is a diagram illustrating a method according to some embodiments Figure 5 A layout view of a more magnified intersection area of ​​data lines, gate control lines, and power lines.

[0094] refer to Figure 8 According to the arrangement position of the gate driving circuit 210 located in the display area DA, the data line DL or the fan-out line FOL which is an extension line of the data line DL may intersect the gate control line GCL.

[0095] Specifically, in the display panel 100 used in a mobile display device such as a smart phone or a tablet PC, since the data lines DL and the gate control lines GCL and the driving voltage lines VVL are centrally located in one side direction adjacent to the display driving circuit 200 , the lines are arranged to intersect each other.

[0096] The gate control line GCL may include a gate start signal transmission line STRL and a plurality of clock signal transmission lines CKL1, CKL2, CKL3, and CKL4. In this case, the gate start signal transmission line STRL and the plurality of clock signal transmission lines CKL1, CKL2, CKL3, and CKL4 may intersect with the data line DL, or may intersect with a fan-out line FOL which is an extension line of the data line DL.

[0097] According to the arrangement position of the gate driving circuit 210 located in the display area DA, the driving voltage line VVL may also intersect with the data line DL, or may intersect with the fan-out line FOL which is an extension line of the data line DL. The driving voltage line VVL may include a high potential driving voltage line VDD and a low potential driving voltage line VSS. In this case, the high potential driving voltage line VDD and the low potential driving voltage line VSS may intersect with the data line DL, or may intersect with the fan-out line FOL which is an extension line of the data line DL.

[0098] Since the gate start signal transmission line STRL and multiple clock signal transmission lines CKL1, CKL2, CKL3 and CKL4 intersect with the data line DL (or the fan-out line FOL which is an extension line of the data line DL), electromagnetic coupling may occur in each intersection node or intersection area (for example, BB area).

[0099] Fig. 9 is a specific illustration of some embodiments of the present invention Figure 8 A layout view of the BB region where a data line intersects a gate control line. Fig.10 is a diagram illustrating a method according to some embodiments Fig. 9 A cross-sectional view of a section taken along line CC' shown in FIG.

[0100] refer to Fig. 9 and Fig.10 , a region (e.g., BB region) where the gate control line GCL and at least one data line DL intersect each other may include the gate control line GCL (shown as the fourth clock signal transmission line CKL4), the first interlayer insulating layer 141, the electrostatic pattern line VGM, the second interlayer insulating layer 142, and at least one data line DL. The first interlayer insulating layer 141, the electrostatic pattern line VGM, and the second interlayer insulating layer 142 may be located between the gate control line GCL and the at least one data line DL.

[0101] As an example, referring to a case in which the fourth clock signal transmission line CKL4 and at least one data line DL intersect each other. Fig. 9 and Fig.10 Layout view and cross-sectional view of the BB region of FIG. 1 , a barrier layer BR is first formed on a substrate SUB. The barrier layer BR is a film for protecting the thin film transistor layer and various lines of the sub-pixel SP from moisture penetrating through the substrate SUB susceptible to moisture penetration. The barrier layer BR may include a plurality of inorganic layers alternately stacked. For example, the barrier layer BR may be formed as a multilayer in which inorganic layers among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0102] A gate insulating layer 130 for protecting an active layer of a thin film transistor is formed on the barrier layer BR, and a gate control line GCL is formed on the gate insulating layer 130. The gate control line GCL may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0103] The first interlayer insulating layer 141 is formed on the gate insulating layer 130 including the gate control line GCL to cover at least one gate control line GCL. The first interlayer insulating layer 141 may be formed as a multilayer in which a plurality of inorganic layers are alternately stacked.

[0104] The electrostatic pattern line VGM is patterned and formed on the first interlayer insulating layer 141 so as to overlap and cover the gate control line GCL in parallel with the first interlayer insulating layer 141 therebetween. The electrostatic pattern line VGM may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The electrostatic pattern line VGM may extend to the display driving circuit 200 or a separate power supply unit.

[0105] The second interlayer insulating layer 142 covering the electrostatic pattern line VGM is formed on the first interlayer insulating layer 141 and the electrostatic pattern line VGM. The second interlayer insulating layer 142 may be formed as a plurality of inorganic layers like the first interlayer insulating layer 141 .

[0106] A plurality of data lines DL may be formed on the second interlayer insulating layer 142 in a direction intersecting the gate control lines GCL and the electrostatic pattern lines VGM. The plurality of data lines DL may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0107] A constant voltage having a level (e.g., a set or predetermined level) may be applied to the electrostatic pattern line VGM formed to intersect at least one data line DL with the second interlayer insulating layer 142 interposed therebetween through the display driving circuit 200 or a separate power supply unit. Therefore, the gate control line GCL formed to intersect at least one data line DL with the electrostatic pattern line VGM interposed therebetween is prevented from being coupled to the at least one data line DL by the electrostatic pattern line VGM interposed therebetween. That is, as Fig. 9 and Fig.10 As shown in , the fourth clock signal transmission line CKL4 formed to intersect at least one data line DL with the electrostatic pattern line VGM interposed therebetween is prevented from being coupled to the at least one data line DL by the electrostatic pattern line VGM interposed therebetween.

[0108] Similarly, the driving voltage line VVL may also be formed to intersect with at least one data line DL with the electrostatic pattern line VGM interposed therebetween. That is, the electrostatic pattern line VGM is located in the same structure in the intersection region between the driving voltage line VVL and the data line DL. Therefore, the driving voltage line VVL may also be prevented from coupling with at least one data line DL by the electrostatic pattern line VGM.

[0109] Fig.11 is a schematic diagram illustrating how Figures 1 to 3 Layout view of the display panel shown in .

[0110] refer to Fig.11 In a display module DU used in a mobile display device such as a smart phone or a tablet PC, since the data lines DL and the gate control lines GCL as well as the power lines VL and the driving voltage lines VVL are centrally arranged in one side direction adjacent to the display driving circuit 200, some lines may intersect with each other.

[0111] To minimize a design in which lines intersect, the driving voltage line VVL may be arranged along the non-display area NDA as a peripheral area of ​​the display area DA in the form of surrounding the display area DA, and may be connected to the gate driving circuit 210 so as not to overlap or intersect with the gate line GL and the data line DL.

[0112] However, the gate control line GCL transmitting the gate control signal to the gate driving circuit 210 may be arranged to intersect one or more fan-out lines FOL as extension lines of the data line DL in one side direction of the display panel 100 corresponding to the arrangement direction of the display driving circuit 200 .

[0113] Fig.12 is an illustration of some embodiments wherein Fig.11Layout view of an enlarged EE area where data lines, gate control lines, and power lines intersect.

[0114] refer to Fig.12 , the widths of the pixels SP arranged in the display area DA in at least one direction may be differently formed according to the arrangement areas of the pixels SP.

[0115] As a specific example, the formed width in one direction of the pixels SP arranged in the preset first plane area among the pixels SP arranged in the display area DA may be formed as the first width SPm(h) as a reference width. In addition, the formed width in one direction of the pixels SP arranged in the second plane area among the pixels SP arranged in the display area DA may be formed as the second width SPn-m(h) smaller than the first width SPm(h). Therefore, the formed width in one direction of the pixels SP arranged in the third plane area among the pixels SP arranged in the display area DA may be formed as the third width SPn(h) greater than the first width SPm(h). That is, the formed width in one direction of the pixels SP arranged in the third plane area among the pixels SP arranged in the display area DA may be greater than the formed widths of the pixels SP arranged in the first plane area and the second plane area.

[0116] In this case, the gate control line GCL may also be arranged to intersect at least one data line DL in the display area DA. For example, the gate control line GCL may be arranged to intersect at least one data line DL in an arrangement area of ​​pixels SP located in the third plane area among pixels SP arranged in the display area DA.

[0117] Fig.13 is a specific illustration of some embodiments of the present invention Fig.12 A layout view of the EE area where a data line intersects a gate control line. Fig.14 is a diagram illustrating a method according to some embodiments Fig.13 A cross-sectional view of a section taken along line FF' shown in FIG.

[0118] refer to Fig.13 and Fig.14 , where a region (eg, EE region) where the gate control line GCL and the at least one data line DL intersect may include an organic insulation pattern layer OML between the gate control line GCL (shown as a gate start signal transmission line STRL) and the at least one data line DL.

[0119] As an example, referring to a case in which a gate start signal transmission line STRL and at least one data line DL intersect each other. Fig.13 and Fig.14Layout view and cross-sectional view of the EE region, a barrier layer BR is first formed on a substrate SUB.

[0120] The barrier layer BR is a film for protecting the thin film transistor layer and various lines of the sub-pixel SP from moisture penetrating through the substrate SUB susceptible to moisture penetration.

[0121] A gate insulating layer 130 for protecting an active layer of a thin film transistor may be formed on the barrier layer BR, and a gate control line GCL may be formed on the gate insulating layer 130 .

[0122] The first interlayer insulating layer 141 is formed on the gate insulating layer 130 including the one or more gate control lines GCL to cover the one or more gate control lines GCL. In addition, the second interlayer insulating layer 142 is formed on the first interlayer insulating layer 141. The second interlayer insulating layer 142 may be formed as a plurality of inorganic layers like the first interlayer insulating layer 141.

[0123] Thereafter, a pattern hole having a preset size and width is formed in an intersection region predetermined to intersect with one or more data lines DL among the front regions of the one or more gate control lines GCL. In addition, an organic insulating pattern layer OML is formed by filling an organic material in the pattern hole having a preset size and width. The organic insulating pattern layer OML includes at least one organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0124] A plurality of data lines DL are formed on the second interlayer insulating layer 142 and a portion of the organic insulation pattern layer OML in a direction intersecting the organic insulation pattern layer OML. The plurality of data lines DL may be formed to intersect the organic insulation pattern layer OML and the gate control line GCL.

[0125] Since the organic material of the organic insulation pattern layer OML has a smaller dielectric constant than other inorganic materials or materials of the interlayer insulation layer, the gate control line GCL formed to intersect at least one data line DL with the organic insulation pattern layer OML therebetween can be prevented from being coupled to the at least one data line DL by the organic insulation pattern layer OML.

[0126] Fig.15 and Fig.16 is a perspective view illustrating a display device according to some embodiments of the present disclosure.

[0127] Fig.15 and Fig.16The display device 10 is illustrated as a foldable display device that is folded in a first direction (X-axis direction). The display device 10 can maintain both a folded state and an unfolded state. The display device 10 can be folded in an inner folding manner with its front surface located inside. When the display device 10 is bent or folded in an inner folding manner, the front surfaces of the display device 10 can be arranged to face each other. Alternatively, the display device 10 can be folded in an outer folding manner with its front surface located outside. When the display device 10 is bent or folded in an outer folding manner, the rear surfaces of the display device 10 can be arranged to face each other.

[0128] The first non-folding area NFA1 may be located on one side (e.g., the right side) of the folding area FDA. The second non-folding area NFA2 may be located on the other side (e.g., the left side) of the folding area FDA. The touch sensing unit TSU according to some embodiments of the present specification may be formed and located on the first non-folding area NFA1 and the second non-folding area NFA2, respectively.

[0129] The first folding line FOL1 and the second folding line FOL2 may extend in the second direction (Y-axis direction), and the display device 10 may be folded in the first direction (X-axis direction). Therefore, since the length of the display device 10 in the first direction (X-axis direction) may be reduced by about half, it may be convenient for a user to carry the display device 10.

[0130] Meanwhile, the extending direction of the first folding line FOL1 and the extending direction of the second folding line FOL2 are not limited to the second direction (Y-axis direction). For example, the first folding line FOL1 and the second folding line FOL2 may extend in the first direction (X-axis direction), and the display device 10 may be folded in the second direction (Y-axis direction). In this case, the length of the display device 10 in the second direction (Y-axis direction) may be reduced by about half. Alternatively, the first folding line FOL1 and the second folding line FOL2 may extend in the oblique direction between the first direction (X-axis direction) and the second direction (Y-axis direction) of the display device 10. In this case, the display device 10 may be folded into a triangular shape.

[0131] When the first folding line FOL1 and the second folding line FOL2 extend in the second direction (Y-axis direction), the length of the folding area FDA in the first direction (X-axis direction) may be shorter than its length in the second direction (Y-axis direction). In addition, the length of the first non-folding area NFA1 in the first direction (X-axis direction) may be longer than the length of the folding area FDA in the first direction (X-axis direction). The length of the second non-folding area NFA2 in the first direction (X-axis direction) may be longer than the length of the folding area FDA in the first direction (X-axis direction).

[0132] The first display area DA1 may be located on the front surface of the display device 10. The first display area DA1 may overlap the folding area FDA, the first non-folding area NFA1, and the second non-folding area NFA2. Therefore, when the display device 10 is unfolded, an image may be displayed in the folding area FDA, the first non-folding area NFA1, and the second non-folding area NFA2 of the display device 10 in a front direction.

[0133] The second display area DA2 may be located on the rear surface of the display device 10. The second display area DA2 may overlap the second non-folding area NFA2. Therefore, when the display device 10 is folded, an image may be displayed in the second non-folding area NFA2 of the display device 10 in the front direction.

[0134] Fig.15 and Fig.16 It is illustrated that the through hole TH in which the camera SDA is formed is located in the first non-folding area NFA1, but embodiments according to the present disclosure are not limited thereto. The through hole TH or the camera SDA may be located in the second non-folding area NFA2 or the folding area FDA.

[0135] Fig.17 and Fig.18 is a perspective view illustrating a display device according to some embodiments of the present disclosure.

[0136] Fig.17 and Fig.18 The display device 10 is illustrated as a foldable display device that is folded in the second direction (Y-axis direction). The display device 10 can maintain both the folded state and the unfolded state. The display device 10 can be folded in an inner folding manner with its front surface located inside. When the display device 10 is bent or folded in an inner folding manner, the front surfaces of the display device 10 can be arranged to face each other. Alternatively, the display device 10 can be folded in an outer folding manner with its front surface located outside. When the display device 10 is bent or folded in an outer folding manner, the rear surfaces of the display device 10 can be arranged to face each other.

[0137] The display device 10 may include a folding area FDA, a first non-folding area NFA1, and a second non-folding area NFA2. The folding area FDA may be an area in which the display device 10 is folded, and the first non-folding area NFA1 and the second non-folding area NFA2 may be areas in which the display device 10 is not folded. The first non-folding area NFA1 may be located on one side (e.g., the lower side) of the folding area FDA. The second non-folding area NFA2 may be located on the other side (e.g., the upper side) of the folding area FDA.

[0138] The touch sensing unit TSU according to some embodiments of the present specification may be formed and located on the first non-folding area NFA1 and the second non-folding area NFA2 , respectively.

[0139] On the other hand, the folding area FDA may be an area bent with a curvature (e.g., a set or predetermined curvature) at the first folding line FOL1 and the second folding line FOL2. Therefore, the first folding line FOL1 may be a boundary between the folding area FDA and the first non-folding area NFA1, and the second folding line FOL2 may be a boundary between the folding area FDA and the second non-folding area NFA2.

[0140] like Fig.17 and Fig.18 As shown in , the first folding line FOL1 and the second folding line FOL2 can extend in the first direction (X-axis direction), and the display device 10 can be folded in the second direction (Y-axis direction). Therefore, since the length of the display device 10 in the second direction (Y-axis direction) can be reduced by about half, it is convenient for the user to carry the display device 10.

[0141] Meanwhile, the extending direction of the first folding line FOL1 and the extending direction of the second folding line FOL2 are not limited to the first direction (X-axis direction). For example, the first folding line FOL1 and the second folding line FOL2 may extend in the second direction (Y-axis direction), and the display device 10 may be folded in the first direction (X-axis direction). In this case, the length of the display device 10 in the first direction (X-axis direction) may be reduced by about half. Alternatively, the first folding line FOL1 and the second folding line FOL2 may extend in the oblique direction between the first direction (X-axis direction) and the second direction (Y-axis direction) of the display device 10. In this case, the display device 10 may be folded into a triangular shape.

[0142] like Fig.17 and Fig.18 As shown in , when the first folding line FOL1 and the second folding line FOL2 extend in the first direction (X-axis direction), the length of the folding area FDA in the second direction (Y-axis direction) may be shorter than its length in the first direction (X-axis direction). In addition, the length of the first non-folding area NFA1 in the second direction (Y-axis direction) may be longer than the length of the folding area FDA in the second direction (Y-axis direction). In addition, the length of the second non-folding area NFA2 in the second direction (Y-axis direction) may be longer than the length of the folding area FDA in the second direction (Y-axis direction).

[0143] The first display area DA1 may be located on the front surface of the display device 10. The first display area DA1 may overlap the folding area FDA, the first non-folding area NFA1, and the second non-folding area NFA2. Therefore, when the display device 10 is unfolded, an image may be displayed in the folding area FDA, the first non-folding area NFA1, and the second non-folding area NFA2 of the display device 10 in a front direction.

[0144] The second display area DA2 may be located on the rear surface of the display device 10. The second display area DA2 may overlap the second non-folding area NFA2. Therefore, when the display device 10 is folded, an image may be displayed in the second non-folding area NFA2 of the display device 10 in the front direction.

[0145] Fig.17 and Fig.18 It is illustrated that the through hole TH in which the camera SDA is located is arranged in the second non-folding area NFA2 , but embodiments according to the present disclosure are not limited thereto. The through hole TH may be located in the first non-folding area NFA1 or the folding area FDA.

[0146] At the end of the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the disclosed embodiments without departing substantially from the spirit and scope of the embodiments according to the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense and not for a limiting purpose.

Claims

1. A display device, comprising: display pixels, the display pixels being formed in an image display area of ​​the display panel; a gate driving circuit formed in the image display area and configured to supply a gate signal to the display pixel; a display driving circuit configured to supply a data voltage to a data line in the image display area through a fan-out line arranged in a non-display area of ​​the display panel, and configured to supply a gate control signal to the gate driving circuit through a gate control line arranged in the non-display area; as well as a driving voltage line arranged in the non-display area and configured to supply a driving voltage to the gate driving circuit, At least one of the gate control lines intersects with one or more of the fan-out lines in a side direction of the image display area corresponding to an arrangement direction of the display driving circuit.

2. The display device according to claim 1, wherein: The at least one of the gate control lines intersects one or more of the data lines in the image display area in the one lateral direction corresponding to the arrangement direction of the display driving circuit.

3. The display device according to claim 2, wherein: The gate control line includes a gate start signal transmission line and a plurality of clock signal transmission lines, and The gate start signal transmission line and one or more signal transmission lines among the plurality of clock signal transmission lines intersect with the one or more data lines, or intersect with the one or more fan-out lines.

4. The display device according to claim 2, wherein: The display pixels arranged in the preset first plane area among the display pixels arranged in the image display area have a formation width in one direction formed as a first width as a reference width, The display pixels arranged in the preset second plane area among the display pixels arranged in the image display area have a formation width in the one direction formed to be a second width smaller than the first width, and The display pixels arranged in a preset third plane area among the display pixels arranged in the image display area have a formation width in the one direction formed to be a third width greater than the first width.

5. The display device according to claim 4, wherein: The one or more data lines intersect at least one of the gate control lines in an arrangement area of ​​the display pixels in the third plane area of ​​the image display area.

6. The display device according to claim 2, wherein: In an intersection region where the one or more gate control lines intersect with the one or more fan-out lines or the data lines, The electrostatic pattern line to which a constant voltage is applied is located between the one or more gate control lines and the one or more fan-out lines intersecting each other, or between the one or more gate control lines and the data lines intersecting each other, Wherein, the intersection area where the at least one gate control line intersects with the one or more fan-out lines or the data lines includes: a first interlayer insulating layer, wherein the first interlayer insulating layer covers the one or more gate control lines; the electrostatic pattern line, the electrostatic pattern line being on the first interlayer insulating layer to overlap the one or more gate control lines in parallel; and a second interlayer insulating layer formed to cover the first interlayer insulating layer and the electrostatic pattern line, and The one or more fan-out lines or the data lines intersect the at least one gate control line with the second interlayer insulating layer interposed between the one or more fan-out lines or the data lines and the at least one gate control line.

7. The display device according to claim 2, wherein: In an intersection region where the one or more gate control lines intersect with the one or more fan-out lines or the data lines, An organic insulating pattern layer is formed between the one or more gate control lines and the one or more fan-out lines or the data lines intersecting each other, wherein the organic insulating pattern layer covering the at least one gate control line is formed in the intersection region where the one or more gate control lines intersect with the one or more fan-out lines or the data lines, and The one or more fan-out lines or the data lines intersect the at least one gate control line with the organic insulation pattern layer interposed between the one or more fan-out lines or the data lines and the at least one gate control line.

8. The display device according to claim 1, wherein: At least one of the driving voltage lines intersects the one or more fan-out lines in the one side direction of the image display area corresponding to the arrangement direction of the display driving circuit.

9. The display device according to claim 8, wherein: The at least one of the driving voltage lines intersects one or more of the data lines in the image display area in the one lateral direction corresponding to the arrangement direction of the display driving circuit.

10. The display device according to claim 9, wherein: In an intersection region where the at least one driving voltage line intersects with the one or more fan-out lines or the data line, An electrostatic pattern line to which a constant voltage is applied is between the at least one driving voltage line and the one or more fan-out lines or the data lines intersecting each other.

11. The display device according to claim 10, wherein: The intersection area where the at least one driving voltage line intersects with the one or more fan-out lines or the data line includes: a first interlayer insulating layer, wherein the first interlayer insulating layer covers the at least one driving voltage line; the electrostatic pattern line, the electrostatic pattern line being on the first interlayer insulating layer to overlap with the at least one driving voltage line; and a second interlayer insulating layer formed to cover the first interlayer insulating layer and the electrostatic pattern line, and The one or more fan-out lines or the data lines intersect the at least one driving voltage line with the second interlayer insulating layer interposed therebetween.

12. The display device according to claim 10, wherein: In an intersection region where the at least one driving voltage line intersects with the one or more fan-out lines or the data line, An organic insulating pattern layer is formed between the at least one driving voltage line and the one or more fan-out lines or the data lines intersecting each other, Wherein, in the intersection area where the at least one driving voltage line intersects with the one or more fan-out lines or the data lines, The organic insulating pattern layer covers the at least one driving voltage line, and The one or more fan-out lines or the data lines intersect the at least one driving voltage line with the organic insulation pattern layer interposed between the one or more fan-out lines or the data lines and the at least one driving voltage line.

13. A display device, comprising: A display panel, the display panel comprising an image display area and a non-display area; display pixels, the display pixels being in the image display area; a gate driving circuit formed in the image display area and configured to supply a gate signal to the display pixel; a display driving circuit configured to supply a data voltage to a data line in the image display area through a fan-out line arranged in the non-display area, and configured to supply a gate control signal to the gate driving circuit through a gate control line arranged in the non-display area; as well as a driving voltage line, the driving voltage line being in the non-display area and configured to supply a driving voltage to the gate driving circuit, wherein at least one of the gate control lines intersects with one or more of the fan-out lines in a side direction of the image display area corresponding to the arrangement direction of the display drive circuit, and At least one of the driving voltage lines intersects the one or more fan-out lines in the one side direction of the image display area corresponding to the arrangement direction of the display driving circuit.

Images