Display panel and display device

Abstract

The invention discloses a display panel and a display device. A pixel driving circuit of the display panel comprises a switch transistor, a driving transistor, a first light-emitting transistor and a first reset crystal which are connected to a first node, a grid electrode of the first light-emitting transistor is connected to a light-emitting control line, a conductive section of an area where the first node is located is located on an active layer, and the light-emitting control line is located on a first source-drain electrode layer. The conductive section and the light-emitting control line have an overlapped part; the conductive section of the area where the first node is located is located on the active layer, and the light-emitting control line is located on the first source-drain electrode layer, so that the conductive section is replaced by a conductor semiconductor layer from a metal layer, the distance between the light-emitting control line and the conductive section is increased, the coupling capacitance between the light-emitting control line and the first node is reduced, and the light-emitting efficiency is improved. The abnormality of the potential of the first node is improved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology. It has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the pixel driving circuit of the OLED display panel usually includes a switching transistor, a driving transistor and a light-emitting transistor. The switching transistor, the driving transistor and the light-emitting transistor are all connected to a first node, and the gate of the light-emitting control transistor is connected to a light-emitting control line. Since the light-emitting control line and the first node overlap, and the light-emitting control line is located in the first gate layer, and the conductive segment in the area where the first node is located is located in the source and drain layer, there is a large coupling capacitance between the light-emitting control line and the first node, so that the voltage of the first node is not reset to the reference voltage during the working stage, resulting in abnormal display of the display panel. Summary of the invention

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a display panel, which includes a plurality of sub-pixel units, each of which is provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, wherein the pixel driving circuit includes a switch transistor connected to a first node, a driving transistor, a first light-emitting transistor and a first reset transistor, wherein the gate of the first light-emitting transistor is connected to a light-emitting control line; wherein the display panel includes:

[0007] substrate substrate;

[0008] An active layer is disposed on one side of the substrate;

[0009] A first gate layer is disposed on a side of the active layer away from the substrate;

[0010] A second gate layer is disposed on a side of the first gate layer away from the base substrate;

[0011] A first source-drain electrode layer is disposed on a side of the second gate layer away from the substrate;

[0012] The active layer includes a conductive segment in a region where the first node is located, the first source-drain electrode layer includes the light-emitting control line, and the conductive segment and the light-emitting control line have an overlapping portion.

[0013] Optionally, the active layer includes a switch active portion of the switch transistor, a first light emitting active portion of the first light emitting transistor, a first reset active portion of the first reset transistor, and an active connecting section, the active connecting section extends along a first direction, the switch active portion, the first light emitting active portion, and the first reset active portion all extend along a second direction, and the first light emitting active portion and the first reset active portion are spaced apart along the first direction;

[0014] Among them, the switch active part and the first light-emitting active part are connected to a first connection point, one end of the active connection section is connected to the first connection point, the other end of the active connection section is connected to the first reset active part, and the light-emitting control line and the first reset active part have a first overlapping part.

[0015] Optionally, the first light emitting active portion includes a first light emitting channel, and the light emitting control line has a second overlapping portion with the first light emitting active portion between the first light emitting channel and the first connection point.

[0016] Optionally, the light-emitting control line includes a first sub-segment, a second sub-segment and a third sub-segment connected to each other, the first sub-segment and the third sub-segment extend along the first direction, and the second sub-segment is arranged at an angle to the first sub-segment and the third sub-segment;

[0017] The first light emitting active portion includes a first light emitting channel, the first sub-segment and the first light emitting channel have an overlapping portion, and the third sub-segment and the first resetting active portion have the first overlapping portion.

[0018] Optionally, the first gate layer includes a first light emitting gate of the first light emitting transistor;

[0019] Among them, the first end of the first light-emitting gate is arranged between the first light-emitting active part and the first reset active part, and the first end of the first light-emitting gate is electrically connected to the light-emitting control line, and the second end of the first light-emitting gate extends toward the first light-emitting active part and overlaps with the first light-emitting active part.

[0020] Optionally, the pixel driving circuit further comprises a second light emitting transistor connected to the driving transistor at a second node, the second light emitting transistor comprising a second light emitting active portion located in the active layer and a second light emitting gate located in the first gate layer;

[0021] The second light emitting active portion extends along the second direction and is arranged on a side of the first reset active portion away from the first light emitting active portion, the first end of the second light emitting gate is arranged between the second light emitting active portion and the first reset active portion, and the first end of the first light emitting gate is electrically connected to the light emitting control line, and the second end of the second light emitting gate extends toward the second light emitting active portion and overlaps with the second light emitting active portion.

[0022] Optionally, the active part further includes a driving active part of the driving transistor, a first end of the driving active part is connected to the switch active part, and a second end of the driving active part is connected to the second connection point.

[0023] Optionally, the pixel driving circuit further comprises a compensation transistor, a first electrode of the compensation transistor is connected to the second node, and a second electrode of the compensation transistor is connected to the gate of the driving transistor;

[0024] The active part includes a first compensation active part and a second compensation active part of the compensation transistor, one end of the first compensation active part and the second light emitting active part are connected to a second connection point, and the other end of the first compensation active part is connected to the second compensation active part;

[0025] Among them, the first gate layer includes a first control line extending along a first direction and a first extension segment connected to the first control line, the first extension segment extends along the second direction, the first control line has an overlapping portion with the switch active portion and the first compensation active portion, and the first extension segment has an overlapping portion with the second compensation active portion.

[0026] Optionally, the pixel driving circuit further includes a second reset transistor, a third reset transistor and a storage capacitor;

[0027] The first electrode of the switch transistor is connected to the data signal line, the second electrode of the switch transistor is connected to the first node, and the gate of the switch transistor is connected to the first control line;

[0028] The first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the gate of the driving transistor is connected to a third node;

[0029] The first electrode of the compensation transistor is connected to the third node, the second electrode of the compensation transistor is connected to the second node, and the gate of the compensation transistor is connected to the first control line;

[0030] A first electrode of the first reset transistor is connected to a first reset line, a second electrode of the first reset transistor is connected to the first node, and a gate of the first reset transistor is connected to a second control line;

[0031] A first electrode of the second reset transistor is connected to a second reset line, a second electrode of the second reset transistor is connected to the third node, and a gate of the second reset transistor is connected to a third control line;

[0032] A first electrode of the third reset transistor is connected to a third reset line, a second electrode of the third reset transistor is connected to an anode of the light emitting device, and a gate of the third reset transistor is connected to the second control line;

[0033] A first electrode of the first light emitting transistor is connected to a high potential line, and a second electrode of the first light emitting transistor is connected to the first node;

[0034] The first electrode of the second light emitting transistor is connected to the second node, the second electrode of the second light emitting transistor is connected to the anode of the light emitting device, and the gate of the second light emitting transistor is connected to the light emitting control line;

[0035] The first plate of the storage capacitor is connected to the high potential line, and the second plate of the storage capacitor is connected to the third node.

[0036] The present application also proposes a display device, which includes the above-mentioned display panel.

[0037] Beneficial effect: The present application makes the conductive segment in the area where the first node is located in the active layer, and the light-emitting control line in the first source and drain layer, so that the conductive segment is replaced by a conductive semiconductor layer from a metal layer, and the spacing between the light-emitting control line and the conductive segment is increased, thereby reducing the coupling capacitance between the light-emitting control line and the first node, improving the abnormality of the potential of the first node, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0039] Figure 1 A simplified structural diagram of the display panel of this application;

[0040] Figure 2 is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application;

[0041] Figure 3 This is a schematic diagram of the film layer in the display panel of this application;

[0042] Figure 4 A diagram showing the film layer stacking of a sub-pixel unit in the display panel of the present application;

[0043] Figure 5 for Figure 4 Structural diagram of the middle shading layer;

[0044] Figure 6 for Figure 4 A structural diagram of the first gate layer;

[0045] Figure 7 for Figure 4 The structure diagram of the active layer in ;

[0046] Figure 8 for Figure 4 A structural diagram of the second gate layer;

[0047] Fig. 9 for Figure 4 A first structural diagram of the first source and drain layer;

[0048] Fig.10 for Figure 4 A second structural diagram of the first source and drain layer;

[0049] Fig.11 for Figure 4 Structural diagram of the first source and drain layer in . DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0051] See also Figures 1 to 11 The present application provides a display panel 100 , which may include a display unit 200 and a gate driving circuit 300 located at one side of the display unit 200 , and the gate driving circuit 300 is used to input a control signal to the display unit 200 .

[0052] In this example, see Figure 1The display unit 200 includes a plurality of sub-pixel rows 210, each sub-pixel row 210 includes a plurality of sub-pixel units 211, each sub-pixel unit 211 is provided with a light-emitting device 211b and a pixel driving circuit 211a connected to the light-emitting device 211b, and the gate driving circuit 300 is used to input a gate control signal to the transistor in the pixel driving circuit 211a.

[0053] In this embodiment, the pixel driving circuit 211a includes a switch transistor T2 connected to a first node A, a driving transistor T1, a first light emitting transistor T5 and a first reset transistor T8, and a gate of the first light emitting transistor T5 is connected to a light emitting control line EM.

[0054] In this embodiment, the display panel 100 includes a base substrate 110, an active layer 123, a first gate layer 125, a second gate layer 127 and a first source-drain layer 129, the active layer 123 is arranged on one side of the base substrate 110, the first gate layer 125 is arranged on a side of the active layer 123 away from the base substrate 110, the second gate layer 127 is arranged on a side of the first gate layer 125 away from the base substrate 110, the first source-drain layer 129 is arranged on a side of the second gate layer 127 away from the base substrate 110, the active layer 123 includes a conductive segment in the area where the first node A is located, the first source-drain layer 129 includes the light-emitting control line EM, and the conductive segment has an overlapping portion with the light-emitting control line EM.

[0055] In the present application, the conductive segment in the area where the first node A is located is located in the active layer 123, and the light-emitting control line EM is located in the first source and drain layer 129, so that the conductive segment is replaced from the metal layer to the conductive semiconductor layer, and the distance between the light-emitting control line EM and the conductive segment is increased, thereby reducing the coupling capacitance between the light-emitting control line EM and the first node A, improving the abnormality of the potential of the first node A, and improving the display effect of the display panel 100.

[0056] It should be noted that the light-emitting device 211b of the present application can be an organic light-emitting diode, Mini LED, MicroLED, a conventional-sized LED or other light-emitting source.

[0057] The technical solution of the present application is now described in conjunction with specific embodiments.

[0058] See also Figure 1The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA, and a display unit 200 is disposed in the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for performing a display function, and a plurality of sub-pixel units 211 for realizing its display function are disposed therein. The non-display area NA may be a frame area of ​​the display panel 100, and a functional component for displaying the sub-pixel unit 211 in the auxiliary display area AA may be disposed therein.

[0059] See also Figure 1 The lower side of the display area AA is provided with a binding terminal 400, which can be connected to an external circuit, and transmits the signal input by the external circuit to the data line, thereby driving the display panel 100 to display the picture. For example, the binding terminal 400 can be bound and connected to a chip or a flip chip film, etc., to provide power and driving signals for the display panel 100.

[0060] In this embodiment, the gate driving circuit 300 is arranged in the non-display area NA, and the gate driving circuit 300 can be arranged on both sides of the display area AA; the gate driving circuit 300 may include a plurality of cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0061] In this embodiment, a plurality of light-emitting devices 211b and a pixel driving circuit 211a for driving the light-emitting devices 211b may be arranged in an array in the display area AA. The pixel driving circuit 211a may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C or other pixel driving circuit 211a. The following embodiment takes the 8T1C pixel driving circuit 211a as an example for description.

[0062] See also Figure 2 The pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a second reset transistor T4, a third reset transistor T7, a first reset transistor T8, a first light emitting transistor T5, a second light emitting transistor T6, and a storage capacitor Cst, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0063] See also Figure 2, the first electrode of the switch transistor T2 is connected to the data signal line Data, the second electrode of the switch transistor T2 is connected to the first node A, and the switch gate T2G of the switch transistor T2 is connected to the first control line Scan1; the first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the driving gate T1G of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control line Scan1; the first electrode of the second reset transistor T4 is connected to the second reset line Vib, the second electrode of the second reset transistor T4 is connected to the third node Q, and the gate T4G of the second reset transistor T4 is connected to the third control line Scan3; the first electrode of the third reset transistor T7 is connected to the third reset line Vic, and the second electrode of the third reset transistor T7 is connected to the anode of the light emitting device 211b. The first electrode of the first reset transistor T8 is connected to the first reset line Via, the second electrode of the first reset transistor T8 is connected to the first node A, and the gate T8G of the first reset transistor T8 is connected to the second control line Scan2; the first electrode of the first light-emitting transistor T5 is connected to the high potential line VDD, the second electrode of the first light-emitting transistor T5 is connected to the first node A, and the first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting control line EM; the first electrode of the second light-emitting transistor T6 is connected to the second node B, the second electrode of the second light-emitting transistor T6 is connected to the anode of the light-emitting device 211b, and the second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting control line EM; the first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; the cathode of the light-emitting device 211b is connected to the low potential line VSS.

[0064] It should be noted that the switch transistors T2 in different sub-pixel units 211 are connected to different data signal lines, and the present application only takes one of them as an example for description.

[0065] In this embodiment, the high potential line VDD is used to provide a constant high voltage level to the pixel driving circuit 211 a , and the low potential line VSS is used to provide a constant low voltage level to the pixel driving circuit 211 a .

[0066] In this embodiment, the switch transistor T2, the drive transistor T1, the third reset transistor T7, the first reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the second reset transistor T4 can be one of P-type transistors or N-type transistors; this application is explained by taking the switch transistor T2, the drive transistor T1, the third reset transistor T7, the first reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the second reset transistor T4 as P-type transistors.

[0067] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0068] In the following embodiments, the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction and the second direction Y is the vertical direction.

[0069] The following is for Figure 2 The structure of the film layer structure of the pixel driving circuit 211a of the present application is described.

[0070] See also Figure 3 The display area AA and the non-display area NA of the display panel 100 may be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110; in the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) provided on the array driving layer 120, a light emitting device layer (not shown) provided on the same layer as the pixel definition layer, and an encapsulation layer (not shown) provided on the pixel definition layer. The following mainly describes the film layer structure in the display area AA.

[0071] In the present embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate may be used.

[0072] In the present embodiment, the base substrate 110 is used to support various film layers disposed on the base substrate 110, and the base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0073] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0074] See also Figure 3 , the array driving layer 120 may include a plurality of thin film transistors, the thin film transistors may be of an etching barrier type, a back channel etching type, or may be divided into a bottom gate thin film transistor, a top gate thin film transistor and the like structure according to the position of the gate and the active layer, or may be divided into an N-type thin film transistor, a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 3 The thin film transistor in the Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of the present application.

[0075] See also Figure 3 The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, an active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, an inter-insulating layer 128 disposed on the second gate layer 127, a first source-drain layer 129 disposed on the inter-insulating layer 128, a first planarizing layer 130 disposed on the first source-drain layer 129, a second source-drain layer 131 disposed on the first planarizing layer 130, and a second planarizing layer 132 disposed on the second source-drain layer 131.

[0076] See also Figure 3 The light shielding layer 121 is disposed on the second barrier layer 114. The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be composed of a black light shielding material, such as a black light shielding metal or a black organic material.

[0077] See also Figure 3 The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0078] In this embodiment, the light shielding layer 121 may also be embedded in the buffer layer 122 .

[0079] See also Figure 3 The material of the active layer 123 may be amorphous silicon or low-temperature polysilicon. For example, in the present application, the material of the active layer 123 may be low-temperature polysilicon.

[0080] See also Figure 3 The first gate insulating layer 124, the second gate insulating layer 126, and the inter-insulating layer 128 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; and the materials of the first gate insulating layer 124, the second gate insulating layer 126, and the inter-insulating layer 128 can be inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0081] See also Figure 3 The first gate layer 125 and the second gate layer 127 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 127 may be copper, molybdenum, or molybdenum-titanium alloy.

[0082] See also Figure 3 The materials of the first source-drain electrode layer 129 and the second source-drain electrode layer 131 may be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal.

[0083] See also Figure 3 The first flat layer 130 and the second flat layer 132 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first flat layer 130 and the second flat layer 132 can be inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0084] It should be noted that Figure 3 The structure is only a cross-sectional view of the present application. If the wiring of the display panel 100 is relatively compact, the display panel 100 of the present application may further include a third source and drain layer disposed on the second planar layer 132, which is not specifically limited here.

[0085] See also Figure 4 and Figure 5 , Figure 4 2 is a film layer stacking diagram of a sub-pixel unit 211 in the display panel 100 of the present application. Figure 5 for Figure 4 Structural diagram of the middle light shielding layer 121.

[0086] See also Figure 5The light shielding layer 121 includes a light shielding body 121a and a first light shielding segment 121b, a second light shielding segment 121c, a third light shielding segment 121d, a fourth light shielding segment 121e, and a fifth light shielding segment 121f connected to the light shielding body 121a. The light shielding body 121a is located in the central area of ​​the sub-pixel unit 211. The first light shielding segment 121b is arranged at a first vertex angle of the light shielding body 121a. The second light shielding segment 121c is arranged at a second vertex angle of the light shielding body 121a. The third light shielding segment 121d and the fourth light shielding segment 121e extend along the second direction Y. The third light shielding segment 121d The light shielding layer 121 in two adjacent sub-pixel units 211 in the first direction X is connected to one end of the second light shielding segment 121c away from the light shielding body 121a, the fourth light shielding segment 121e is connected to one end of the light shielding body 121a away from the second light shielding segment 121c, the fifth light shielding segment 121f is arranged on both sides of the light shielding body 121a along the first direction X, and the light shielding layers 121 in two adjacent sub-pixel units 211 in the first direction X are connected to each other through the fifth light shielding segment 121f, and the light shielding layers 121 in two adjacent sub-pixel units 211 in the second direction Y are connected through the third light shielding segment 121d of one sub-pixel unit 211 and the fourth light shielding segment 121e of the other sub-pixel unit 211.

[0087] In this embodiment, the orthographic projection of the channel of the switch active part T2A of the switch transistor T2 on the light shading layer 121 is located in the first light shading segment 121b, the orthographic projection of the channel of the compensation active part of the compensation transistor T3 on the light shading layer 121 is located in the second light shading segment 121c, and the orthographic projection of the channel of the driving active part T1A of the driving transistor T1 on the light shading layer 121 is located in the light shading body 121a.

[0088] See also Figure 4 and Figure 6 , Figure 6 for Figure 4 The first gate layer 125 includes a first third control line Scan3, a first first control line Scan1, and a first second control line Scan2 extending along the first direction X. The third control line Scan3, the first control line Scan1, and the second control line Scan2 are arranged at intervals along the second direction Y. The first gate layer 125 also includes a first extension segment 125a and a second extension segment 125b connected to the first control line Scan1. The first extension segment 125a and the second extension segment 125b both extend along the second direction Y, and the length of the first extension segment 125a in the second direction Y is less than the length of the second extension segment 125b in the second direction Y.

[0089] In this embodiment, the first gate layer 125 also includes a first electrode Cst1 arranged between the first control line Scan1 and the second control line Scan2, a first light-emitting gate T5G of the first light-emitting transistor T5, and a second light-emitting gate T6G of the second light-emitting transistor T6, the first light-emitting gate T5G and the second light-emitting gate T6G are arranged at intervals and close to the second control line Scan2, and the first electrode Cst1 is arranged close to the first control line Scan1.

[0090] See also Figure 4 and Figure 7 , Figure 7 for Figure 4 The active layer 123 includes a switch active portion T2A of the switch transistor T2, a first light emitting active portion T5A of the first light emitting transistor T5, a first reset active portion T8A of the first reset transistor T8, a drive active portion T1A of the drive transistor T1, a second light emitting active portion T6A of the second light emitting transistor T6, a second reset active portion T4A of the second reset transistor T4, a third reset active portion T7A of the third reset transistor T7, a first compensation active portion T3Aa and a second compensation active portion T3Ab of the compensation transistor T3, and an active connection section 123a.

[0091] The active connecting section 123a and the second compensation active portion T3Ab extend along the first direction X, the first compensation active portion T3Aa, the switch active portion T2A, the first light emitting active portion T5A, the second light emitting active portion T6A, the first reset active portion T8A, and the third reset active portion T7A all extend along the second direction Y, and the first light emitting active portion T5A, the first reset active portion T8A, and the second light emitting active portion T6A are arranged at intervals along the first direction X.

[0092] The switch active portion T2A and the first light emitting active portion T5A are connected to the first connection point M1, one end of the active connection section 123a is connected to the first connection point M1, the other end of the active connection section 123a is connected to the first reset active portion T8A, one end of the first compensation active portion T3Aa and the second light emitting active portion T6A are connected to the second connection point M2, the other end of the first compensation active portion T3Aa is connected to the second compensation active portion T3Ab, a first end of the driving active portion T1A is connected to the switch active portion T2A, a second end of the driving active portion T1A is connected to the second connection point M2, the second reset active portion T4A and the second compensation active portion T3Ab are connected to the third connection point M3, the third reset active portion T7A and the second light emitting active portion T6A are connected to the second light emitting active portion T6A, and one end away from the first compensation active portion T3Aa is connected to the fourth connection point M4.

[0093] In this embodiment, the driving active portion T1A and the second resetting active portion T4A may be U-shaped.

[0094] In this embodiment, the first control line Scan1 overlaps with the switch active part T2A, and the first control line Scan1 at the overlapping position is the switch gate T2G of the switch transistor T2, and the switch channel of the switch active part T2A at the overlapping position; the first control line Scan1 overlaps with the first compensation active part T3Aa, and the first control line Scan1 at the overlapping position is the first compensation gate T3Ga of the compensation transistor T3, and the first compensation channel of the compensation transistor T3 of the first compensation active part T3Aa at the overlapping position; the first extension section 125a overlaps with the second compensation active part T3Ab, and the first extension section 125a at the overlapping position is the second compensation gate T3Gb of the compensation transistor T3, and the second compensation active part T3Ab at the overlapping position is the second compensation channel of the compensation transistor T3.

[0095] In this embodiment, the third control line Scan3 overlaps with the second reset active portion T4A, and the third control line Scan3 at the overlapping position is the second reset gate T4G of the second reset transistor T4, and the second reset channel of the second reset transistor T4 of the second reset active portion T4A at the overlapping position; the second control line Scan2 overlaps with the third reset active portion T7A, and the second control line Scan2 at the overlapping position is the third reset gate T7G of the third reset transistor T7, and the third reset channel of the third reset transistor T7 of the third reset active portion T7A at the overlapping position.

[0096] In this embodiment, the first end of the first light emitting gate T5G is disposed between the first light emitting active portion T5A and the first reset active portion T8A, and the first end of the first light emitting gate T5G is electrically connected to the light emitting control line EM, and the second end of the first light emitting gate T5G extends toward the first light emitting active portion T5A and overlaps with the first light emitting active portion T5A.

[0097] In this embodiment, a first end of the second light emitting gate T6G is disposed between the second light emitting active portion T6A and the first reset active portion T8A, and a first end of the first light emitting gate T5G is electrically connected to the light emitting control line EM, and a second end of the second light emitting gate T6G extends toward the second light emitting active portion T6A and overlaps with the second light emitting active portion T6A.

[0098] See also Figure 4 and Figure 8 , Figure 8 for Figure 4The second gate layer 127 includes a second plate Cst2 of a storage capacitor and a first connection electrode 127a, wherein the second plate Cst2 is arranged opposite to the first plate Cst1, and the area of ​​the second plate Cst2 is larger than the area of ​​the first plate Cst1, and the first connection electrode 127a corresponds to the connection point between the first compensation active portion T3Aa and the second compensation active portion T3Ab; at the same time, the second gate layer 127 also includes an electrical connection segment 127b arranged on both sides of the second plate Cst2, and the second plates Cst2 in two adjacent sub-pixel units 211 are electrically connected through the electrical connection segment 127b.

[0099] In this embodiment, the second electrode plate Cst2 is provided with a through hole HL, and the upper conductive wire for transmitting a high potential signal passes through the through hole and is connected to the first electrode plate Cst1 .

[0100] See also Figure 4 , Fig. 9 and Fig.10 , Fig. 9 for Figure 4 A first structural diagram of the first source and drain layer 129, Fig.10 for Figure 4 A second structural diagram of the first source and drain layer 129.

[0101] The first source-drain layer 129 includes a second third control line Scan3, a second reset line Vi2, a second first control line Scan1, a lateral high potential line Vdd1, a light-emitting control line EM, a second second control line Scan2, a third reset line Vi3, and a first reset line Vi1 arranged at intervals along the second direction Y; the second third control line Scan3, the second reset line Vi2, the second first control line Scan1, the second second control line Scan2, the third reset line Vi3, and the first reset line Vi1 all extend along the first direction X.

[0102] In this embodiment, the second third control line Scan3 partially overlaps with the first third control line Scan3, and the second third control line Scan3 and the first third control line Scan3 are electrically connected through a via; the second second control line Scan2 partially overlaps with the first second control line Scan2, and the second second control line Scan2 and the first second control line Scan2 are electrically connected through a via; the first first control line Scan1 and the second first control line Scan1 are arranged at intervals, and the second first control line Scan1 is arranged between the first first control line Scan1 and the second reset line Vi2, one end of the second extension segment 125b is connected to the first first control line Scan1, and the other end of the second extension segment 125b passes through the via and is electrically connected to the second first control line Scan1.

[0103] In this embodiment, the first source-drain layer 129 further includes a second connection electrode 129a, a third connection electrode 129b and a fourth connection electrode 129c. The second connection electrode 129a and the third connection electrode 129b are arranged between the horizontal high potential line Vdd1 and the second first control line Scan1, and the third connection electrode 129b is arranged between the second connection electrode 129a and the fourth connection electrode 129c. One end of the second connection electrode 129a passes through the via hole and is connected to the switch active part T2A away from the first connection point M1. The other end of the third connection electrode 129a passes through the via hole and is connected to the data signal line Data; the third connection electrode 129b extends along the second direction Y, one end of the third connection electrode 129b passes through the via hole and is connected to the first electrode plate Cst1, and the other end of the third connection electrode 129b passes through the via hole and is connected to the longitudinal high potential line Vdd2 of the second source and drain layer 131; one end of the fourth connection electrode 129c is connected to the transverse high potential line Vdd1, and the other end of the fourth connection electrode 129c is connected to the first connection electrode 127a of the second gate layer 127.

[0104] In this embodiment, the horizontal high potential line Vdd1 is V-shaped and recessed toward the second second control line Scan2 to avoid the end of the third connecting electrode 129b away from the second first control line Scan1, and the bottom of the recessed section of the horizontal high potential line Vdd1 passes through a via hole and is connected to the longitudinal high potential line Vdd2 of the second source and drain layer 131.

[0105] See also Fig. 9 and Fig.10 , the light emitting control line EM and the first reset active part T8A have a first overlapping portion N1; and Fig. 9 In the embodiment, the light emitting control line EM has a second overlapping portion N2 with the first light emitting active portion T5A between the first light emitting channel and the first connection point M1.

[0106] exist Fig. 9In the embodiment, the light emitting control line EM is a horizontal line segment extending along the first direction X, and the light emitting control line EM overlaps with the first light emitting active portion T5A and the first reset active portion T8A at the same time. Since the first light emitting channel of the first light emitting active portion T5A and the first reset channel of the first reset active portion T8A are both located on the side of the overlapping region away from the active connecting segment 123a, the active layer 123 of the first overlapping portion N1 and the second overlapping portion N2 is a conductive segment in the region where the first node A of the present application is located; and since the first overlapping portion N1 and the second overlapping portion N2 of the present application are The coupling capacitance between the two points N2 is composed of the electrode plate formed by the conductive semiconductor material and the electrode plate formed by the first source and drain layer 129, and the first gate insulation layer 124, the first gate layer 125, the second gate insulation layer 126, the second gate layer 127, and the inter-insulation layer 128 are spaced between the two. The coupling capacitance of the prior art is formed by the film layer where the first gate layer 125 and the first source and drain layer 129 are located. The technical solution of the present application increases the distance between the two electrodes in the overlapping part, and the metal electrode plate is replaced by a conductive semiconductor material, which can also reduce the coupling capacitance.

[0107] exist Fig.10 In the embodiment, the light emitting control line EM includes a first sub-segment EM1, a second sub-segment EM2 and a third sub-segment EM3 which are connected to each other. The first sub-segment EM1 and the third sub-segment EM3 extend along the first direction X, and the second sub-segment EM2 is arranged at an angle to the first sub-segment EM1 and the third sub-segment EM3; that is, the first sub-segment EM1 and the first light emitting channel have an overlapping portion, and the third sub-segment EM3 and the first reset active portion T8A have the first overlapping portion N1.

[0108] exist Fig. 9 On the basis of Fig.10 Part of the light-emitting control line EM is moved downward to avoid overlapping of the light-emitting control line EM and the conductive segment belonging to the first node A in the first light-emitting active portion T5A, thereby further reducing the coupling capacitance between the light-emitting control line EM and the conductive segment in the area where the first node A is located, improving the abnormality of the potential of the first node A, and improving the display effect of the display panel 100.

[0109] See also Figure 4 and Fig.11 , Fig.11 for Figure 4The second source-drain layer 131 includes a data signal line Data, a longitudinal high potential line Vdd2 and a fifth connection electrode 131a arranged at intervals along the first direction X. The data signal line Data, the longitudinal high potential line Vdd2 and the fifth connection electrode 131a all extend along the second direction Y. The data signal line Data passes through a via hole and is connected to the second connection electrode 129a. The longitudinal high potential line Vdd2 passes through a via hole and is connected to the transverse high potential line Vdd1.

[0110] In this embodiment, one end of the fifth connection electrode 131a is connected to the fourth connection point M4 through a via hole, and the other end of the fifth connection electrode 131a is connected to the anode of the light emitting device 211b. It should be noted that, since the positions of the anodes of the sub-pixel units 211 of different colors are different, the lengths of the fifth connection electrodes 131a of the sub-pixel units 211 of different colors are different.

[0111] The present application also provides a display device, which includes the above-mentioned display panel. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0112] The present application discloses a display panel and a display device; the display panel includes a pixel driving circuit including a switch transistor, a driving transistor, a first light-emitting transistor and a first reset crystal connected to a first node, the gate of the first light-emitting transistor is connected to a light-emitting control line, a conductive segment in the area where the first node is located is located in an active layer, the light-emitting control line is located in a first source-drain layer, and the conductive segment and the light-emitting control line have an overlapping portion; the present application replaces the conductive segment from a metal layer with a conductive semiconductor layer by increasing the spacing between the light-emitting control line and the conductive segment, thereby reducing the coupling capacitance between the light-emitting control line and the first node, improving the abnormality of the potential of the first node, and improving the display effect of the display panel.

[0113] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0114] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a plurality of sub-pixel units, each of which is provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, wherein the pixel driving circuit comprises a switch transistor connected to a first node, a driving transistor, a first light-emitting transistor and a first reset transistor, and a gate of the first light-emitting transistor is connected to a light-emitting control line; wherein the display panel comprises: substrate substrate; An active layer is disposed on one side of the substrate; A first gate layer is disposed on a side of the active layer away from the substrate; A second gate layer is disposed on a side of the first gate layer away from the base substrate; A first source-drain electrode layer is disposed on a side of the second gate layer away from the substrate; The active layer includes a conductive segment in a region where the first node is located, the first source-drain electrode layer includes the light-emitting control line, and the conductive segment and the light-emitting control line have an overlapping portion.

2. The display panel according to claim 1, characterized in that: The active layer includes a switch active portion of the switch transistor, a first light emitting active portion of the first light emitting transistor, a first reset active portion of the first reset transistor, and an active connecting section, wherein the active connecting section extends along a first direction, the switch active portion, the first light emitting active portion, and the first reset active portion all extend along a second direction, and the first light emitting active portion and the first reset active portion are spaced apart along the first direction; Among them, the switch active part and the first light-emitting active part are connected to a first connection point, one end of the active connection section is connected to the first connection point, the other end of the active connection section is connected to the first reset active part, and the light-emitting control line and the first reset active part have a first overlapping part.

3. The display panel according to claim 2, characterized in that: The first light emitting active portion includes a first light emitting channel, and the light emitting control line has a second overlapping portion with the first light emitting active portion between the first light emitting channel and the first connection point.

4. The display panel according to claim 2, characterized in that: The light-emitting control line comprises a first sub-segment, a second sub-segment and a third sub-segment connected to each other, the first sub-segment and the third sub-segment extend along the first direction, and the second sub-segment is arranged at an angle to the first sub-segment and the third sub-segment; The first light emitting active portion includes a first light emitting channel, the first sub-segment and the first light emitting channel have an overlapping portion, and the third sub-segment and the first resetting active portion have the first overlapping portion.

5. The display panel according to claim 2, characterized in that: The first gate layer includes a first light emitting gate of the first light emitting transistor; Among them, the first end of the first light-emitting gate is arranged between the first light-emitting active part and the first reset active part, and the first end of the first light-emitting gate is electrically connected to the light-emitting control line, and the second end of the first light-emitting gate extends toward the first light-emitting active part and overlaps with the first light-emitting active part.

6. The display panel according to claim 5, characterized in that: The pixel driving circuit further includes a second light emitting transistor connected to the driving transistor at a second node, the second light emitting transistor including a second light emitting active portion located in the active layer and a second light emitting gate located in the first gate layer; The second light emitting active portion extends along the second direction and is arranged on a side of the first reset active portion away from the first light emitting active portion, the first end of the second light emitting gate is arranged between the second light emitting active portion and the first reset active portion, and the first end of the first light emitting gate is electrically connected to the light emitting control line, and the second end of the second light emitting gate extends toward the second light emitting active portion and overlaps with the second light emitting active portion.

7. The display panel according to claim 5, characterized in that: The active part further includes a driving active part of the driving transistor, a first end of the driving active part is connected to the switch active part, and a second end of the driving active part is connected to a second connection point.

8. The display panel according to claim 5, characterized in that: The pixel driving circuit further comprises a compensation transistor, a first electrode of the compensation transistor is connected to the second node, and a second electrode of the compensation transistor is connected to the gate of the driving transistor; The active part includes a first compensation active part and a second compensation active part of the compensation transistor, one end of the first compensation active part and the second light emitting active part are connected to a second connection point, and the other end of the first compensation active part is connected to the second compensation active part; Among them, the first gate layer includes a first control line extending along a first direction and a first extension segment connected to the first control line, the first extension segment extends along the second direction, the first control line has an overlapping portion with the switch active portion and the first compensation active portion, and the first extension segment has an overlapping portion with the second compensation active portion.

9. The display panel according to claim 8, characterized in that: The pixel driving circuit further includes a second light emitting transistor, a second reset transistor, a third reset transistor and a storage capacitor; The first electrode of the switch transistor is connected to the data signal line, the second electrode of the switch transistor is connected to the first node, and the gate of the switch transistor is connected to the first control line; The first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the gate of the driving transistor is connected to a third node; The first electrode of the compensation transistor is connected to the third node, the second electrode of the compensation transistor is connected to the second node, and the gate of the compensation transistor is connected to the first control line; A first electrode of the first reset transistor is connected to a first reset line, a second electrode of the first reset transistor is connected to the first node, and a gate of the first reset transistor is connected to a second control line; A first electrode of the second reset transistor is connected to a second reset line, a second electrode of the second reset transistor is connected to the third node, and a gate of the second reset transistor is connected to a third control line; A first electrode of the third reset transistor is connected to a third reset line, a second electrode of the third reset transistor is connected to an anode of the light emitting device, and a gate of the third reset transistor is connected to the second control line; A first electrode of the first light emitting transistor is connected to a high potential line, and a second electrode of the first light emitting transistor is connected to the first node; The first electrode of the second light emitting transistor is connected to the second node, the second electrode of the second light emitting transistor is connected to the anode of the light emitting device, and the gate of the second light emitting transistor is connected to the light emitting control line; The first plate of the storage capacitor is connected to the high potential line, and the second plate of the storage capacitor is connected to the third node.

10. A display device, characterized in that: The display device includes the display panel as described in any one of items 1 to 9 above.

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