Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a substrate, a first insulating layer, at least one first wire, a second insulating layer and at least one second wire which are sequentially laminated. The orthographic projection of at least part of the first wires on the substrate and the orthographic projection of at least part of the second wires on the substrate have a first overlapping position, the orthographic projection of at least part of the first wires on the substrate and the orthographic projection of at least part of the second wires on the substrate have a second overlapping position, and the first overlapping position is provided with a first via hole. The second overlapping part is provided with a second via hole, and the second wire is electrically connected with the corresponding first wire through the first via hole. The second via hole is formed in the first insulating layer, and the terrain at the first via hole is the same as the terrain at the non-wire-changing hole at the corresponding position through the arrangement of the second via hole, so that the risk of screen-off Mura is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, with the continuous development of the display industry and people's higher and higher requirements for display effects, the outer frame of display devices has a tendency to gradually narrow. For example, narrow-border TVs and full-screen mobile phones increase the display area and improve the screen-to-body ratio by narrowing the non-display area at the edge of the panel.

[0003] In order to further reduce the width of the frame, existing display panels have designed some of the wiring originally set in the frame area in the panel display area, making the product more beautiful. However, the compression of the wiring space can easily cause off-screen Mura (uneven display) in the display area of ​​the display panel. Summary of the invention

[0004] An object of the present invention is to provide a display panel and a display device to solve the problem of screen-off Mura and poor display effect in existing display panels.

[0005] To achieve the above object, the present invention provides a display panel, the display panel comprising

[0006] substrate;

[0007] A first insulating layer is disposed on the substrate;

[0008] At least one first wiring is arranged on a side of the first insulating layer away from the substrate;

[0009] A second insulating layer is disposed on a side of the first insulating layer away from the substrate;

[0010] At least two second routing lines are arranged on a side of the first insulating layer away from the substrate; the second insulating layer is located between the film layer where the first routing lines are located and the film layer where the second routing lines are located; at least part of the first routing lines and at least part of the second routing lines have a first overlap, and the first overlap is provided with a first via hole; the first via hole is provided in the second insulating layer, and the second routing line is electrically connected to the corresponding first routing line through the first via hole; at least part of the first routing lines and at least part of the second routing lines have a second overlap, and the second overlap is provided with a second via hole, and the second via hole is provided in the first insulating layer.

[0011] Optionally, the display panel further comprises: a plurality of data lines, at least some of the data lines being electrically connected to corresponding second lines via corresponding first lines;

[0012] Optionally, at least part of the first routing lines include at least one first connecting line, and at least part of the second routing lines include at least one second connecting line;

[0013] At least some of the data lines are electrically connected to the corresponding second connection lines via the corresponding first connection lines;

[0014] A first connection line and a second connection line electrically connected to the same data line have a first overlap, and at least part of the first connection line is electrically connected to the corresponding second connection line through a first via hole at the first overlap.

[0015] Optionally, at least some of the first routing lines further include at least one first compensation line, and / or at least some of the second routing lines further include at least one second compensation line;

[0016] At least some of the first connection lines and the corresponding second compensation lines have a second overlap, and a second via hole is provided at the second overlap;

[0017] And / or, at least some of the second connection lines have a second overlap with the corresponding first compensation lines, and a second via hole is provided at the second overlap;

[0018] And / or, at least some of the first compensation lines have a first overlap with the corresponding second compensation lines, and at least some of the first compensation lines are electrically connected with the corresponding second compensation lines through a first via hole at the first overlap;

[0019] Optionally, the first compensation line is connected to a DC voltage or a power supply voltage, and / or the second compensation line is connected to a DC voltage or a power supply voltage;

[0020] Optionally, the first compensation line and the corresponding first connection line are arranged at intervals, arranged in the same layer, insulated, and on the same line;

[0021] And / or, the second compensation line and the corresponding second connection line are arranged at intervals, arranged in the same layer, insulated, and on the same line.

[0022] Optionally, the first routing line extends along a first direction, the second routing line extends along a second direction, and the first direction intersects the second direction.

[0023] Optionally, the data line extends along the second direction; and / or, a plurality of data lines are arranged along the first direction;

[0024] Optionally, the data line and the second line are arranged on the same layer;

[0025] Optionally, the second insulating layer is located on a side of the film layer where the first wiring is located that is close to or far from the substrate;

[0026] Optionally, at the first overlap, the one of the first routing and the second routing that is away from the substrate is recessed toward the substrate, and at the second overlap, the one of the first routing and the second routing that is away from the substrate is recessed toward the substrate;

[0027] Optionally, a first insulating layer is provided at the first overlap; and a second insulating layer is provided at the second overlap.

[0028] Optionally, at least some of any first connection lines have a first overlap with the corresponding second connection line, and the first connection line and the corresponding second connection line are electrically connected through a first via hole at the first overlap; the first connection line and the corresponding second compensation line have a second overlap, and a second via hole is provided at the second overlap;

[0029] Optionally, at least some of the second connection lines are located between adjacent data lines; and / or at least some of the second compensation lines are located between adjacent data lines;

[0030] Optionally, the data lines located on both sides of the same second routing line and adjacent to the second routing line are axially symmetrical with a perpendicular bisector of the second routing line parallel to the second direction as a symmetry axis;

[0031] Optionally, among the three adjacent data lines, the spacing between the data line in the middle and the data line on one side is different from the spacing between the data line in the middle and the data line on the other side; the second connecting line is located between two adjacent data lines with a smaller spacing; and / or the second compensation line is located between two adjacent data lines with a smaller spacing;

[0032] Optionally, there is a first central axis between two adjacent data lines, and there is a second central axis between the adjacent first via hole and the second via hole, and the second central axis coincides with the corresponding first central axis.

[0033] Optionally, the display panel includes a display area, and the first via hole and the second via hole are located in the display area.

[0034] Optionally, the display area includes a first display area and second display areas located on two sides of the first display area that are opposite to each other along a first direction, and the data lines located in the second display area are electrically connected to corresponding second connection lines via corresponding first connection lines; the farther the data lines located in the second display area are from the first display area, the longer the length of the first connection lines electrically connected to the data lines is, and the longer the length of the second connection lines electrically connected to the data lines is;

[0035] And / or, a first connection line and a second connection line electrically connecting different data lines, the first connection line and the second connection line have a second overlap, and a second via hole is provided at the second overlap.

[0036] Optionally, the same first routing line has a first overlap with at least one second routing line; and has a second overlap with at least one second routing line;

[0037] And / or, the first routing line and the second routing line are arranged in different layers;

[0038] and / or, the material of the first insulating layer includes an organic material, and / or, the material of the second insulating layer includes an organic material;

[0039] And / or, the aperture of the first via hole is equal to the aperture of the second via hole, and the depth of the first via hole is equal to the depth of the second via hole; and / or, the thickness of the first insulating layer is greater than or equal to the thickness of the second insulating layer.

[0040] Optionally, the display panel further includes a power line located between adjacent data lines;

[0041] Optionally, among the three adjacent data lines, the spacing between the data line in the middle and the data line on one side is different from the spacing between the data line in the middle and the data line on the other side; the power line is located between two adjacent data lines with a larger spacing;

[0042] Optionally, the power line includes a first sub-power line and a second sub-power line, and at least one first sub-power line and at least one second sub-power line are provided between at least part of two adjacent data lines;

[0043] Between at least part of two adjacent data lines, the first sub-power line and the second sub-power line both extend along the second direction and are arranged along the first direction;

[0044] Optionally, the orthographic projections of the first sub-power line and the second sub-power line on the substrate are outside the orthographic projection range of the data line on the substrate;

[0045] Optionally, between at least part of two adjacent data lines, the first sub-power line is electrically connected to the second sub-power line;

[0046] Optionally, between at least part of two adjacent data lines, the first sub-power line and the second sub-power line are in an axisymmetric structure;

[0047] Optionally, the power line and the second line are arranged on the same layer.

[0048] Optionally, the display panel has a display area and a non-display area, the non-display area includes a binding area; the second connecting line is electrically connected to the binding terminal of the binding area;

[0049] Optionally, the display panel further includes:

[0050] A driver chip is arranged in the binding area;

[0051] The second connection line extends from the display area to the binding area and is electrically connected to the driving chip through the binding terminal. The present invention also provides a display device, which includes the display panel as described above.

[0052] The advantages of the present invention are: a display panel and a display device of the present invention, by opening a second via hole at a corresponding position, make the terrain at the line switching hole (i.e., the first via hole) of the first routing and the second routing the same as the terrain at the non-line switching hole at the corresponding position, thereby ensuring the uniformity of the display panel, reducing the risk of screen-off Mura, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic diagram of a top view of a display panel in an embodiment of the present invention;

[0055] Figure 2 for Figure 1 The enlarged schematic diagram of the structure of the display panel in the middle frame a;

[0056] Figure 3 An enlarged schematic diagram of a first routing line and a second routing line in a local area in an embodiment of the present invention;

[0057] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure of the first via hole (ie, the first overlap) at the AA' line;

[0058] Figure 5 for Figure 3 A schematic diagram of the cross-sectional structure of the middle line BB' at the second via hole (ie, the second overlap);

[0059] Figure 6 The display panel in other embodiments of the present invention Figure 3 A schematic diagram of the cross-sectional structure of the first via hole (ie, the first overlap) at the AA' line;

[0060] Figure 7 The display panel in other embodiments of the present invention Figure 3 A schematic diagram of the cross-sectional structure of the second via hole (ie, the second overlapping portion) taken along line BB'.

[0061] Figure 8 FIG. 1 is a schematic diagram of a top view of a display panel in another embodiment of the present invention.

[0062] Fig. 9 This is a schematic diagram of a top view of a display panel in another embodiment of the present invention. The components in the figure are shown as follows:

[0063] Display panel 1; Display area AA;

[0064] First display area AA1; Second display area AA2;

[0065] Non-display area NA; Binding area BA;

[0066] substrate 10;

[0067] First routing line 21; Second routing line 31;

[0068] A first connecting line 211; A first compensation line 212;

[0069] A second connecting line 311; A second compensation line 312;

[0070] A first insulating layer 40; A second insulating layer 50;

[0071] A first via hole 51; A second via hole 41;

[0072] A first sub-power line 32; A second sub-power line 33;

[0073] Data line 34; Driver chip 6;

[0074] Central axis L1; Perpendicular bisector L2. DETAILED DESCRIPTION

[0075] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0076] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0077] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0078] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0079] In related display technologies, the pursuit of extremely narrow borders by terminal products (such as mobile phones, tablets, etc.) has made the wiring of the lower border increasingly tight. In order to narrow the border without compressing the width of the routing signal, the Fanout in AA (FIAA for short) wiring method is currently commonly used, that is, the fan-out routing is arranged in the display area, thereby further narrowing the border of the display panel. However, in the finished display panel, the inventor of the present application found that the display panel has the problem of off-screen Mura, which seriously affects the final display effect of the display panel.

[0080] Based on the above problems in related display technologies, an embodiment of the present invention provides a display panel 1, such as Figures 1 to 5 As shown, the display panel includes a substrate 10 , a first insulating layer 40 , a second insulating layer 50 , at least one first wiring 21 and at least two second wirings 31 .

[0081] The first insulating layer 40 is arranged on the substrate; at least one first routing line 21 is arranged on the side of the first insulating layer 40 away from the substrate 10; the second insulating layer 50 is arranged on the side of the first insulating layer 40 away from the substrate 10; at least two second routing lines 31 are arranged on the side of the first insulating layer 40 away from the substrate 10; the second insulating layer 50 is located between the film layer where the first routing line 21 is located and the film layer where the second routing line 31 is located.

[0082] At least part of the first routing line 21 and at least part of the second routing line 31 have a first overlap, at least part of the first routing line 21 and at least part of the second routing line 31 are at positions relative to each other along the thickness direction of the substrate, for example, the orthographic projection of at least part of the first routing line 21 on the substrate 10 and the orthographic projection of at least part of the second routing line 31 on the substrate 10 have a first overlap, and the first overlap is provided with a first via 51. The first via 51 is provided in the second insulating layer 50, and the second routing line 31 is electrically connected to the corresponding first routing line 21 through the first via 51.

[0083] At least part of the first routing line 21 and at least part of the second routing line 31 have a second overlap, and at least part of the first routing line 21 and at least part of the second routing line 31 are at positions relative to each other along the thickness direction of the substrate, for example, the orthographic projection of at least part of the first routing line 21 on the substrate 10 and the orthographic projection of at least part of the second routing line 31 on the substrate have a second overlap. A second via 41 is provided at the second overlap, and the second via 41 is provided in the first insulating layer 40. The first overlap and the second overlap may correspond to different positions. The orthographic projection of the first via 51 on the substrate 10 is located outside the orthographic projection of the second via 41 on the substrate 10, for example, the orthographic projection of the first via 51 on the substrate 10 and the orthographic projection of the second via 41 on the substrate 10 do not overlap, but are staggered.

[0084] The display panel 1 has a display area AA and a non-display area NA. The display area AA includes a first display area AA1 and second display areas AA2 located on two opposite sides of the first display area AA1 along a first direction X. The non-display area NA includes a binding area BA.

[0085] The second connection line 311 is electrically connected to the bonding terminal of the bonding area BA.

[0086] There may be multiple first lines 21. There may be multiple second lines 31. There is no need to set an electrical connection via at the second overlap between the first line 21 and the second line 31. By setting a second via 41, the one of the first line 21 and the second line 31 that is away from the substrate is recessed at the first overlap and the second overlap to reduce the risk of screen-off Mura. The first line and the second line may be set in different layers.

[0087] The display panel further includes: a driving chip 6 disposed in the binding area BA.

[0088] like Figure 1-Figure 5 As shown in , the display panel 1 further includes a substrate 10 , a first wiring 21 , a second wiring 31 and a driving chip 6 .

[0089] The substrate 10 includes a multi-layer circuit structure, which may be one or more display lines such as a scan signal line, a reset signal line, a drive power line, and a light-emitting signal line. An inorganic insulating film layer is also provided between adjacent circuit structures, and the inorganic insulating film layer is used to insulate and protect the circuit structure to prevent short circuits between adjacent circuit structures. For example, the second connecting line 311 extends from the display area AA to the binding area BA, and is electrically connected to the driver chip 6 through the binding terminal.

[0090] For example, the first wiring 21 extends along a first direction X, and the second wiring 31 extends along a second direction Y. The first direction X intersects with the second direction Y, for example, they are perpendicular to each other.

[0091] At least two first wirings 21 are insulated and arranged on the substrate 10, extending along the first direction X, and arranged along the second direction Y perpendicular to the first direction X. At least two second wirings 31 are insulated and arranged on a side of the first wiring 21 away from the substrate 10, extending along the second direction Y, and arranged along the first direction X. For example, the first wiring 21 is connected to the corresponding second wiring 31 through a via structure, and is combined with the second wiring 31 to form a fan-out wiring.

[0092] like Figure 1 As shown in the figure, the first wiring 21 is arranged in the display area AA, one end of which is electrically connected to the circuit structure in the substrate 10, and the other end of which is electrically connected to the second wiring 31; the end of the second wiring 31 connected to the first wiring 21 is located in the display area AA, and the other end of the second wiring 31 extends to the binding area BA along the second direction Y. By arranging the fan-out wiring in the display area AA, the space occupied by the binding area BA can be reduced, and the lower frame of the display panel 1 can be narrowed to achieve narrow frame display.

[0093] The driving chip 6 is arranged in the binding area BA, which is electrically connected to one end of the second wiring 31 located in the binding area BA, and is electrically connected to other circuit structures in the display panel 1 through the second wiring 31 and the first wiring 21 and transmits display signals, thereby controlling the light emission of the light-emitting device in the display panel 1.

[0094] For example, the same first routing line 21 has a first overlap with at least one second routing line 31, and a second overlap with at least one second routing line 32. For example, the same first routing line 21 has a first overlap with at least one second routing line 31, and a second overlap with at least another second routing line 32. For example, the same first routing line 21 has a first overlap and a second overlap with different second routing lines 31, respectively.

[0095] For example, the first wiring 21 and the second wiring 31 are arranged at the second overlapping position through an insulating spacer of the second insulating layer.

[0096] Specifically, Figure 3 , Figure 4 and Figure 5 As shown in FIG, a first insulating layer 40 is provided between the substrate 10 and the first wiring 21 , and a second insulating layer 50 is provided between the first wiring 21 and the second wiring 31 . The first insulating layer 40 and the second insulating layer 50 are used for insulating and protecting the first wiring 21 and the second wiring 31 , respectively.

[0097] Optionally, the material of the first insulating layer 40 includes an organic material, and / or the material of the second insulating layer 50 includes an organic material.

[0098] A first via hole 51 is provided in the second insulating layer 50, and the first wiring 21 is electrically connected to the corresponding second wiring 31 through the first via hole 51. A second via hole 41 is provided in the first insulating layer 40, and the orthographic projection of the second via hole 41 on the substrate 10 at least partially overlaps with the orthographic projection of the first wiring 21 and the second wiring 31 on the display panel 1, and does not overlap with the orthographic projection of the first via hole 51 on the substrate 10.

[0099] Specifically, among at least a portion of the first routing lines 21, each first routing line 21 has an overlap with the plurality of second routing lines 31, and at the overlap, the orthographic projection of the first routing line 21 on the substrate 10 overlaps with the orthographic projection of the second routing line 31 on the substrate 10. At the overlap, a first via hole 51 or a second via hole 41 is provided in the display panel 1. The orthographic projection of the same first routing line 21 on the substrate 10 only overlaps with the orthographic projection of one first via hole 51 on the substrate 10, but it may overlap with the orthographic projections of multiple second via holes 41 on the substrate 10, that is, only one first via hole 51 electrically connected to the corresponding second routing line 31 is provided on one side of the same first routing line 21, but multiple second via holes 41 may be provided on the side away from the second routing line 31, and by providing the second via holes 41, the thickness of the intersection of the first routing line 21 and other second routing lines 31 can be reduced, thereby causing the second routing line 31 located above the second via hole 41 to be recessed, so that the terrain of other second routing lines 31 at the intersection with the first routing line 21 is the same as the terrain of the second routing line 31 located at the first via hole 51, thereby reducing the phenomenon of different light reflection conditions caused by the first via hole 51 causing the terrain of the second routing line 31 to be recessed, thereby reducing the risk of off-screen Mura, thereby improving the uniformity of the display panel 1. The patterning of the second via 41 can be formed using the same mask template and the same process as other vias in the first insulating layer 40, thereby eliminating screen-off Mura and improving the display effect without increasing production costs or reducing production efficiency.

[0100] For example, the second insulating layer 50 is located on a side of the film layer where the first wiring 21 is located close to or away from the substrate 10. In other embodiments of the present invention, such as Figure 6 and Figure 7As shown in , the second insulating layer 50 can be arranged on the side of the film layer where the first wiring 21 is located close to the substrate 10, and the film layer where the second wiring 31 is located can be arranged between the second insulating layer 50 and the first insulating layer 40, that is, the stacking order of the film layers in the display panel 1 is the substrate 10, the first insulating layer 40, the film layer where the second wiring 31 is located, the second insulating layer 50 and the film layer where the first wiring 21 is located. In this embodiment, the second via 41 can cause the first wiring 21 located above the second via 41 to be recessed, so that the terrain of the first wiring 21 at the intersection with other second wirings 31 is the same as the terrain of the first wiring 21 located at the first via 51, thereby also achieving the effect of reducing the risk of screen-off Mura and improving display uniformity. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0101] See also Figure 4 and Figure 6 For example, at the first overlap, the one of the first trace 21 and the second trace 31 that is away from the substrate 10 is recessed toward the substrate 10. Figure 5 and Figure 7 For example, at the second overlapping portion, the one of the first routing line 21 and the second routing line 31 that is away from the substrate 10 is recessed toward the substrate 10 .

[0102] See also Figure 4 and Figure 6 For example, a first insulating layer 40 is disposed at the first overlap. Figure 5 and Figure 7 For example, a second insulating layer 50 is disposed at the second overlap.

[0103] For example, the display panel also includes a third insulating layer, which is located between the first insulating layer and the substrate, and the third insulating layer is arranged at the second overlap; the third insulating layer is arranged at the first overlap; at the second overlap, one of the first routing and the second routing closer to the substrate contacts the third insulating layer.

[0104] Furthermore, the aperture of the first via 51 is equal to the aperture of the second via 41, and / or the depth of the first via 51 is also equal to the depth of the second via 41, so that the size of the second via 41 is the same as the aperture of the first via 51, thereby making the terrain of the second wiring 31 on the second via 41 the same as the terrain of the second wiring 31 on the first via 51, thereby reducing the screen-off Mura problem caused by the terrain difference.

[0105] Optionally, the thickness of the first insulating layer 40 is greater than or equal to the thickness of the second insulating layer 50, and the second via 41 is disposed on the side of the first insulating layer 40 facing the first wiring 21. When the thickness of the first insulating layer 40 is greater than the thickness of the second insulating layer 50, the second via 41 may not penetrate the first insulating layer 40; when the thickness of the first insulating layer 40 is equal to the thickness of the second insulating layer 50, the second via 41 penetrates the first insulating layer 40. Further, there is a central axis L1 between two adjacent data lines 34, and the spacing between the first via 51 and the central axis L1 is equal to the spacing between the second via 41 and the central axis L1. The orthographic projection of the first via 51 on the substrate 10 and the orthographic projection of the adjacent second via 41 on the substrate 10 are axially symmetrical structures with the central axis L1 as the symmetry axis.

[0106] like Figure 3 As shown, the display panel 1 further includes a power line, which is located between the adjacent data lines 34. For example, the power line and the second wiring 31 are arranged in the same layer.

[0107] For example, the display panel 1 further includes a plurality of data lines 34. For example, the plurality of data lines 34 extend along the second direction Y and are arranged along the first direction X. For example, among three adjacent data lines 34, the spacing between the data line 34 in the middle and the data line 34 on one side is different from the spacing between the data line 34 in the middle and the data line 34 on the other side; the power line is located between two adjacent data lines 34 with a larger spacing.

[0108] For example, the power line includes a first sub-power line 32 and a second sub-power line 33. Among them, the first sub-power line 32, the second sub-power line 33 and the data line 34 are all located in the same conductive layer (for example, a metal layer) as the second wiring 31, and they can be prepared by the same patterning process. The first sub-power line 32 and the second sub-power line 33 can be wirings for transmitting power signals (for example, a high voltage VDD or a low voltage VSS), for example, they can be electrically connected to the first compensation line and / or the second compensation line. The data line 34 can transmit data signals for the display panel 1. In other embodiments of the present invention, the specific applications of the first sub-power line 32, the second sub-power line 33 and the data line 34 are not limited, and they can also be used as wirings for other functions.

[0109] For example, the display panel 1 further includes a plurality of data lines 34, and at least some of the data lines 34 are electrically connected to the corresponding second lines 31 via the corresponding first lines 21. For example, at least some of the first lines 21 include at least one first connection line 211, and at least some of the second lines 31 include at least one second connection line 311; at least some of the data lines 34 are electrically connected to the corresponding second connection line 311 via the corresponding first connection line 211. For example, the data lines and the second lines are arranged in the same layer. Multiple structures arranged in the same layer can be obtained by patterning the same film layer, thereby simplifying the process. Figure 8 The first connection line 211 and the second connection line 311 are exemplarily drawn. The first connection line 211 and the second connection line 311 may have a first overlap. The first connection line 211 and the second connection line 311 may be electrically connected through a first via 51 at the first overlap.

[0110] For example, at least some of the first wirings 21 include at least one first compensation line 212, and / or, at least some of the second wirings 31 include at least one second compensation line 312. For example, the first compensation line 212 is connected to a DC voltage or a power supply voltage, and / or, the second compensation line 312 is connected to a DC voltage or a power supply voltage. The display panel 1 also includes a pixel circuit, the first compensation line 212 is electrically connected to the pixel circuit, and / or, the second compensation line 312 is electrically connected to the pixel circuit. The first compensation line 212 can transmit an initialization signal and a power supply signal, and / or, the second compensation line 312 can transmit an initialization signal and a power supply signal. The pixel circuit may include a driving transistor, one or more initialization transistors, a data writing transistor, a threshold compensation transistor, and a part or all of a light emitting control transistor. The initialization transistor can be used to initialize at least one of the gate, the first electrode (e.g., the source electrode), the second electrode (e.g., the drain electrode), and the first electrode of the light emitting element of the driving transistor. The initialization transistor can be connected to an initialization signal. The driving transistor and the light emitting element can be connected in series between a first power line (which can be used to transmit a high voltage VDD) and a second power line (which can be used to transmit a low voltage VSS). The first electrode of the light-emitting element may be electrically connected to the pixel circuit. The first electrode of the light-emitting element may be an anode. The data writing transistor may be connected between the data line and the first electrode (e.g., source) of the driving transistor. The threshold compensation transistor may be connected between the gate and the second electrode of the driving transistor. The pixel circuit may include a first initialization transistor, which may be used to initialize the gate of the driving transistor. The pixel circuit may include a second initialization transistor, which may be used to initialize at least one of the first electrodes of the light-emitting element. The pixel circuit may include a third initialization transistor, which may be used to initialize the first electrode (e.g., source) or the second electrode (e.g., drain) of the driving transistor.

[0111] By setting the first compensation line 212 and / or the second compensation line 312, the first compensation line 212, the second compensation line 312, the first connection line, and the second connection line are evenly distributed in the display area, thereby reducing the risk of screen-off Mura. If the first connection line and the second connection line are only set in a local area, there will be a screen-off Mura problem.

[0112] Specifically, Figure 1 and Figure 2As shown in FIG. 1 , in the display area AA, a plurality of data lines 34 extend along the second direction Y and are arranged along the first direction X, and the data lines 34 are provided in the first display area AA1 and the second display area AA2. The first wiring 21 includes a first connection line 211 and a first compensation line 212, and the second wiring 31 includes a second connection line 311 and a second compensation line 312. The first connection line 211 and the second connection line 311 are provided in the two second display areas AA2 located on both sides of the first display area AA1, and the first compensation line 212 and the second compensation line 312 can extend from the first display area AA1 to the second display area AA2 or be directly provided in the second display area AA2.

[0113] For example, the first compensation line 212 and the corresponding first connection line 211 are arranged at intervals, and / or arranged in the same layer, and / or arranged in insulation, and / or arranged on the same line. There may be a break 35 between the co-linear first compensation line 212 and the corresponding first connection line 211, such as Figure 8 shown.

[0114] For example, the second compensation line 312 and the corresponding second connection line 311 are arranged at intervals, and / or arranged in the same layer, and / or arranged in insulation, and / or arranged on the same line. There may be a break 35 between the co-linear second compensation line 312 and the corresponding second connection line 311, such as Figure 8 shown.

[0115] The first compensation line 212 and the corresponding first connection line 211 are disposed in the same layer and on the same line, and the first compensation line 212 and the corresponding first connection line 211 are disposed at intervals and are insulated.

[0116] The second compensation line 312 and the corresponding second connection line 311 are disposed in the same layer and on the same line, and the second compensation line 312 and the corresponding second connection line 311 are disposed at intervals and maintained insulated.

[0117] At least one of the first compensation line 212 and the second compensation line 312 can be connected to a DC voltage or a power supply voltage.

[0118] For example, the display panel includes a display area, and the first via hole and the second via hole are located in the display area.

[0119] For example, the display area includes a first display area and a second display area located on two sides of the first display area opposite to each other along a first direction. In the data lines 34 in the second display area AA2, the data lines are electrically connected to the corresponding second connection lines 311 via the corresponding first connection lines 211, respectively. Moreover, the farther the distance between the data line 34 and the first display area AA1 is, the longer the length of the first connection line 211 electrically connected to the data line 34 is, and / or the longer the length of the second connection line 311 electrically connected to the data line 34 is; for example, the longer the length of the first connection line 211 and the second connection line 311 electrically connected to the data line 34 is.

[0120] For example, the first connection line 211 and the second connection line 311 that are electrically connected to the same data line 34 have a first overlap (for example, the orthographic projection of the first connection line 211 on the substrate and the orthographic projection of the second connection line 311 on the substrate have a first overlap), and the first connection line 211 is electrically connected to the corresponding second connection line 311 through a first via 51 located at the first overlap, so that the data line 34 is electrically connected to the second connection line 311 through the first connection line 211, and then electrically connected to the driver chip 6 through the second connection line 311, thereby realizing the transmission of data signals.

[0121] For example, at least a portion of the data lines 34 and the corresponding first connection lines 211 have a first overlap, and at least a portion of the data lines 34 and the corresponding first connection lines 211 are electrically connected through the first via holes 51 at the first overlap.

[0122] For example, in the first connection line 211 and the second connection line 311 electrically connected to different data lines 34, the first connection line 211 and the second connection line 311 have a second overlap (for example, the orthographic projection of the first connection line 211 on the substrate and the orthographic projection of the second connection line 311 on the substrate have a second overlap), and a second via 41 is provided at the second overlap, thereby ensuring that data transmission will not short-circuit while reducing the terrain of the second connection line 311 in the second overlap, so that the terrain of the second connection line 311 at the second overlap is the same as the terrain of the second connection line 311 at the first overlap, thereby reducing the risk of screen-off Mura. In the data lines 34 in the second display area AA2, the data lines 34 are electrically connected to the corresponding second connection lines 311 via the corresponding first connection lines 211, respectively, and the first connection lines 211 electrically connected to the data lines 34 have the same length. The farther the distance between the data lines 34 and the first display area AA1 is, the farther the distance between the connection position of the data lines 34 and the first connection lines 211 and the binding area is.

[0123] Furthermore, at least some of the first connection lines 211 and the corresponding second compensation lines 312 have a second overlap (for example, at least some of the orthographic projections of the first connection lines 211 on the substrate and the orthographic projections of the corresponding second compensation lines 312 on the substrate have a second overlap), and a second via 41 is provided at the second overlap.

[0124] For example, at least some of the second connection lines 311 and the corresponding first compensation lines 212 have a second overlap (for example, the orthographic projection of at least some of the second connection lines 311 on the substrate and the orthographic projection of the corresponding first compensation lines 212 on the substrate have a second overlap), and a second via 41 is provided at the second overlap.

[0125] By setting the second via 41, in different second overlaps, the terrain of the second connecting line 311 and the second compensation line 312 and between the second connecting line 311 and the first compensation line 212 is lowered in the second overlap while maintaining insulation, so that the terrain of the second wiring 31 at the second overlap is the same as that of the second wiring 31 at the first overlap, thereby reducing the risk of screen-off Mura.

[0126] Furthermore, at least some of the first compensation lines 212 have a first overlap with the corresponding second compensation lines 312 (for example, the orthographic projection of at least some of the first compensation lines 212 on the substrate and the orthographic projection of the corresponding second compensation lines 312 on the substrate have a first overlap), and at least some of the first compensation lines 212 are electrically connected to the corresponding second compensation lines 312 through the first vias 51 at the first overlap, thereby enabling the first compensation lines 212 to be connected to the corresponding second compensation lines 312, thereby transmitting a DC voltage or a power supply voltage to the display panel.

[0127] For example, for any first connection line 211 among at least some of the first connection lines 211, the first connection line 211 and the corresponding second connection line 311 have a first overlap (for example, the orthographic projection of the first connection line 211 on the substrate 10 and the orthographic projection of the corresponding second connection line 311 on the substrate 10 have a first overlap), and the first connection line 211 and the corresponding second connection line 311 are electrically connected through the first via 51 at the first overlap; the first connection line 211 and the corresponding second compensation line 312 have a second overlap (for example, the orthographic projection of the first connection line 211 on the substrate and the orthographic projection of the corresponding second compensation line 312 on the substrate have a second overlap), and a second via 41 is provided at the second overlap.

[0128] For example, at least some of the second connection lines 311 are located between adjacent data lines 34; and / or at least some of the second compensation lines 312 are located between adjacent data lines;

[0129] For example, the data lines 34 located on both sides of the same second routing line 31 and adjacent to the second routing line 31 are axisymmetric with the perpendicular bisector L2 of the second routing line 31 parallel to the second direction Y as the axis of symmetry.

[0130] For example, among three adjacent data lines 34, the spacing between the data line 34 in the middle and the data line 34 on one side is different from the spacing between the data line 34 in the middle and the data line 34 on the other side; the second connection line 311 is located between two adjacent data lines 34 with a smaller spacing; and / or the second compensation line 312 is located between two adjacent data lines 34 with a smaller spacing;

[0131] For example, there is a first central axis L1 between two adjacent data lines 34 , and there is a second central axis between the adjacent first via hole 51 and the second via hole 41 , and the second central axis coincides with the corresponding first central axis L1 .

[0132] like Figure 3 As shown in , at least one first sub-power line 32 and at least one second sub-power line 33 are provided between at least two adjacent data lines 34. For example, between at least two adjacent data lines 34, the first sub-power line 32 and the second sub-power line 33 extend along the second direction Y and are arranged along the first direction X, and the orthographic projections of the first sub-power line 32 and the second sub-power line 33 on the substrate 10 are located outside the orthographic projection range of the second wiring 31 and / or the data line 34 on the substrate 10. Specifically, between at least two adjacent data lines, the first sub-power line 32 and the second sub-power line 33 are electrically connected. Between at least two adjacent data lines, the first sub-power line and the second sub-power line are in an axisymmetric structure, and the first sub-power line 32 and the second sub-power line 33 are in an axisymmetric structure with the central axis L1 between at least two adjacent data lines 34 as the symmetry axis, and are electrically connected to each other.

[0133] The plurality of data lines 34 extend along the second direction Y, and / or the plurality of data lines 34 are arranged along the first direction X, the second connection line 311 is located between adjacent data lines 34, and the orthographic projection of the data line 34 on the substrate 10 is located outside the orthographic projection range of the second line 31 on the substrate 10. Specifically, the data lines 34 located on both sides of the same second line 31 and adjacent to the second line 31 are axially symmetrical with the perpendicular bisector L2 of the second line 31 parallel to the second direction Y as the symmetry axis.

[0134] For example, the first via holes and the second via holes may be evenly distributed in the display area, and the density of the via holes (including the first via holes and the second via holes) at various positions in the display area is equal.

[0135] The embodiment of the present invention further provides a display device, including the display panel 1 as described above. The display device may be an OLED (Organic Light-Emitting Diode) display device. The display device may be any display device with a display function, such as a mobile phone, a laptop computer, a tablet computer, etc.

[0136] In the display panel and the display device provided in the embodiments of the present invention, a second via hole is opened at a corresponding position so that the terrain at the line switching hole (i.e., the first via hole) where the first wiring and the second wiring are switched is the same as the terrain at the non-line switching hole at the corresponding position (corresponding to the second via hole position), thereby ensuring the uniformity of the display panel, reducing the risk of screen-off Mura, and improving the display effect of the display panel.

[0137] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. A display panel, characterized in that: include: substrate; A first insulating layer, disposed on the substrate; At least one first wiring is arranged on a side of the first insulating layer away from the substrate; A second insulating layer, disposed on a side of the first insulating layer away from the substrate; At least two second routing lines are arranged on a side of the first insulating layer away from the substrate; the second insulating layer is located between the film layer where the first routing line is located and the film layer where the second routing line is located; at least part of the first routing line and at least part of the second routing line have a first overlap, and the first overlap is provided with a first via hole; the first via hole is provided in the second insulating layer, and the second routing line is electrically connected to the corresponding first routing line through the first via hole; at least part of the first routing line and at least part of the second routing line have a second overlap, and the second overlap is provided with a second via hole, and the second via hole is provided in the first insulating layer.

2. The display panel according to claim 1, wherein: The display panel further comprises: a plurality of data lines, at least some of the data lines being electrically connected to the corresponding second wirings via the corresponding first wirings; Preferably, at least some of the first routing lines include at least one first connecting line, and at least some of the second routing lines include at least one second connecting line; At least some of the data lines are electrically connected to the corresponding second connection lines via the corresponding first connection lines; The first connection line and the second connection line are electrically connected to the same data line, the first connection line and the second connection line have a first overlap, and at least part of the first connection line is electrically connected to the corresponding second connection line through the first via hole at the first overlap.

3. The display panel according to claim 2, wherein: At least some of the first routing lines further include at least one first compensation line, and / or at least some of the second routing lines further include at least one second compensation line; At least some of the first connecting lines have a second overlapping portion with the corresponding second compensation lines, and the second overlapping portion is provided with the second via hole; And / or, at least some of the second connecting lines have a second overlap with the corresponding first compensation lines, and the second overlapping part is provided with the second via hole; and / or, at least some of the first compensation lines have a first overlap with the corresponding second compensation lines, and at least some of the first compensation lines are electrically connected to the corresponding second compensation lines through the first via holes at the first overlap; preferably, the first compensation lines are connected to a DC voltage or a power supply voltage, and / or the second compensation lines are connected to a DC voltage or a power supply voltage; Preferably, the first compensation line and the corresponding first connecting line are spaced apart, arranged in the same layer, insulated, and collinear; and / or the second compensation line and the corresponding second connecting line are spaced apart, arranged in the same layer, insulated, and collinear.

4. The display panel according to claim 2, wherein: The first routing line extends along a first direction, the second routing line extends along a second direction, and the first direction intersects the second direction. Preferably, the data line extends along the second direction; and / or, a plurality of the data lines are arranged along the first direction; Preferably, the data line and the second wiring are arranged in the same layer; Preferably, the second insulating layer is located on a side of the film layer where the first wiring is located close to or away from the substrate; Preferably, at the first overlap, the one of the first routing and the second routing that is away from the substrate is recessed toward the substrate, and at the second overlap, the one of the first routing and the second routing that is away from the substrate is recessed toward the substrate; Preferably, the first insulating layer is disposed at the first overlap; and the second insulating layer is disposed at the second overlap.

5. The display panel according to claim 3, wherein: At least one of the first connection lines of some of the first connection lines has a first overlap with the corresponding second connection line, and the first connection line is electrically connected to the corresponding second connection line through the first via hole at the first overlap; the first connection line has a second overlap with the corresponding second compensation line, and the second overlap is provided with a second via hole; Preferably, at least part of the second connection lines are located between adjacent data lines; and / or, at least part of the second compensation lines are located between adjacent data lines; Preferably, the data lines located on both sides of the same second routing line and adjacent to the second routing line are axially symmetrical with a perpendicular bisector of the second routing line parallel to the second direction as a symmetry axis; Preferably, among the three adjacent data lines, the spacing between the data line located in the middle and the data line located on one side is different from the spacing between the data line located in the middle and the data line located on the other side; the second connecting line is located between two adjacent data lines with a smaller spacing; and / or the second compensation line is located between two adjacent data lines with a smaller spacing; Preferably, there is a first central axis between two adjacent data lines, and there is a second central axis between adjacent first via holes and second via holes, and the second central axis coincides with the corresponding first central axis.

6. The display panel according to claim 2, wherein: The display panel includes a display area, the first via hole and the second via hole are located in the display area, Preferably, the display area includes a first display area and second display areas located on two sides of the first display area that are opposite to each other along a first direction, and the data lines located in the second display area are electrically connected to the corresponding second connection lines via the corresponding first connection lines; the farther the data lines located in the second display area are from the first display area, the longer the length of the first connection lines electrically connected to the data lines is, and the longer the length of the second connection lines electrically connected to the data lines is; And / or, the first connection line and the second connection line that are electrically connected to different data lines have a second overlapping portion, and a second via hole is provided at the second overlapping portion.

7. The display panel according to claim 1, wherein: The same first routing line has the first overlapping part with at least one of the second routing lines; and has the second overlapping part with at least one of the second routing lines; and / or, the material of the first insulating layer includes an organic material, and / or, the material of the second insulating layer includes an organic material; And / or, the aperture of the first via hole is equal to the aperture of the second via hole, and the depth of the first via hole is equal to the depth of the second via hole; And / or, the thickness of the first insulating layer is greater than or equal to the thickness of the second insulating layer.

8. The display panel according to claim 2, wherein: The display panel further includes a power line located between adjacent data lines; Preferably, among the three adjacent data lines, the spacing between the data line located in the middle and the data line located on one side is different from the spacing between the data line located in the middle and the data line located on the other side; the power line is located between two adjacent data lines with a larger spacing; Preferably, the power line comprises a first sub-power line and a second sub-power line, and at least one of the first sub-power line and at least one of the second sub-power line is provided between at least part of two adjacent data lines; Between at least part of two adjacent data lines, the first sub-power line and the second sub-power line both extend along the second direction and are arranged along the first direction; Preferably, the orthographic projections of the first sub-power line and the second sub-power line on the substrate are outside the orthographic projection range of the data line on the substrate; Preferably, between at least part of two adjacent data lines, the first sub-power line is electrically connected to the second sub-power line; Preferably, between at least part of two adjacent data lines, the first sub-power line and the second sub-power line are in an axisymmetric structure; Preferably, the power line and the second line are arranged in the same layer.

9. The display panel according to claim 2, wherein: The display panel has a display area and a non-display area, the non-display area includes a binding area; the second connecting line is electrically connected to the binding terminal of the binding area; Preferably, the display panel further includes: A driving chip, arranged in the binding area; The second connection line extends from the display area to the binding area, and is electrically connected to the driving chip through the binding terminal.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-9.

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