Silicon wafer suitable for high-voltage device and manufacturing method thereof
By forming an epitaxial stacked layer on the support wafer and performing multiple epitaxial growths and precisely controlling the silicon layer thickness, the problems of resistivity non-uniformity and defects in high-voltage devices are solved, thereby improving silicon wafer quality and device performance.
Patent Information
- Application Number
- CN202411368589.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-10
AI Technical Summary
In existing technologies, the silicon wafer resistivity of high-voltage devices is inconsistent, and there are poor uniformity of doping concentration and local defects, which leads to uneven current distribution in the device, especially during avalanche breakdown.
By forming an epitaxial stack layer on a support wafer, multiple epitaxial silicon layers are grown sequentially using multiple epitaxial growth processes. The thickness and quality of each silicon layer are adjusted to form an epitaxial stack layer with good resistivity uniformity. The support wafer is then removed through processes such as grinding, chamfering, and polishing to obtain a silicon wafer with high resistivity and low oxygen content.
It improves the resistivity uniformity of silicon wafers, reduces internal defects, and enhances the performance of high-voltage devices, especially in terms of stability and current distribution uniformity during avalanche breakdown.
Smart Images
Figure CN119287510A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a silicon wafer suitable for high-voltage devices and a manufacturing method thereof. Background Art
[0002] High voltage (HV) devices are mainly used in screen driver chips. High voltage devices need to meet an operating voltage of more than 200V when working. Therefore, high performance requirements are placed on high voltage devices.
[0003] The single crystal wafers currently obtained by the Czochralski method and the zone melting method have poor resistivity consistency after slicing, grinding, polishing and other process treatments. The silicon wafers have poor doping concentration uniformity, large doping gradients or large local defects, which may cause the current of devices (especially high-voltage devices or high-power devices) manufactured using the silicon wafers to be unevenly distributed, especially when the devices are in avalanche breakdown. The impact on the devices is great.
[0004] Therefore, how to improve the uniformity of the resistivity of silicon wafers and reduce the defects inside the silicon wafers, thereby improving the performance of high-voltage devices manufactured from the silicon wafers, is a technical problem that needs to be solved urgently. Summary of the invention
[0005] The present invention provides a silicon wafer suitable for high-voltage devices and a manufacturing method thereof, which are used to improve the consistency of the resistivity of the silicon wafer and reduce the defects inside the silicon wafer, thereby improving the performance of the high-voltage device manufactured from the silicon wafer.
[0006] According to some embodiments, the present invention provides a method for manufacturing a silicon wafer suitable for a high voltage device, comprising the following steps:
[0007] Providing a support wafer, the support wafer comprising a first surface and a second surface that are oppositely distributed along a first direction;
[0008] An epitaxial stacking layer is formed on the first surface of the supporting wafer, and the supporting wafer is removed. The epitaxial stacking layer includes a plurality of epitaxial silicon layers stacked in sequence along the first direction. The plurality of epitaxial silicon layers are grown in sequence through multiple epitaxial growth processes, and the epitaxial stacking layer is used as a silicon wafer.
[0009] In some embodiments, the thicknesses of the plurality of epitaxial silicon layers in the epitaxial stack layer are all the same; or,
[0010] At least two epitaxial silicon layers in the epitaxial stack layer have different thicknesses.
[0011] In some embodiments, the specific steps of forming an epitaxial stack layer on the first surface of the supporting wafer include:
[0012] Acquire the number of the epitaxial silicon layers in the epitaxial stack layer according to the preset thickness of the epitaxial stack layer as the preset number of layers;
[0013] The preset number of epitaxial silicon layers is formed one by one by adopting multiple epitaxial growth processes.
[0014] In some embodiments, the specific steps of obtaining the number of epitaxial silicon layers in the epitaxial stack layer according to the preset thickness of the epitaxial stack layer include:
[0015] The number of layers n of the epitaxial silicon layer in the epitaxial stack layer is calculated using the following formula:
[0016] n=(T+R) / D
[0017] Wherein, T is the preset thickness of the epitaxial stack layer, D is the thickness of a single epitaxial silicon layer grown by the epitaxial growth process, and R is a fixed compensation thickness.
[0018] In some embodiments, the specific steps of forming the epitaxial stack layer on the first surface of the supporting wafer and removing the supporting wafer include:
[0019] The following cycle steps are performed multiple times until the preset number of epitaxial silicon layers is formed, and the cycle steps include:
[0020] Using a primary epitaxial growth process to form a layer of the epitaxial silicon layer located above the first surface of the supporting wafer;
[0021] A portion of the support wafer is removed.
[0022] In some embodiments, the thickness of the support wafer removed in each of the cycle steps is the same as the thickness of the formed epitaxial silicon layer.
[0023] In some embodiments, the specific steps of forming an epitaxial stacking layer on the first surface of the supporting wafer and removing the supporting wafer include:
[0024] Using multiple epitaxial growth processes to form a plurality of epitaxial silicon layers one by one, and using all of the epitaxial silicon layers together as the epitaxial stacking layer;
[0025] The support wafer below the epitaxial stack layer is removed.
[0026] In some embodiments, after forming the epitaxial stacking layer on the first surface of the supporting wafer and removing the supporting wafer, the following steps are further included:
[0027] Part of the epitaxial stack layer is removed to adjust the thickness of the epitaxial stack layer.
[0028] According to some other embodiments, the present invention further provides a silicon wafer suitable for a high voltage device, comprising:
[0029] The epitaxial stack layer comprises a plurality of epitaxial silicon layers stacked in sequence, wherein the plurality of epitaxial silicon layers are grown in sequence through multiple epitaxial growth processes.
[0030] In some embodiments, the thicknesses of the plurality of epitaxial silicon layers in the epitaxial stack layer are all the same; or,
[0031] At least two epitaxial silicon layers in the epitaxial stack layer have different thicknesses.
[0032] The silicon wafer and manufacturing method thereof provided by the present invention are applied to high-voltage devices. An epitaxial stacking layer is formed on the first surface of a supporting wafer. The epitaxial stacking layer includes a plurality of epitaxial silicon layers stacked in sequence along the first direction. The plurality of epitaxial silicon layers are grown in sequence through multiple epitaxial growth processes. After the supporting wafer is removed, only the epitaxial stacking layer is used as a silicon wafer. Since the epitaxial silicon layer grown by the epitaxial growth process has good resistivity uniformity, not only has fewer defects, but also has the characteristics of high resistance and low oxygen content, the resistivity uniformity of the silicon wafer as a whole can be improved, and the defects inside the silicon wafer can be reduced, thereby improving the performance of the high-voltage device manufactured by the silicon wafer. The present invention forms the epitaxial stacking layer through multiple epitaxial growth processes, so that the quality and thickness of each epitaxial silicon layer can be better adjusted, thereby better adjusting the thickness and quality of the entire epitaxial stacking layer, so as to further improve the quality of the silicon wafer, so that the resistivity consistency of the silicon wafer is further improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 is a flow chart of a method for manufacturing a silicon wafer suitable for high voltage devices in a specific embodiment of the present invention;
[0034] Figure 2 is a schematic diagram of a structure of a supporting wafer in a specific embodiment of the present invention;
[0035] Figure 3 is a schematic diagram of a structure after an epitaxial silicon layer is formed on a supporting wafer in a specific embodiment of the present invention;
[0036] Figure 4 It is a structural schematic diagram of a specific embodiment of the present invention after an epitaxial stacking layer is formed on a supporting wafer and the supporting wafer is removed;
[0037] Figure 5 It is another structural schematic diagram of a specific embodiment of the present invention after an epitaxial stacking layer is formed on a supporting wafer. DETAILED DESCRIPTION
[0038] The specific implementation of the silicon wafer applicable to high voltage devices and the manufacturing method thereof provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0039] This specific embodiment provides a method for manufacturing a silicon wafer suitable for high voltage devices. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a silicon wafer suitable for high voltage devices in a specific embodiment of the present invention. Figure 1 As shown, the method for manufacturing a silicon wafer suitable for high voltage devices comprises the following steps:
[0040] Step S11, providing a supporting wafer, wherein the supporting wafer includes a first surface and a second surface that are relatively distributed along a first direction;
[0041] Step S12, forming an epitaxial stacking layer on the first surface of the supporting wafer, and removing the supporting wafer, the epitaxial stacking layer includes a plurality of epitaxial silicon layers stacked in sequence along the first direction, the plurality of epitaxial silicon layers are formed by sequentially growing through multiple epitaxial growth processes, and the epitaxial stacking layer is used as a silicon wafer.
[0042] Figure 2 is a schematic diagram of a structure of a supporting wafer in a specific embodiment of the present invention, Figure 3 is a schematic diagram of a structure after an epitaxial silicon layer is formed on a supporting wafer in a specific embodiment of the present invention, Figure 4 1 is a schematic diagram of a structure after forming an epitaxial stack layer on a support wafer and removing the support wafer according to a specific embodiment of the present invention. In some embodiments, the thickness of the multiple epitaxial silicon layers 30 in the epitaxial stack layer 40 are the same; or,
[0043] In the epitaxial stack layer 40 , at least two epitaxial silicon layers 30 have different thicknesses.
[0044] In one example, the thickness of all the epitaxial silicon layers 30 in the epitaxial stack layer 40 along the first direction is the same, thereby further simplifying the manufacturing process of the epitaxial stack layer 40 and being able to better control the overall resistivity distribution of the epitaxial stack layer 40 and the overall defect distribution of the epitaxial stack layer 40.
[0045] In another example, there are at least two epitaxial silicon layers 30 in the epitaxial stack layer 40 with different thicknesses. For example, in the direction along the support wafer 20 pointing to the epitaxial stack layer 40, the thickness of the epitaxial silicon layer 30 gradually decreases, thereby improving the efficiency of forming the epitaxial stack layer 40.
[0046] In some embodiments, the specific steps of forming the epitaxial stack layer 40 on the first surface 201 of the support wafer 20 include:
[0047] Obtaining the number of the epitaxial silicon layer 30 in the epitaxial stack layer 40 according to the preset thickness of the epitaxial stack layer 40 as the preset number of layers;
[0048] The epitaxial silicon layers 30 having the preset number of layers are formed one by one by adopting multiple epitaxial growth processes.
[0049] For example, the number of epitaxial silicon layers 30 in the epitaxial stacked layer 40 is calculated according to the preset thickness of the epitaxial stacked layer 40 to be formed and the thickness of a single epitaxial silicon layer 30 that can be grown and formed by a single epitaxial growth process in theory, and the calculated number of layers is used as the preset number of epitaxial silicon layers 30 to be grown epitaxially, and the preset number of epitaxial silicon layers 30 are formed one by one through multiple epitaxial growth processes, that is, each epitaxial growth process forms and only forms one layer of epitaxial silicon layer 30. By adopting the above method, not only the number of executions of the epitaxial process can be accurately controlled, thereby accurately controlling the total thickness of the epitaxial stacked layer 40, but also the parameters of each epitaxial process (such as epitaxial temperature, epitaxial pressure, epitaxial time, reactant dosage, etc.) can be better adjusted according to the number of epitaxial processes to be implemented, thereby better controlling the quality of each epitaxial silicon layer 30, and thus better improving the quality of the silicon wafer finally formed.
[0050] In some embodiments, the specific steps of obtaining the number of the epitaxial silicon layer 30 in the epitaxial stack layer 40 according to the preset thickness of the epitaxial stack layer 40 include:
[0051] The number of layers n of the epitaxial silicon layer 30 in the epitaxial stack layer 40 is calculated using the following formula:
[0052] n=(T+R) / D
[0053] Wherein, T is the preset thickness of the epitaxial stack layer 40, D is the thickness of a single epitaxial silicon layer 30 grown by the epitaxial growth process, and R is a fixed compensation thickness.
[0054] For example, the number of layers n of the epitaxial silicon layer 30 in the epitaxial stack layer 40 is calculated by using the formula n=(T+R) / D, and the thickness of the epitaxial silicon layer 30 lost in the subsequent trimming process of a single epitaxial silicon layer 30 and / or the trimming process of the epitaxial stack layer 40 as a whole can be compensated by adding a fixed value compensation thickness R, thereby ensuring the thickness of the silicon wafer suitable for high-voltage devices formed in the end. In one example, R is 10 μm.
[0055] In order to further improve the morphology of the silicon wafer while precisely controlling the thickness of the silicon wafer, in some embodiments, the specific steps of forming the epitaxial stacking layer 40 on the first surface 201 of the support wafer 20 and removing the support wafer 20 include:
[0056] The following cycle steps are performed multiple times until the preset number of epitaxial silicon layers 30 are formed and at least the support wafer 20 is completely removed, and the cycle steps include:
[0057] A layer of the epitaxial silicon layer 30 is formed above the first surface 201 of the supporting wafer 20 by using a primary epitaxial growth process;
[0058] Part of the support wafer 20 is removed.
[0059] In some embodiments, the thickness of the support wafer 20 removed in each of the cycle steps is the same as the thickness of the formed epitaxial silicon layer 30 .
[0060] In some embodiments, after the epitaxial stacking layer 40 is formed on the first surface 201 of the supporting wafer 20 and the supporting wafer 20 is removed, the following steps are further included:
[0061] Part of the epitaxial stack layer 40 is removed to adjust the thickness of the epitaxial stack layer 40 .
[0062] For example, the first cycle step is performed: a layer of the epitaxial silicon layer 30 covering the first surface 201 of the support wafer 20 is formed by a single epitaxial growth process, such as Figure 3 As shown; the back side of the support wafer 20 (i.e., the second surface 202 of the support wafer 20) is trimmed by means of grinding, chamfering, and grinding to remove part of the thickness of the support wafer 20 (for example, remove the support wafer 20 having the same thickness as the epitaxial silicon layer 30 grown in this cycle step). Then, the second cycle step is performed: an epitaxial growth process is used to form another epitaxial silicon layer 30 covering the surface of the epitaxial silicon layer 30 formed in the first cycle step; the back side of the remaining support wafer 20 (i.e., the surface of the support wafer 20 facing away from the epitaxial silicon layer 30) is trimmed by means of grinding, chamfering, and grinding to remove part of the thickness of the support wafer 20 again (for example, remove the support wafer 20 having the same thickness as the epitaxial silicon layer 30 grown in this cycle step). This process is repeated until n cycles are performed to form the epitaxial stacking layer 40 including n layers of the epitaxial silicon layer 30, and all the support wafers 20 are removed, to obtain the following. Figure 4Afterwards, the epitaxial stack layer 40 is subjected to a trimming treatment (e.g., chamfering, grinding, and polishing) to adjust the overall thickness of the epitaxial stack layer 40 (e.g., the overall thickness of the epitaxial stack layer 40 along the first direction) and the overall morphology of the epitaxial stack layer 40 (e.g., the edge shape of the epitaxial stack layer 40 and the flatness of the surface of the epitaxial stack layer 40), so as to further improve the quality of the epitaxial stack layer 40, for example, reduce defects such as burrs on the surface of the epitaxial stack layer 40, improve the flatness of the surface of the epitaxial stack layer 40, and obtain the silicon wafer of the preset thickness.
[0063] Figure 5 2 is another structural schematic diagram of a specific embodiment of the present invention after forming an epitaxial stacking layer on a supporting wafer. In other embodiments, the specific steps of forming the epitaxial stacking layer 40 on the first surface 201 of the supporting wafer 20 and removing the supporting wafer 40 include:
[0064] Multiple epitaxial growth processes are used to form multiple epitaxial silicon layers 30 one by one, and all of the epitaxial silicon layers 30 are used together as the epitaxial stacking layer 40. Figure 5 As shown;
[0065] Remove the support wafer 20 below the epitaxial stack layer 40, such as Figure 4 shown.
[0066] Specifically, the number of epitaxial silicon layers 30 in the epitaxial stacked layer 40 is obtained according to the preset thickness of the epitaxial stacked layer 40 as the preset number of layers, and the preset number of epitaxial silicon layers 30 are formed one by one by using multiple epitaxial growth processes, and the preset number of epitaxial silicon layers 30 are used as the epitaxial stacked layer 40 as a whole. Figure 5 As shown. After the epitaxial stack layer 40 is formed, the entire support wafer 20 is removed by grinding, chamfering and polishing, and the remaining epitaxial stack layer 40 is used as a silicon wafer to further improve the manufacturing efficiency of the silicon wafer. In one example, while removing the support wafer 20, part of the epitaxial stack layer 40 can also be removed to adjust the overall thickness of the epitaxial stack layer 40, thereby obtaining the silicon wafer of the preset thickness.
[0067] This specific embodiment also provides a silicon wafer suitable for high voltage devices. The structural schematic diagram of the silicon wafer suitable for high voltage devices provided in this specific embodiment can be found in Figure 5 The silicon wafer suitable for high voltage devices can be made of Figure 1-Figure 5 The method for manufacturing a silicon wafer suitable for high voltage devices is shown in FIG. Figure 1-Figure 5 As shown, the silicon wafer suitable for high voltage devices comprises:
[0068] The epitaxial stack layer 40 includes a plurality of epitaxial silicon layers 30 stacked in sequence, wherein the plurality of epitaxial silicon layers 30 are grown in sequence through multiple epitaxial growth processes.
[0069] In some embodiments, the thicknesses of the plurality of epitaxial silicon layers 30 in the epitaxial stack layer 40 are all the same; or,
[0070] In the epitaxial stack layer 40 , at least two epitaxial silicon layers 30 have different thicknesses.
[0071] The silicon wafer and manufacturing method thereof suitable for high-voltage devices provided in this specific embodiment form an epitaxial stacking layer on the first surface of a supporting wafer, wherein the epitaxial stacking layer includes a plurality of epitaxial silicon layers stacked in sequence along the first direction, wherein the plurality of epitaxial silicon layers are grown in sequence through multiple epitaxial growth processes, and after removing the supporting wafer, only the epitaxial stacking layer is used as the silicon wafer. Since the epitaxial silicon layer grown by the epitaxial growth process has good resistivity uniformity, not only has fewer defects, but also has the characteristics of high resistance and low oxygen content, the resistivity uniformity of the silicon wafer as a whole can be improved, and the defects inside the silicon wafer can be reduced, thereby improving the performance of the high-voltage device manufactured by the silicon wafer. This specific embodiment forms the epitaxial stacking layer through multiple epitaxial growth processes, thereby being able to better adjust the quality and thickness of each epitaxial silicon layer, thereby better adjusting the thickness and quality of the entire epitaxial stacking layer, so as to further improve the quality of the silicon wafer, and further improve the resistivity consistency of the silicon wafer.
[0072] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for manufacturing a silicon wafer suitable for high voltage devices, characterized in that: The steps include: Providing a support wafer, the support wafer comprising a first surface and a second surface that are oppositely distributed along a first direction; An epitaxial stacking layer is formed on the first surface of the supporting wafer, and the supporting wafer is removed. The epitaxial stacking layer includes a plurality of epitaxial silicon layers stacked in sequence along the first direction. The plurality of epitaxial silicon layers are grown in sequence through multiple epitaxial growth processes, and the epitaxial stacking layer is used as a silicon wafer.
2. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 1, characterized in that: The thicknesses of the plurality of epitaxial silicon layers in the epitaxial stack layer are all the same; or, At least two epitaxial silicon layers in the epitaxial stack layer have different thicknesses.
3. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 1, characterized in that: The specific steps of forming an epitaxial stack layer on the first surface of the supporting wafer include: Acquire the number of the epitaxial silicon layers in the epitaxial stack layer according to the preset thickness of the epitaxial stack layer as the preset number of layers; The preset number of epitaxial silicon layers is formed one by one by adopting multiple epitaxial growth processes.
4. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 3, characterized in that: The specific step of obtaining the number of epitaxial silicon layers in the epitaxial stack layer according to the preset thickness of the epitaxial stack layer comprises: The number of layers n of the epitaxial silicon layer in the epitaxial stack layer is calculated using the following formula: n=(T+R) / D Wherein, T is the preset thickness of the epitaxial stack layer, D is the thickness of a single epitaxial silicon layer grown by the epitaxial growth process, and R is a fixed compensation thickness.
5. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 4, characterized in that: The specific steps of forming an epitaxial stacking layer on the first surface of the supporting wafer and removing the supporting wafer include: The following cycle steps are performed multiple times until the preset number of epitaxial silicon layers are formed and at least the support wafer is completely removed, the cycle steps comprising: Using a primary epitaxial growth process to form a layer of the epitaxial silicon layer located above the first surface of the supporting wafer; A portion of the support wafer is removed.
6. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 5, characterized in that: The thickness of the support wafer removed in each of the cycle steps is the same as the thickness of the formed epitaxial silicon layer.
7. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 1, characterized in that: The specific steps of forming an epitaxial stacking layer on the first surface of the supporting wafer and removing the supporting wafer include: Using multiple epitaxial growth processes to form a plurality of epitaxial silicon layers one by one, and using all of the epitaxial silicon layers together as the epitaxial stacking layer; The support wafer below the epitaxial stack layer is removed.
8. The method for manufacturing a silicon wafer suitable for high voltage devices according to claim 1, characterized in that: After forming an epitaxial stacking layer on the first surface of the supporting wafer and removing the supporting wafer, the method further includes the following steps: Part of the epitaxial stack layer is removed to adjust the thickness of the epitaxial stack layer.
9. A silicon wafer suitable for high voltage devices, characterized in that: include: The epitaxial stack layer comprises a plurality of epitaxial silicon layers stacked in sequence, wherein the plurality of epitaxial silicon layers are grown in sequence through multiple epitaxial growth processes.
10. The silicon wafer suitable for high voltage devices according to claim 9, characterized in that: The thicknesses of the plurality of epitaxial silicon layers in the epitaxial stack layer are all the same; or, At least two epitaxial silicon layers in the epitaxial stack layer have different thicknesses.