Shift register control method, control circuit and electronic equipment

Abstract

The invention relates to the technical field of circuit control, and discloses a shifting register control method, a shifting register control circuit and electronic equipment, the shifting register control method is applied to the shifting register control circuit, and the shifting register control circuit comprises a controller integrated with a direct access control unit, an SPI communication module and a shifting register. The controller is electrically connected with the SPI communication module, and the SPI communication module is electrically connected with the shift register; the control method comprises the following steps: the controller outputs a control signal to the SPI communication module through the direct access control unit; and the SPI communication module performs output control on the shift register by using the control signal based on an SPI master station mode, so that the output capability of the circuit is enhanced, the burden of a controller is reduced, and the overall performance and efficiency of the system are improved.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to a shift register control method, a control circuit and an electronic device. Background Art

[0002] With the development of science and technology, electronic products are becoming more and more intelligent, and the control systems in electronic products are becoming more and more complex. In order to make the controller meet the input and output pins required by the system, the prior art uses shift registers to perform serial-to-parallel or parallel-to-serial processing of data, wherein the shift register data input pins, clock input pins, etc. require the controller to control the corresponding signals according to the logic output. When the controller resources are relatively tight, this continuous intervention will lead to waste of resources and affect the performance and efficiency of the overall system. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a shift register control method, a control circuit and an electronic device, which can effectively solve the problem in the existing solution that the shift register data input pin, the clock input pin, etc. require the controller to control the corresponding signal according to the logic output, which leads to resource waste when the controller resources are relatively tight, affecting the performance and efficiency of the overall system.

[0004] In a first aspect, an embodiment of the present application provides a shift register control method, which is applied to a shift register control circuit, wherein the shift register control circuit comprises: a controller integrated with a direct access control unit, an SPI communication module, and a shift register, wherein the controller is electrically connected to the SPI communication module, and the SPI communication module is electrically connected to the shift register;

[0005] The control method comprises:

[0006] The controller outputs a control signal to the SPI communication module through the direct access control unit;

[0007] The SPI communication module uses the control signal to perform output control on the shift register based on the SPI master mode.

[0008] In some embodiments, the direct access control unit includes at least one channel connected to a control signal source address, and the controller transmits the control signal to the SPI communication module using the channel.

[0009] In some embodiments, before the SPI communication module uses the control signal to control the output of the shift register based on the SPI master mode, the shift register control method further includes:

[0010] The working mode of the SPI communication module is configured to be a preset mode.

[0011] In some embodiments, the SPI communication module uses the control signal to control the output of the shift register based on the SPI master mode, including:

[0012] The SPI communication module outputs a preset data signal to the shift register in the preset mode;

[0013] The shift register is controlled to latch and output the preset data signal.

[0014] In some embodiments, the SPI communication module outputting a preset data signal to the shift register in the preset mode includes:

[0015] The SPI communication module outputs a low level signal to the storage clock pin of the shift register;

[0016] When the shift clock signal controlling the shift register is at a falling edge, the preset data signal is transmitted to the data input pin of the shift register through the output pin of the master device;

[0017] When the shift clock signal controlling the shift register is at a rising edge, the preset data signal is shifted in sequence.

[0018] In some embodiments, controlling the shift register to latch and output the preset data signal comprises:

[0019] The storage clock pin of the shift register is controlled to be a high level signal so as to latch and output the preset data signal.

[0020] In some embodiments, the controller transmits the control signal to the SPI communication module using the channel, comprising:

[0021] Obtaining the control signal source address;

[0022] Obtain the target address of the SPI communication module;

[0023] The control signal is read from the control signal source address and written into the target address of the SPI communication module.

[0024] In a second aspect, an embodiment of the present application provides a shift register control circuit, which includes: a controller integrated with a direct access control unit, an SPI communication module and a shift register, the controller is electrically connected to the SPI communication module, and the SPI communication module is electrically connected to the shift register.

[0025] In some embodiments, the controller is electrically connected to the SPI communication module via a peripheral bus;

[0026] The master device output pin of the SPI communication module is connected to the data input pin of the shift register, the clock signal pin of the SPI communication module is connected to the shift clock pin of the shift register, and the slave device selection pin of the SPI communication module is connected to the storage clock pin of the shift register.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, comprising at least one shift register control circuit as described in the second aspect above.

[0028] The embodiments of the present application have the following beneficial effects:

[0029] The shift register control circuit of the present application includes a controller integrated with a direct access control unit, an SPI communication module and a shift register, wherein the controller, the SPI communication module and the shift register are connected in sequence, wherein the controller uses its direct access control unit to output a control signal to the SPI communication module, and the SPI communication module, as a master device, uses the control signal to control the shift register to achieve parallel output. The shift register control method of the present application uses the direct access control unit in the controller to transmit the control signal, and does not require the controller to control the corresponding signal according to the logic output, which greatly reduces the burden of the controller, releases the resources of the controller, and improves the overall performance and efficiency of the system; the SPI communication module is used to control the shift register according to the control signal to achieve parallel output, which greatly increases the output capacity of the circuit and expands the output interface of the circuit, and the SPI communication module supports high-speed data transmission, which can quickly transmit data from the controller to the shift register, thereby improving data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A schematic diagram of the structure of a shift register control circuit according to an embodiment of the present application is shown;

[0032] Figure 2 A schematic diagram showing the principle of a shift register control circuit according to an embodiment of the present application is shown;

[0033] Figure 3A first flow chart of a shift register control method according to an embodiment of the present application is shown;

[0034] Figure 4 A second flow chart of the shift register control method according to an embodiment of the present application is shown;

[0035] Figure 5 A third flow chart of the shift register control method according to an embodiment of the present application is shown;

[0036] Figure 6 An operation timing diagram of the SPI communication module according to an embodiment of the present application is shown;

[0037] Figure 7 A fourth flow chart of the shift register control method according to an embodiment of the present application is shown;

[0038] Figure 8 A fifth flow chart of the shift register control method according to an embodiment of the present application is shown.

[0039] Description of main component symbols:

[0040] 11: controller; 12: SPI communication module; 13: shift register; 14: peripheral bus;

[0041] 111: Direct access control unit. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0043] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0044] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0045] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0046] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0047] Taking into account that in the existing scheme, the data input pins, clock input pins, etc. of the shift register need to be controlled by the controller according to the corresponding signals of the logic output, which leads to resource waste when the controller resources are relatively tight, affecting the performance and efficiency of the overall system. The present application provides a shift register control method, a control circuit and an electronic device. The shift register control method of the present application uses the direct access control unit in the controller to transmit the control signal, and does not require the controller to control according to the corresponding signals of the logic output, which greatly reduces the burden of the controller, releases the resources of the controller, and improves the overall performance and efficiency of the system; the SPI communication module is used to control the shift register according to the control signal to achieve parallel output, which greatly increases the output capacity of the circuit and expands the output interface of the circuit. The SPI communication module supports high-speed data transmission, and can quickly transmit data from the controller to the shift register, thereby improving data transmission efficiency.

[0048] The shift register control circuit is described below in conjunction with some specific embodiments.

[0049] In one embodiment, Figure 1A structural schematic diagram of a shift register control circuit of an embodiment of the present application is shown. Exemplarily, the shift register control circuit includes: a controller 11 integrated with a direct access control unit 111, an SPI communication module 12 and a shift register 13, the controller 11 is electrically connected to the SPI communication module 12, and the SPI communication module 12 is electrically connected to the shift register 13.

[0050] It can be understood that the shift register 13 can be any type of shift register. The shift register 13 can be a shift register with a storage register, or a shift register without a storage register. The shift register 13 can also be a shift register with serial output and parallel output. The number of parallel output terminals of the shift register 13 can be set according to actual application conditions. Exemplarily, the shift register 13 has eight parallel output terminals.

[0051] The working process of the shift register control circuit of this embodiment is: when the direct access control unit 111 obtains the request transmission signal of the SPI communication module 12, the control signal of the control signal source address is transmitted to the target address of the SPI communication module 12 by using the channel, and the SPI communication module 12 uses the control signal to control the shift register 13 to achieve parallel output.

[0052] The control signal source address in the controller 11 and the target address of the SPI communication module 12 can be set according to the actual application situation. Only one control signal source address and the target address of the SPI communication module 12 can be set, or multiple control signal source addresses and the target address of the SPI communication module 12 can be set. It can be understood that a channel can be set in the direct access control unit 111, and the control signal can be transmitted by using one channel; multiple channels can also be set in the direct access control unit 111, and the multiple channels are respectively connected to different control signal source addresses and target addresses of the SPI communication module 12.

[0053] It is understandable that the control signal includes the signal for the SPI communication module 12 to control each pin of the shift register 13, and also includes the preset data signal that the shift register 13 needs to output. The control signal can be written to the control signal source address according to the actual application situation. It is understandable that the preset data signal can be any digital signal, the preset data signal can be 0XAA, and the preset data signal can also be 0XFF.

[0054] The shift register control circuit of the present embodiment is provided with a controller 11 integrated with a direct access control unit 111, an SPI communication module 12 and a shift register 13. The output interface of the circuit is expanded by the shift register 13 to meet the system's demand for output pins. When the SPI communication module 12 needs to control the shift register 13, the control signal is transmitted by the direct access control unit 111, and the controller 11 is not required to control the corresponding signal according to the logic output, which greatly reduces the burden of the controller 11, releases the resources of the controller 11, and improves the overall performance and efficiency of the system. In addition, the SPI communication module 12 supports high-speed data transmission and can quickly transmit data from the controller 11 to the shift register 13, thereby improving data transmission efficiency.

[0055] In one embodiment, Figure 2 A schematic diagram of the principle of the shift register control circuit of the embodiment of the present application is shown. On the basis of the above embodiment, the controller 11 is electrically connected to the SPI communication module 12 through the peripheral bus 14. Specifically, the peripheral bus 14 can be a high-performance peripheral bus, the peripheral bus 14 can also be a low-speed peripheral bus, or the peripheral bus 14 can also be a high-performance peripheral bus and a low-speed peripheral bus. Exemplarily, the peripheral bus 14 is a high-performance peripheral bus and a low-speed peripheral bus. When the direct access control unit 111 obtains the request transmission signal of the SPI communication module 12, it is also necessary to obtain the control right of the peripheral bus 14; when the direct access control unit 111 writes the control signal to the target address of the SPI communication module 12, it is also necessary to release the control right of the peripheral bus 14.

[0056] The master device output pin of the SPI communication module 12 is connected to the data input pin of the shift register 13 , the clock signal pin of the SPI communication module 12 is connected to the shift clock pin of the shift register 13 , and the slave device selection pin of the SPI communication module 12 is connected to the storage clock pin of the shift register 13 .

[0057] Specifically, Figure 2 As shown, the master device output pin of the SPI communication module 12 is MOSI, the clock signal pin of the SPI communication module 12 is SCLK, and the slave device selection pin of the SPI communication module 12 is CS; the data input pin of the shift register 13 is DS, the shift clock pin of the shift register 13 is SHCP, and the storage clock pin of the shift register 13 is STCP; Q0-Q7 of the shift register 13 are respectively the parallel output pins of the shift register 13.

[0058] The working process of the shift register control circuit of this embodiment is: the SPI communication module 12 first controls the storage clock pin of the shift register 13 to be a low-level signal, and when the signal of the shift clock pin of the shift register 13 is a falling edge, the preset data signal is transmitted to the data input pin of the shift register 13 through the master device output pin, and the shift clock pin of the shift register 13 is controlled to shift in data in sequence each time when the signal is a rising edge. After the data transmission is completed, the storage clock pin of the shift register 13 is controlled to be a high-level signal, the preset data signal is latched into the storage register, and the preset data signal is controlled to be output.

[0059] It is understandable that before the SPI communication module 12 controls the shift register 13, it is necessary to configure the SPI working mode. Preferably, the SPI working mode is configured as a preset mode, wherein the preset mode is one of the four working modes in the SPI communication mode, specifically: the clock polarity of the SPI communication module 12 is 1, and the clock phase of the SPI communication module 12 is 1.

[0060] The shift register control circuit of this embodiment connects each pin of the SPI communication module 12 with the shift register 13, so that the SPI communication module 12 controls the shift register 13 through each pin to shift and output the preset data. While increasing the output port, it can reduce the number of connections between the controller 11 and the external device, simplify the hardware design, and reduce the cost of the circuit.

[0061] The present application also provides a shift register control method. Figure 3 A flow chart of a shift register control method according to an embodiment of the present application is shown. The shift register control method is applied to the shift register control circuit mentioned in any of the above embodiments. The control method includes:

[0062] Step S101 : the controller 11 outputs a control signal to the SPI communication module 12 via the direct access control unit 111 .

[0063] It is understandable that the control signal can be transmitted using one channel of the direct access control unit 111, or multiple channels. The control signal includes the signal that the SPI communication module 12 controls each pin of the shift register 13, and also includes the preset data signal that the shift register 13 needs to output. The control signal can be written into the control signal source address according to the actual application situation.

[0064] Step S102: the SPI communication module 12 uses a control signal to control the output of the shift register 13 based on the SPI master mode.

[0065] The SPI master mode refers to a mode in which the SPI communication module 12 controls the shift register 13 as a master device. Specifically, the SPI communication module 12 controls the shift register 13 by controlling the pin signals input to the shift register 13 to achieve parallel output.

[0066] In this embodiment, the controller 11 transmits the control signal by directly accessing the control unit 111, which can significantly improve the performance and efficiency of the system, reduce the burden on the controller 11, reduce the delay in data transmission, and improve the reliability of the system; and the SPI communication module 12 controls the shift register 13 using the control signal based on the SPI master station mode to achieve parallel output, thereby increasing the output capacity of the circuit and meeting the system's requirements for output pins.

[0067] In one embodiment, based on the above embodiment, the direct access control unit 111 includes at least one channel connected to the source address of the control signal, and the controller 11 transmits the control signal to the SPI communication module 12 by using the channel.

[0068] The direct access control unit 111 may use only one channel, with both ends of the channel respectively connected to the control signal source address and the target address of the SPI communication module 12 for transmission. The direct access control unit 111 may also use multiple channels, with both ends of the multiple channels respectively connected to different control signal source addresses and the target address of the SPI communication module 12 for transmission.

[0069] In this embodiment, the control signal transmission is performed by directly accessing the channel of the control unit 111, and the controller 11 does not need to intervene, thereby achieving high-speed transmission.

[0070] In one embodiment, Figure 4 Another flow chart of the shift register control method according to an embodiment of the present application is shown. Based on the above embodiment, before step S102, the shift register control method further includes:

[0071] Step S201: configuring the working mode of the SPI communication module 12 to be a preset mode.

[0072] It can be understood that the working mode of the SPI communication module 12 can be configured according to the actual application situation. Specifically, the SPI communication module 12 has four working modes: Mode 1: the clock polarity is 0, the clock phase is 0, that is, the clock is at a low level when it is idle, and data is captured on the first edge; Mode 1: the clock polarity is 0, the clock phase is 1, that is, the clock is at a low level when it is idle, and data is captured on the second edge; Mode 2: the clock polarity is 1, the clock phase is 0, that is, the clock is at a high level when it is idle, and data is captured on the first edge; Mode 3: the clock polarity is 1, the clock phase is 1, that is, the clock is at a high level when it is idle, and data is captured on the second edge; wherein the first edge is the first edge of the clock signal pin signal, which is a rising edge, and the second edge is the second edge of the clock signal pin signal, which is a falling edge. By way of example, the preset mode is Mode 3.

[0073] In this embodiment, before the SPI communication module 12 controls the shift register 13, the SPI working mode is configured to ensure that the control signal will not have errors during the transmission process, guarantee the signal integrity, and ensure the speed and reliability of signal transmission.

[0074] In one embodiment, Figure 5 Another schematic flow chart of the shift register control method according to an embodiment of the present application is shown. Based on the above embodiment, step S102 includes:

[0075] Step S301 : the SPI communication module 12 outputs a preset data signal to the shift register 13 in a preset mode.

[0076] The SPI communication module 12 transmits the preset data signal to the shift register 13 through the data input pin of the shift register 13 by controlling the signal of the shift clock pin and the storage clock pin input to the shift register 13 according to the configured working mode.

[0077] The preset data signal is a parallel output signal of the shift register 13. The preset data signal may be any digital signal. The preset data signal may be 0XAA or 0XFF.

[0078] Step S302: Control the shift register 13 to latch and output the preset data signal.

[0079] The SPI communication module 12 latches the preset data signal into the storage register and outputs it by controlling the signal input to the storage clock pin of the shift register 13 .

[0080] Specifically, latching refers to copying the preset data in the shift register 13 to the output register.

[0081] In this embodiment, the SPI communication module 12 controls the shift register 13 to output data according to the working mode. The correct working mode can ensure that the preset data signal is correctly sampled during the transmission process to ensure the integrity of the data. The SPI communication module 12 can also achieve efficient data transmission and meet high bandwidth requirements.

[0082] As an optional solution, Figure 6 The following is an operation timing diagram of an SPI communication module. Figure 7 FIG. 4 is another flow chart of a shift register control method.

[0083] In one embodiment, if Figure 6 and Figure 7 As shown, based on the above embodiment, step S301 includes:

[0084] Step S401: the SPI communication module 12 outputs a low level signal to the storage clock pin of the shift register.

[0085] Specifically, mode 3 has a clock polarity of 1 and a clock phase of 1, that is, the clock is at a high level when idle, and data is captured on the second edge; the first edge is the first edge of the clock signal pin signal, which is a rising edge, and the second edge is the second edge of the clock signal pin signal, which is a falling edge.

[0086] The SPI communication module 12 controls the storage clock pin of the shift register 13 to be a low level signal, so that the shift register 13 can latch the data.

[0087] Step S402: when the shift clock signal controlling the shift register 13 is at a falling edge, the preset data signal is transmitted to the data input pin of the shift register 13 through the output pin of the master device.

[0088] It is understandable that the SPI communication module 12 transmits the preset data signal to the data input pin of the shift register 13 through the master device output pin at the first falling edge of the shift clock pin. Since the SPI communication module 12 operates in mode 3, it is sampled at the falling edge of the shift clock pin.

[0089] Step S403: When the shift clock signal of the shift register 13 is at a rising edge, the preset data signal is shifted in sequence. For example, Figure 6 As shown, the preset data signal is 0X55, that is, 01010101.

[0090] In this embodiment, by controlling the transmission of the preset data signal by controlling the clock signal, it is possible to ensure that the data is accurately synchronized with the clock signal during the transmission process, thereby avoiding data transmission errors.

[0091] In one embodiment, if Figure 6 and Figure 7 As shown, based on the above embodiment, step S302 includes:

[0092] Step S404: The preset data signal is latched and outputted by controlling the storage clock pin of the shift register 13 to be a high level signal.

[0093] Specifically, the output of the preset data may be controlled by controlling the storage clock pin of the shift register 13 , or the output of the preset data signal may be controlled by controlling the dedicated data output pin of the shift register 13 .

[0094] In this embodiment, it can be ensured that the data is latched into the storage register after the data is completely shifted in the shift register 13. This avoids partial latching of data during the shifting process, thereby ensuring the integrity and accuracy of the data, while avoiding data conflicts and improving the reliability of the system.

[0095] In one embodiment, Figure 8 Another flow chart of the shift register control method according to an embodiment of the present application is shown. Based on the above embodiment, step S101 includes:

[0096] Step S501: Acquire the control signal source address.

[0097] Specifically, a section of memory in the controller 11 is set as the control signal source address, and the direct access control unit 111 is configured with a register so that the direct access control unit 111 obtains the control signal source address.

[0098] Step S502: Obtain the target address of the SPI communication module 12.

[0099] Specifically, a section of memory in the SPI communication module 12 is set as the target address, and the register of the direct access control unit 111 is configured so that the direct access control unit 111 obtains the target address.

[0100] Step S503 : reading the control signal from the control signal source address and writing it into the target address of the SPI communication module 12 .

[0101] The direct access control unit 111 reads the control signal from the source address and transmits it via the peripheral bus 14 .

[0102] In this embodiment, the direct access control unit 111 transmits control signals through source addresses and target addresses, so that relevant personnel only need to set the source address and target address of the control signal and write the control signal to the source address. The direct access control unit 111 can automatically complete the movement of the signal, reducing the complexity of programming.

[0103] An embodiment of the present application further provides an electronic device. Exemplarily, the electronic device includes the above-mentioned shift register control circuit.

[0104] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0105] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0106] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0107] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A shift register control method, characterized in that: Applied to a shift register control circuit, the shift register control circuit comprises: a controller integrated with a direct access control unit, an SPI communication module and a shift register, the controller is electrically connected to the SPI communication module, and the SPI communication module is electrically connected to the shift register; the control method comprises: The controller outputs a control signal to the SPI communication module through the direct access control unit; The SPI communication module uses the control signal to perform output control on the shift register based on the SPI master mode.

2. The shift register control method according to claim 1, characterized in that: The direct access control unit includes at least one channel connected to a control signal source address, and the controller transmits the control signal to the SPI communication module using the channel.

3. The shift register control method according to claim 1, characterized in that: Before the SPI communication module uses the control signal to control the output of the shift register based on the SPI master mode, the shift register control method further includes: The working mode of the SPI communication module is configured to be a preset mode.

4. The shift register control method according to claim 3, characterized in that: The SPI communication module uses the control signal to control the output of the shift register based on the SPI master mode, including: The SPI communication module outputs a preset data signal to the shift register in the preset mode; The shift register is controlled to latch and output the preset data signal.

5. The shift register control method according to claim 4, characterized in that: The SPI communication module outputs a preset data signal to the shift register in the preset mode, comprising: The SPI communication module outputs a low level signal to the storage clock pin of the shift register; When the shift clock signal controlling the shift register is at a falling edge, the preset data signal is transmitted to the data input pin of the shift register through the output pin of the master device; When controlling the rising edge of the shift clock signal of the shift register, the preset data signal is shifted in sequence.

6. The shift register control method according to claim 4, characterized in that: The controlling the shift register to latch and output the preset data signal comprises: The storage clock pin of the shift register is controlled to be a high level signal to latch and output the preset data signal.

7. The shift register control method according to claim 2, characterized in that: The controller uses the channel to transmit the control signal to the SPI communication module, comprising: Obtaining the control signal source address; Obtain the target address of the SPI communication module; The control signal is read from the control signal source address and written into the target address of the SPI communication module.

8. A shift register control circuit, characterized in that: The shift register control circuit comprises: a controller integrated with a direct access control unit, an SPI communication module and a shift register, wherein the controller is electrically connected to the SPI communication module, and the SPI communication module is electrically connected to the shift register.

9. The shift register control circuit according to claim 8, characterized in that: The controller is electrically connected to the SPI communication module via a peripheral bus; The master device output pin of the SPI communication module is connected to the data input pin of the shift register, the clock signal pin of the SPI communication module is connected to the shift clock pin of the shift register, and the slave device selection pin of the SPI communication module is connected to the storage clock pin of the shift register.

10. An electronic device, characterized in that: The electronic device comprises the shift register control circuit as described in any one of claims 8-9.

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