Method and system for realizing quick inversion of El matrix based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a method and a system for realizing quick inversion of an El-Mit matrix based on an FPGA, and the method comprises the steps: carrying out the LDL decomposition of an n-order El-Mit matrix based on the positive definite symmetry of the El-Mit matrix, and obtaining a lower triangular matrix and a diagonal matrix; s2, utilizing an inversion module for lower triangular matrix inversion and an inversion module for diagonal matrix inversion to respectively and simultaneously perform block inversion and diagonal matrix inversion on the lower triangular matrix; and S3, obtaining an inverse matrix through matrix multiplication by using a matrix multiplication module. According to the scheme, the lower triangular matrix and the diagonal matrix are decomposed by utilizing the positive qualitative property of the El matrix, the calculation in the decomposition process is simpler, the number of iterations is smaller, and the calculation amount and the data storage amount in the calculation process are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of array signal processing, and in particular to a method and system for realizing fast inversion of Hermitian matrix based on FPGA. Background Art

[0002] Matrix inversion operations are widely used in array signal processing. The beam pointing and interference suppression in the array space domain both involve the inversion of the spatial correlation matrix. In practical engineering applications, the correlation matrix of the array is estimated by time averaging the observed data vector obtained by a finite number of snapshots. Taking advantage of the fact that it is a positive Hermitian array, a method is proposed to use the conjugate symmetry of the Hermitian array to perform LDL decomposition on the correlation matrix and then perform block inversion. This method has low computational complexity, small storage requirements, and is easy to implement in FPGA engineering, which brings great convenience to the engineering implementation of array signal processing. Summary of the invention

[0003] Based on the above technical problems, the present invention proposes a method and system for fast inversion of Hermitian matrix based on FPGA, and the specific technical solution is as follows.

[0004] In a first aspect, a method for fast inversion of a Hermitian matrix based on an FPGA comprises the following steps:

[0005] Step S1: Based on the positive definite symmetry of the Hermitian matrix, perform LDL decomposition on the n-order Hermitian matrix to obtain a lower triangular matrix L and a diagonal matrix D;

[0006] Step S2: using the L inversion module for inverting the lower triangular matrix and the D inversion module for inverting the diagonal matrix, respectively and simultaneously performing block inversion on the lower triangular matrix L and inversion on the diagonal matrix D;

[0007] Step S3: Utilize the matrix multiplication module to obtain the inverse matrix through matrix multiplication.

[0008] Specifically, the LDL decomposition of the n-order Hermitian matrix includes the following sub-steps:

[0009] Step S11: Calculate the kth element of the diagonal matrix D;

[0010] Step S12: Calculate the j-th row and k-th column element of the intermediate matrix U;

[0011] Step S13: Calculate the j-th row and k-th column element of the lower triangular matrix L;

[0012] Step S14: Repeat steps S11 to S13 according to the number of rows and columns of the matrix until all valid elements of the lower triangular matrix L and the diagonal matrix D are obtained; the calculation formulas for each part are:

[0013]

[0014] l jk =u jk / d k .

[0015] Specifically, the step S2 of inverting the lower triangular matrix L is as follows: firstly divide the lower triangular matrix L into blocks to reduce the order of the matrix, and then invert the low-order matrix after the block division, and the expression is:

[0016]

[0017] Specifically, the step S2 seeks the inverse of the diagonal matrix D by seeking the inverse of the diagonal elements of the matrix, and the expression is:

[0018]

[0019] Specifically, the matrix multiplication in step S3 is to perform matrix multiplication on the inverse calculation results of the lower triangular matrix L and the inverse calculation results of the diagonal matrix D to obtain the inverse matrix A -1 , the expression is:

[0020] A -1 =(L -1 ) H *D -1 *L -1 .

[0021] On the other hand, a system for implementing fast inversion of Hermitian matrix based on FPGA, used to implement the method for implementing fast inversion of Hermitian matrix based on FPGA, comprising:

[0022] LDL decomposition module: The Hermitian matrix A enters the LDL decomposition module and is iteratively decomposed;

[0023] L inversion module: inverse the lower triangular matrix L after LDL decomposition is completed;

[0024] D inversion module: inverts the diagonal matrix D after LDL decomposition, inputs the diagonal elements of the diagonal matrix, and inverts all elements in parallel;

[0025] Matrix multiplication module: receives the inverse matrix of the lower triangular matrix L and the diagonal matrix D, first transforms L -1 Perform conjugate transpose and D -1 Perform matrix multiplication to obtain the intermediate matrix LD, and finally the intermediate matrix LD is added to L -1 Perform matrix multiplication to obtain the inverse matrix A -1 .

[0026] Specifically, the state transformation of the LDL decomposition module during decomposition is as follows:

[0027] The module is in the IDLE state. When there is data to be processed, it enters the state Loop0. In the Loop0 state, counter 0 starts working, and the count value k ranges from 1 to n. After counter 0 is valid, it jumps to Loop1, counter 1 starts working, and the count value m ranges from 1 to k-1. At the same time, it starts calculating at each count value of counter 1. After counter 1 finishes counting, it jumps to Sub0 and starts counting d k =a kk -sum1;

[0028] After Sub0 calculation is completed, it jumps to Loop2 state, counter 2 starts working, and the count value j ranges from k+1 to n. After the count value j is valid, it jumps to Loop3 state, counter 3 starts working, and the count value m ranges from 1 to k-1. At the same time, it starts calculating at each count value of counter 3

[0029] After counting 3, jump to Sub1 state and start counting u jk =a jk -sum2 and l jk =u jk / d k After Sub1 is finished calculating, it jumps to Loop2 again, and the calculated value of Counter 2 is increased by 1, and it jumps to Loop3 and Sub1 again in sequence until Counter 2 finishes counting;

[0030] When Loop2 counts up, it jumps to Loop0 and repeats the above process until Counter 0 ends, and finally returns to the IDLE state, and the decomposition is completed.

[0031] Specifically, the state transformation of the L inversion module is as follows:

[0032] Jump from IDLE state to Loop0 state, the counting range of counter 0 count value i is 1 to n; after the count value of counter 0 is valid, the state machine jumps to Recip0 state and starts counting

[0033] After the calculation is completed, it jumps to the Loop1 state. The counting range of the count value j of counter 1 is 1 to i-1. After the count value j is valid, it jumps to the Loop2 state. The counting range of the count value k of counter 2 is j to i-1. When the count value k is valid, it is calculated.

[0034] After counting is completed, jump to state Mult0 and then calculate r ij=-invl*sum3, after the calculation is completed, jump to Loop1, then jump to Loop2 and Mult0 in turn until the count value j reaches the end value and then return to Loop0;

[0035] Repeat the above steps until the count value i of counter 0 reaches the end value, return to state IDLE, and the inversion of the L matrix is ​​completed.

[0036] Beneficial effects of the present invention: The present invention proposes a method and system for fast inversion of Hermitian matrices based on FPGA, and utilizes the conjugate symmetry of the Hermitian array to implement a method for inverting the correlation matrix in blocks after LDL decomposition. The method has small computational complexity and storage volume, is easy to implement in FPGA engineering, and brings great convenience to the engineering implementation of array signal processing; by utilizing the structural characteristics of the lower triangular matrix and the diagonal matrix, the problems of complex calculation and large storage volume in the process of ordinary matrix inversion methods are solved, and the positive definiteness of the Hermitian matrix is ​​used to decompose it into the lower triangular matrix and the diagonal matrix. Compared with other decomposition methods such as QR decomposition, the decomposition process is simpler to calculate and the number of iterations is less. The method of sampling and inverting the lower triangular matrix in blocks can greatly reduce the amount of calculation and the amount of data storage in the calculation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a system architecture diagram of the present invention for realizing fast inversion of Hermitian matrix based on FPGA;

[0038] Figure 2 is a state transition diagram of LDL decomposition in an embodiment of the present invention;

[0039] Figure 3 is a state jump diagram of L inversion in an embodiment of the present invention;

[0040] Figure 4 is a processing block diagram of a D inversion module in an embodiment of the present invention;

[0041] Figure 5 is a processing block diagram of a matrix multiplication module in an embodiment of the present invention;

[0042] Figure 6 Schematic diagram of block inversion of the lower triangular matrix in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described with reference to the accompanying drawings.

[0044] The present invention proposes a method and system for fast inversion of Hermitian matrix based on FPGA. According to the positive definite symmetry of Hermitian matrix, the n-order Hermitian matrix is ​​decomposed by LDL to obtain a lower triangular matrix and a diagonal matrix. The specific expression is as follows

[0045]

[0046] Among them, the matrix L is a lower triangular matrix, and the diagonal elements are all 1, L and LH are conjugate transposes of each other, and the matrix D is a diagonal matrix. Then the lower triangular matrix is ​​inverted in blocks and inverted in diagonal matrices at the same time, and finally the inverse matrix is ​​obtained by matrix multiplication. The specific calculation formula is:

[0047] A -1 =(L -1 ) H *D -1 *L -1 .

[0048] By utilizing the structural characteristics of lower triangular matrices and diagonal matrices, the problems of complex calculations and large storage volume in the process of ordinary matrix inversion methods are solved.

[0049] The purpose of the present invention is achieved through the following technical solutions:

[0050] The present invention is used for FPGA engineering implementation of Hermitian matrix inversion, and is mainly composed of four functional modules, namely, an LDL decomposition module for decomposing the Hermitian matrix, an L inversion module for inverting the lower triangular matrix, a D inversion module for inverting the diagonal matrix, and a matrix multiplication module.

[0051] The LDL decomposition module is calculated according to the following formula:

[0052]

[0053] l jk =u jk / d k

[0054] The process specifically includes the following steps:

[0055] (a) Calculate the kth element of the diagonal matrix D;

[0056] (b) Calculate the j-th row and k-th column element of the intermediate matrix U;

[0057] (c) Calculate the j-th row and k-th column element of the lower triangular matrix L;

[0058] (d) Repeat the above steps according to the number of rows and columns of the matrix until all valid elements of the matrices L and D are obtained.

[0059] The L inversion module divides the L lower triangular matrix into blocks first to reduce the order of the matrix, and inverts the low-order matrix after the block division, which can effectively reduce the number of iterations.

[0060] The block inversion method of the lower triangular matrix is ​​as follows Figure 6 As shown, C is an n1-order square matrix, B is an n2-order square matrix, A is a matrix with n2 rows and n1 columns, and n = n1 + n2. First, invert the matrix B and the matrix C, and then calculate -B -1 AC -1 , we can get the inverse matrix L -1 The expression for the inversion of the lower triangular matrix is ​​as follows:

[0061]

[0062] In the D inversion module, since the matrix D is a diagonal matrix, the inverse matrix of the matrix D is to find the inverse of the diagonal elements of the matrix. The specific expression is as follows

[0063]

[0064] The matrix multiplication module performs matrix multiplication on the calculation results of the previous L inversion module and D inversion module to obtain the inverse matrix A -1 The specific expression is as follows

[0065] A -1 =(L -1 ) H *D -1 *L -1 .

[0066] In this embodiment, the Hermitian matrix A enters the LDL decomposition module, and its specific processing can be described by a state machine. Figure 2 ; It can be seen from the LDL decomposition formula that there is a loop iteration process in the decomposition process. In the FPGA implementation, a counter can be used as a loop flag, which is reflected in the state machine as Loop0, Loop1, Loop2, and Loop3 states.

[0067] First, the module is in the IDLE state, and when there is data to be processed, it enters the Loop0 state;

[0068] In the state of Loop0, counter 0 starts working, and the count value k ranges from 1 to n; after counter 0 is valid, it jumps to Loop1, counter 1 starts working, and the count value m ranges from 1 to k-1. At the same time, it starts counting at each count value of counter 1. After counter 1 finishes counting, it jumps to Sub0 and starts counting d k =a kk-sum1. After Sub0 is calculated, it jumps to Loop2 state, counter 2 starts working, and the count value j ranges from k+1 to n. After the count value j is valid, it jumps to Loop3 state, counter 3 starts working, and the count value m ranges from 1 to k-1. At the same time, it starts calculating at each count value of counter 3.

[0069] After counting 3, jump to Sub1 state and start counting u jk =a jk -sum2 and l jk =u jk / d k After Sub1 is calculated, it jumps to Loop2 again, and the calculated value of Counter 2 is increased by 1. It repeats and jumps to Loop3 and Sub1 in sequence until Counter 2 finishes counting. After Loop2 finishes counting, it jumps to Loop0 and repeats the above process in sequence until Counter 0 ends. Finally, it returns to the IDLE idle state and the decomposition is completed.

[0070] After the LDL decomposition is completed, the L matrix enters the L inversion module, and the state machine jumps during the processing process as follows Figure 3 As shown. The state machine jumps from the IDLE state to the Loop0 state, and the count value i of counter 0 has a count range of 1 to n. After the count value of counter 0 is valid, the state machine jumps to the Recip0 state and starts calculating. After the calculation is completed, it jumps to the Loop1 state. The counting range of the count value j of counter 1 is 1 to i-1. After the count value j is valid, it jumps to the Loop2 state. The counting range of the count value k of counter 2 is j to i-1. When the count value k is valid, it is calculated. After counting is completed, jump to state Mult0 and then calculate r ij =-invl*sum3, after the calculation is completed, jump to Loop1, jump to Loop2, Mult0 loop in turn until the count value j reaches the end value and then return to Loop0. Repeat the above steps until the count value i of counter 0 reaches the end value, return to state IDLE, and the inversion of L matrix is ​​completed.

[0071] D Inverse module, since the input is the diagonal elements of the diagonal matrix, only the inversion operation needs to be performed. In order to make full use of the parallel characteristics of F PGA, this module directly inverts all elements in parallel to improve efficiency. The processing structure is shown in Figure 4 .

[0072] The matrix multiplication module receives the inverse matrices of L and D and first transforms L -1 Perform conjugate transpose and D -1 Perform matrix multiplication to obtain the intermediate matrix LD, and finally the intermediate matrix LD is added to L -1 Perform matrix multiplication to obtain the inverse matrix A-1 .

[0073] The present invention has shown and described the basic principles and main features of the present invention and the advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for fast inversion of Hermitian matrix based on FPGA, characterized in that: The following steps are involved: Step S1: Based on the positive definite symmetry of the Hermitian matrix, perform LDL decomposition on the n-order Hermitian matrix to obtain a lower triangular matrix L and a diagonal matrix D; Step S2: using the L inversion module for inverting the lower triangular matrix and the D inversion module for inverting the diagonal matrix, respectively and simultaneously performing block inversion on the lower triangular matrix L and inversion on the diagonal matrix D; Step S3: Utilize the matrix multiplication module to obtain the inverse matrix through matrix multiplication.

2. The method for fast inversion of Hermitian matrix based on FPGA according to claim 1, characterized in that: The LDL decomposition of the n-order Hermitian matrix comprises the following sub-steps: Step S11: Calculate the kth element of the diagonal matrix D; Step S12: Calculate the j-th row and k-th column element of the intermediate matrix U; Step S13: Calculate the j-th row and k-th column element of the lower triangular matrix L; Step S14: Repeat steps S11 to S13 according to the number of rows and columns of the matrix until all valid elements of the lower triangular matrix L and the diagonal matrix D are obtained; the calculation formulas for each part are: l jk =u jk / d k 。 3. The method for fast inversion of Hermitian matrix based on FPGA according to claim 1, characterized in that: The step S2 of inverting the lower triangular matrix L specifically comprises: firstly dividing the lower triangular matrix L into blocks to reduce the order of the matrix, and then inverting the low-order matrix after the block division, and the expression is:

4. The method for fast inversion of Hermitian matrix based on FPGA according to claim 1, characterized in that: The step S2 seeks the inverse of the diagonal matrix D by seeking the inverse of the diagonal elements of the matrix, and the expression is:

5. The method for fast inversion of Hermitian matrix based on FPGA according to claim 1, characterized in that: The matrix multiplication in step S3 is to perform matrix multiplication on the inverse calculation results of the lower triangular matrix L and the inverse calculation results of the diagonal matrix D to obtain the inverse matrix A. -1 , the expression is: A -1 =(L -1 ) H *D -1 *L -1 。 6. A system for implementing fast inversion of Hermitian matrices based on FPGA, used to implement the method for implementing fast inversion of Hermitian matrices based on FPGA as claimed in any one of claims 1 to 5, characterized in that: include: LDL decomposition module: The Hermitian matrix A enters the LDL decomposition module and is iteratively decomposed; L inversion module: inverse the lower triangular matrix L after LDL decomposition is completed; D inversion module: inverts the diagonal matrix D after LDL decomposition, inputs the diagonal elements of the diagonal matrix, and inverts all elements in parallel; Matrix multiplication module: receives the inverse matrix of the lower triangular matrix L and the diagonal matrix D, first transforms L -1 Perform conjugate transpose and D -1 Perform matrix multiplication to obtain the intermediate matrix LD, and finally the intermediate matrix LD is added to L -1 Perform matrix multiplication to obtain the inverse matrix A -1 .

7. The system for implementing fast inversion of Hermitian matrix based on FPGA according to claim 6, characterized in that: The state transformation of the LDL decomposition module during decomposition is specifically as follows: The module is in the IDLE state. When there is data to be processed, it enters the state Loop0. In the Loop0 state, counter 0 starts working, and the count value k ranges from 1 to n. After counter 0 is valid, it jumps to Loop1, counter 1 starts working, and the count value m ranges from 1 to k-1. At the same time, it starts calculating at each count value of counter 1. After counter 1 finishes counting, it jumps to Sub0 and starts counting d k =a kk -sum1; After Sub0 calculation is completed, it jumps to Loop2 state, counter 2 starts working, and the count value j ranges from k+1 to n. After the count value j is valid, it jumps to Loop3 state, counter 3 starts working, and the count value m ranges from 1 to k-1. At the same time, it starts calculating at each count value of counter 3 After counting 3, jump to Sub1 state and start counting u jk =a jk -sum2 and l jk =u jk / d k After Sub1 is finished calculating, it jumps to Loop2 again, and the calculated value of Counter 2 is increased by 1, and it jumps to Loop3 and Sub1 again in sequence until Counter 2 finishes counting; When Loop2 counts up, it jumps to Loop0 and repeats the above process until Counter 0 ends, and finally returns to the IDLE state, and the decomposition is completed.

8. The system for implementing fast inversion of Hermitian matrix based on FPGA according to claim 6, characterized in that: The state transformation of the L inversion module is specifically as follows: Jump from IDLE state to Loop0 state, the counting range of counter 0 count value i is 1 to n; after the count value of counter 0 is valid, the state machine jumps to Recip0 state and starts counting After the calculation is completed, it jumps to the Loop1 state, and the counting range of the count value j of counter 1 is 1 to i-1; After the count value j is valid, it jumps to the Loop2 state. The counting range of the count value k of counter 2 is j~i-1. When the count value k is valid, it is calculated After counting is completed, jump to state Mult0 and then calculate r ij =-invl*sum3, after the calculation is completed, jump to Loop1, then jump to Loop2 and Mult0 in turn until the count value j reaches the end value and then return to Loop0; Repeat the above steps until the count value i of counter 0 reaches the end value, return to state IDLE, and the inversion of the L matrix is ​​completed.

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