Equipment case intrusion detection system and detection method thereof

Abstract

The invention discloses an equipment case intrusion detection system and a detection method thereof, and belongs to the technical field of case equipment monitoring. In order to effectively perform intrusion protection on case equipment, the sensor is mounted at an opening and closing position of a case cover of the equipment; the control panel comprises a sensor interface, the sensor interface is connected with an intrusion memory circuit, the intrusion memory circuit is respectively connected with a clock generation circuit and a main control chip, the main control chip is respectively connected with a battery measurement circuit and a sound alarm circuit, and the battery measurement circuit is connected with a power supply circuit; the sensor is connected with the control panel through a sensor interface, and the control panel is respectively connected with a mainboard and an upper computer interface of the equipment case through a mainboard USB (Universal Serial Bus) interface; and the control panel outputs the state of the case cover through an IO port. The intrusion detection system provided by the invention can effectively prevent the operation of the equipment so as to protect the equipment from the risk of intrusion, is high in integration degree, can be smoothly accessed into various cases, is transparent to a user after being mounted in the cases, and can well adapt to the existing equipment.

Description

Technical Field

[0001] The invention belongs to the technical field of chassis equipment monitoring, and in particular relates to an equipment chassis intrusion detection system and a detection method thereof. Background Art

[0002] A chassis intrusion detection system is a device designed to monitor and alert on any unauthorized opening of the chassis. These systems typically contain sensors, software, and alarm mechanisms that can detect any unauthorized opening or closing of the chassis, as well as possible physical intrusion.

[0003] It is generally used in computers and servers, IoT devices, industrial control systems, security systems, data center security, military and defense fields, financial institutions, etc. The main application method is to install intrusion detection systems on key equipment to protect the equipment from unauthorized operations to prevent malicious operations or data leakage.

[0004] There are two main chassis intrusion detection technologies at present. One is the intrusion detection record integrated in the motherboard, which uses a touch switch to detect the opening and closing of the chassis cover. When the chassis cover is closed, the switch can be pressed down, which is judged as a normal chassis signal; when the chassis cover is opened, the switch pops up, which is judged as an intrusion signal. The signal is detected by the motherboard and recorded. This method can continue to use the motherboard battery for detection and record in the BIOS when the power is off, and can be viewed through the BIOS system or during the boot process. The other is a separate chassis intrusion detection circuit, which mainly detects the opening of the chassis through various sensors, and then provides a chassis opening and closing signal to other systems or motherboards. Sensors are no longer limited to touch switches, but have been extended to magnetic, photoelectric, sound wave and other means, but similar to touch switches, the purpose is to detect whether the chassis cover is open. This technology can provide sound and light prompts or access other detection systems when being invaded. However, there are the following defects: First, if the intrusion occurs in a power outage, it cannot effectively prevent the operation of the device when the device is powered on, or it cannot effectively detect the intrusion for a long time in a power outage. In this case, it is easy to put the protected device in danger, and malicious operations or data leakage will occur during the operation of the device due to the intrusion that has occurred. The second is that when the intrusion occurs during the operation of the protected device, the operation of the program or system on the protected device cannot be effectively terminated, indicating that the intrusion has occurred but effective stop-loss measures cannot be taken quickly and automatically. Summary of the invention

[0005] The problem to be solved by the present invention is to effectively protect chassis equipment from intrusion, and proposes an equipment chassis intrusion detection system and a detection method thereof.

[0006] To achieve the above object, the present invention is implemented through the following technical solutions:

[0007] An equipment chassis intrusion detection system comprises a sensor, a control panel and a host computer interface, wherein the sensor, the control panel and the host computer interface are installed inside the equipment chassis;

[0008] The sensor is installed at the opening and closing position of the equipment chassis cover;

[0009] The control board includes a sensor interface, the sensor interface is connected to an intrusion memory circuit, the intrusion memory circuit is respectively connected to a clock generation circuit and a main control chip, the main control chip is respectively connected to a battery measurement circuit and a sound alarm circuit, and the battery measurement circuit is connected to a power supply circuit;

[0010] The sensor and the control board are connected via a sensor interface, and the control board is respectively connected to a mainboard and a host computer interface of a device chassis via a mainboard USB interface; the control board outputs the chassis cover status via an IO port.

[0011] Furthermore, in the clock generating circuit, one end of the capacitor C4 is grounded, and the other end is connected to the Schmitt trigger input terminal A; one end of the resistor R14 is connected to the Schmitt trigger input terminal A, and the other end is connected to the Schmitt trigger output terminal Y, which is the output FF_CLK of the clock generating circuit; one end of the capacitor C3 is grounded, and the other end is connected to the Schmitt trigger power supply terminal, and this end is the uninterruptible power supply terminal VDD_SBY provided by the power supply circuit.

[0012] Furthermore, in the intrusion memory circuit, the clock input terminal CP of the trigger is connected to the output FF_CLK of the clock generation circuit; one end of the resistor R2 is connected to the uninterruptible power supply terminal VDD_SBY, and the other end is connected to the reset terminal 1R of the trigger; one end of the resistor R4 is connected to the chassis intrusion reset signal MCU_CASE_RST, and the other end is connected to the input terminal 1K of the trigger; one end of the resistor R7 is grounded, and the other end is connected to the trigger input terminal 1K; one end of the capacitor C2 is grounded, and the other end is connected to the uninterruptible power supply terminal VDD_SBY; one end of the resistor R1 is connected to the chassis opening signal in the sensor interface circuit

[0013] SWITCH_CASE_SIG and the other end are connected to the trigger input terminal 1J; one end of the resistor R5 is grounded, and the other end is connected to the trigger output terminal 1Q, which is also the intrusion signal MCU_CASE_STATE output by the intrusion memory circuit; one end of the resistor R6 is grounded, and the other end is connected to the trigger input terminal J; the power supply terminal and the ground terminal of the trigger are respectively connected to the uninterruptible power supply terminals VDD_SBY and GND.

[0014] Furthermore, in the intrusion memory circuit, the trigger is a JK trigger.

[0015] Furthermore, in the battery measurement circuit, one end of the resistor R13 is connected to the base of the transistor Q2, and the other end is the input end MCU_MEAS_EN of the battery measurement circuit; one end of the resistor R12 is grounded, and the other end is connected to the base of the transistor Q2; one end of the resistor R10 is grounded, and the other end is connected to the resistor R9, which is the output MCU_ADC of the battery measurement circuit; one end of R9 is connected to R10, and the other end is connected to the drain of the field effect transistor Q1; the gate of the field effect transistor Q1 is connected to the collector of the transistor Q2, the drain is connected to R9, and the source is connected to the positive electrode VBAT of the backup battery in the power supply circuit; one end of the resistor R11 is connected to the collector of the transistor Q2, and the other end is connected to the mainboard power supply 3.3V; the emitter of the transistor Q2 is grounded.

[0016] Furthermore, the sensor is one of mechanical button, magnetic detection, photoelectric ranging and acoustic ranging types.

[0017] A device chassis intrusion detection method is implemented based on the device chassis intrusion detection system, and includes the following steps:

[0018] After a device chassis intrusion detection system is powered on, it is first determined whether a handshake with a host computer interface is successful. If it is determined to be yes, a heartbeat packet is periodically sent to the host computer interface. If it is determined to be no, an application mode of not using the host computer interface is adopted.

[0019] An equipment chassis intrusion detection system performs battery power detection at regular intervals to determine whether a battery test interval has been reached. If so, the battery power is measured and a low-power alarm is issued when the backup battery is low in power. A low-power alarm notification is sent to the upper computer interface for the successful handshake with the upper computer interface in step S1;

[0020] A device chassis intrusion detection system performs chassis intrusion detection. When chassis intrusion occurs, the control board triggers a hardware interrupt, triggers a sound alarm, and sends a soft interrupt notification to the upper computer interface that successfully shakes hands with the upper computer interface in step S1;

[0021] For a successful handshake with the host computer interface in step S1, the host computer interface sends an intrusion release instruction to the control panel, stops the sound alarm and resets the intrusion memory circuit. A device chassis intrusion detection system releases all intrusion states and sends a confirmation release notification to the host computer interface.

[0022] Furthermore, continuous detection during power failure is used to continuously detect chassis intrusion to protect the device, which is achieved by using a JK trigger and a Schmitt trigger with a high-capacity button lithium battery;

[0023] Set the Schmitt trigger in the clock generation circuit to a multivibrator, whose operating voltage is 3.3V of a high-capacity button lithium battery, and the clock period T is:

[0024] T=1.45×C4×R14

[0025] The clock signal is FF_CLK, and the clock signal frequency f is:

[0026]

[0027] The clock signal is provided to the intrusion memory circuit as a clock trigger. Under the trigger of FF_CLK, the intrusion memory circuit detects whether the chassis cover is opened with T as a period.

[0028] Furthermore, the intrusion memory function is realized by the intrusion memory circuit and the sensor interface. The input signal of the intrusion memory function is the sensor, which is connected to the main control board through the sensor interface; the sensor interface J1 is used to connect the sensor; the sensor signal is input to the main control board after photoelectric isolation through the optical coupler U2;

[0029] The SWITCH_CASE_SIG signal is the chassis opening and closing signal transmitted by the sensor, which is connected to the J end of the JK trigger; MCU_CASE_RST is the input signal for resetting the intrusion memory circuit, which is connected to the K end of the JK trigger. Under the control of the main control chip of the control board, the intrusion state recorded by the intrusion memory circuit is reset to normal. MCU_CASE_STATE is the intrusion memory result output by the intrusion memory circuit. When it is high, it means that the chassis has been invaded. The result is:

[0030] MCU_CASE_STATE=(SWITCH_CASE_SIGN×MCU_CASE_STATE+MCU_CASE_RST'×MCU_CASE_STATE)×FF_CLK↑.

[0031] Beneficial effects of the present invention:

[0032] The device chassis intrusion detection system of the present invention has a high degree of integration and can be smoothly connected to various chassis. It is installed inside the chassis and is transparent to the user, so it can be well adapted to existing equipment.

[0033] The device chassis intrusion detection system described in the present invention can maintain a certain degree of independence and working ability even when the device is powered off. Even if the device is powered on again, the intrusion detection system can effectively prevent the operation of the device, thereby protecting the device from the risk of an intrusion that has already occurred.

[0034] The device chassis intrusion detection method described in the present invention designs an intelligent countermeasure mechanism. The present invention is connected to the power switch of the device or the access control system. When the device is intruded, the present invention can quickly cut off the power supply of the device or lock the room where the device is located to automatically stop the loss and reduce further damage and risks.

[0035] The device chassis intrusion detection method described in the present invention provides a host computer interface for system developers to call, making it simple and convenient to obtain the chassis intrusion status. Users can easily integrate this function into their systems without having to deeply understand the specific implementation details of the chassis intrusion detection system. This also allows users to quickly stop services and protect data security based on the intrusion status interrupt performed by the host computer interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the framework structure of an equipment chassis intrusion detection system of the present invention;

[0037] Figure 2 This is a circuit block diagram of the control board of the present invention;

[0038] Figure 3 The intrusion memory circuit diagram of the control board of the present invention;

[0039] Figure 4 A clock generating circuit diagram of the control board of the present invention;

[0040] Figure 5 The battery measurement circuit diagram of the control board of the present invention;

[0041] Figure 6 The power circuit diagram of the control board of the present invention;

[0042] Figure 7 The sound alarm circuit diagram of the control panel of the present invention;

[0043] Figure 8 The sensor interface circuit diagram of the control board of the present invention;

[0044] Fig. 9 Schematic diagram of sensor installation of the present invention

[0045] Fig.10 This is the host computer connection and battery measurement flow chart of the present invention;

[0046] Fig.11 This is a flow chart of intrusion signal processing of the present invention;

[0047] Fig.12 It is a flow chart of intrusion elimination of the present invention;

[0048] Fig.13 This is the power supply circuit block diagram. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the specific embodiments described are only part of the embodiments of the present invention, rather than all of the specific embodiments. The components of the specific embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations, and the present invention can also have other embodiments.

[0050] Therefore, the following detailed description of the specific embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected specific embodiments of the present invention. Based on the specific embodiments of the present invention, all other specific embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0051] In order to further understand the content, features and effects of the present invention, the following specific implementation methods are given as examples, and the attached Figure 1 -Attached Fig.12 The detailed instructions are as follows:

[0052] Embodiment 1:

[0053] An equipment chassis intrusion detection system comprises a sensor, a control panel and a host computer interface, wherein the sensor, the control panel and the host computer interface are installed inside the equipment chassis;

[0054] The sensor is installed at the opening and closing position of the equipment chassis cover;

[0055] The control board includes a sensor interface, the sensor interface is connected to an intrusion memory circuit, the intrusion memory circuit is respectively connected to a clock generation circuit and a main control chip, the main control chip is respectively connected to a battery measurement circuit and a sound alarm circuit, and the battery measurement circuit is connected to a power supply circuit;

[0056] The sensor and the control board are connected via a sensor interface, and the control board is respectively connected to a mainboard and a host computer interface of a device chassis via a mainboard USB interface; the control board outputs the chassis cover status via an IO port.

[0057] Furthermore, in the clock generating circuit, one end of the capacitor C4 is grounded, and the other end is connected to the Schmitt trigger input terminal A; one end of the resistor R14 is connected to the Schmitt trigger input terminal A, and the other end is connected to the Schmitt trigger output terminal Y, which is the output FF_CLK of the clock generating circuit; one end of the capacitor C3 is grounded, and the other end is connected to the Schmitt trigger power supply terminal, and this end is the uninterruptible power supply terminal VDD_SBY provided by the power supply circuit.

[0058] Furthermore, in the intrusion memory circuit, the clock input terminal CP of the trigger is connected to the output FF_CLK of the clock generating circuit; one end of the resistor R2 is connected to the uninterruptible power supply terminal VDD_SBY, and the other end is connected to the reset terminal 1R of the trigger; one end of the resistor R4 is connected to the chassis intrusion reset signal MCU_CASE_RST, and the other end is connected to the input terminal 1K of the trigger; one end of the resistor R7 is grounded, and the other end is connected to the trigger input terminal 1K; one end of the capacitor C2 is grounded, and the other end is connected to the uninterruptible power supply terminal VDD_SBY; one end of the resistor R1 is connected to the chassis start signal SWITCH_CASE_SIG in the sensor interface circuit, and the other end is connected to the trigger input terminal 1J; one end of the resistor R5 is grounded, and the other end is connected to the trigger output terminal 1Q, which is also the intrusion signal MCU_CASE_STATE output by the intrusion memory circuit; one end of the resistor R6 is grounded, and the other end is connected to the trigger input terminal J; the power supply terminal and the ground terminal of the trigger are respectively connected to the uninterruptible power supply terminal VDD_SBY and GND.

[0059] Furthermore, in the intrusion memory circuit, the trigger is a JK trigger.

[0060] Furthermore, in the battery measurement circuit, one end of the resistor R13 is connected to the base of the transistor Q2, and the other end is the input end MCU_MEAS_EN of the battery measurement circuit; one end of the resistor R12 is grounded, and the other end is connected to the base of the transistor Q2; one end of the resistor R10 is grounded, and the other end is connected to the resistor R9, which is the output MCU_ADC of the battery measurement circuit; one end of R9 is connected to R10, and the other end is connected to the drain of the field effect transistor Q1; the gate of the field effect transistor Q1 is connected to the collector of the transistor Q2, the drain is connected to R9, and the source is connected to the positive electrode VBAT of the backup battery in the power supply circuit; one end of the resistor R11 is connected to the collector of the transistor Q2, and the other end is connected to the mainboard power supply 3.3V; the emitter of the transistor Q2 is grounded.

[0061] Furthermore, the sensor is one of the types of mechanical button, magnetic detection, photoelectric ranging and sound wave ranging.

[0062] Embodiment 2:

[0063] A device chassis intrusion detection method is implemented based on the device chassis intrusion detection system described in Example 1, and includes the following steps:

[0064] After a device chassis intrusion detection system is powered on, it is first determined whether a handshake with a host computer interface is successful. If it is determined to be yes, a heartbeat packet is periodically sent to the host computer interface. If it is determined to be no, an application mode of not using the host computer interface is adopted.

[0065] An equipment chassis intrusion detection system performs battery power detection at regular intervals to determine whether a battery test interval has been reached. If so, the battery power is measured and a low-power alarm is issued when the backup battery is low in power. A low-power alarm notification is sent to the upper computer interface for the successful handshake with the upper computer interface in step S1;

[0066] A device chassis intrusion detection system performs chassis intrusion detection. When chassis intrusion occurs, the control board triggers a hardware interrupt, triggers a sound alarm, and sends a soft interrupt notification to the upper computer interface that successfully shakes hands with the upper computer interface in step S1;

[0067] For a successful handshake with the host computer interface in step S1, the host computer interface sends an intrusion release instruction to the control panel, stops the sound alarm and resets the intrusion memory circuit. A device chassis intrusion detection system releases all intrusion states and sends a confirmation release notification to the host computer interface.

[0068] Furthermore, continuous detection during power failure is used to continuously detect chassis intrusion to protect the device, which is achieved by using a JK trigger and a Schmitt trigger with a high-capacity button lithium battery;

[0069] Set the Schmitt trigger in the clock generation circuit to a multivibrator, whose operating voltage is 3.3V of a high-capacity button lithium battery, and the clock period T is:

[0070] T=1.45×C4×AR14

[0071] The clock signal is FF_CLK, and the clock signal frequency f is:

[0072]

[0073] The clock signal is provided to the intrusion memory circuit as a clock trigger. Under the trigger of FF_CLK, the intrusion memory circuit detects whether the chassis cover is opened with T as a period.

[0074] Furthermore, the intrusion memory function is realized by the intrusion memory circuit and the sensor interface. The input signal of the intrusion memory function is the sensor, which is connected to the main control board through the sensor interface; the sensor interface J1 is used to connect the sensor; the sensor signal is input to the main control board after photoelectric isolation through the optical coupler U2;

[0075] The SWITCH_CASE_SIG signal is the chassis opening and closing signal transmitted by the sensor, which is connected to the J end of the JK trigger; MCU_CASE_RST is the input signal for resetting the intrusion memory circuit, which is connected to the K end of the JK trigger. Under the control of the main control chip of the control board, the intrusion state recorded by the intrusion memory circuit is reset to normal. MCU_CASE_STATE is the intrusion memory result output by the intrusion memory circuit. When it is high, it means that the chassis has been invaded. The result is:

[0076] MCU_CASE_STATE=(SWITCH_CASE_SIGN×MCU_CASE_STATE+MCU_CASE_RST'×MCU_CASE_STATE)×FF_CLK↑.

[0077] Furthermore, the low power alarm function is realized by the cooperation of the power circuit and the main control on the control board. The power circuit is divided into three parts. The mainboard power supply refers to the power supply provided by the mainboard, which is effective when the protected device is powered on; when the device is powered off, a high-capacity button lithium battery is used as a backup battery; the switching of the two power supplies is realized by the power switching circuit; the mainboard power supply, the backup battery and the power switching circuit constitute the power circuit, and its circuit structure is shown in the power circuit; V3.3 is the mainboard power supply voltage value of 3.3V, BAT1 is the backup battery with a voltage of VBAT, R3 is the current limiting resistor for protecting the battery, and D1 is the original component for realizing power switching. It will give priority to the mainboard power supply according to the effective status of the mainboard power supply and the backup battery, and finally output a stable uninterruptible power supply VDD_SBY to other components on the control board, where the calculation formula of VDD_SBY is:

[0078]

[0079] Further, the battery measurement circuit, MCU_MEAS_EN is the signal for controlling the measurement of the backup battery voltage. The master will periodically pull up the MCU_MEAS_EN signal and read the battery power through MCU_ADC to ensure that the user is prompted and replaced before the backup battery is exhausted;

[0080] The battery measurement steps are as follows: first, MCU_MEAS_EN turns on Q2 when it is pulled high; second, the conduction of Q2 turns on Q1, which in turn connects MCU_ADC to the backup battery VBAT and divides the voltage through R9 and R10; third, the main control measures the backup battery voltage VBAT through ADC to estimate the battery power, and the battery voltage MCU measured by ADC ADS for:

[0081]

[0082] Among them, VFIX is the circuit error correction value, which is used to correct the error caused by circuit manufacturing;

[0083] When no measurement is performed, the MCU_MEAS_EN signal is pulled low to ensure maximum battery power conservation; if the battery voltage VBAT read is lower than the threshold VTHE, it is determined that the battery needs to be replaced, and the main control sends an alarm to the user through the host computer interface and sounds an alarm. The calculation formula of VTHE is:

[0084]

[0085] Furthermore, the sound alarm function is realized by the main control sound alarm circuit. In the sound alarm circuit diagram, B1 is a buzzer or a speaker, and Q3, R15 and R16 form an amplifier circuit for amplifying the main control signal to drive B1 to issue a sound alarm.

[0086] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0087] Although the present application has been described above with reference to specific embodiments, various modifications may be made thereto and parts thereof may be replaced with equivalents without departing from the scope of the present application. In particular, as long as there is no structural conflict, the various features in the specific embodiments disclosed in the present application may be used in combination with each other in any manner, and the fact that these combinations are not exhaustively described in this specification is only for the sake of omitting space and saving resources. Therefore, the present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A device chassis intrusion detection system, characterized in that: It includes a sensor, a control panel and a host computer interface, wherein the sensor, the control panel and the host computer interface are installed inside the equipment chassis; The sensor is installed at the opening and closing position of the equipment chassis cover; The control board includes a sensor interface, the sensor interface is connected to an intrusion memory circuit, the intrusion memory circuit is respectively connected to a clock generation circuit and a main control chip, the main control chip is respectively connected to a battery measurement circuit and a sound alarm circuit, and the battery measurement circuit is connected to a power supply circuit; The sensor and the control board are connected via a sensor interface, and the control board is respectively connected to a mainboard and a host computer interface of a device chassis via a mainboard USB interface; the control board outputs the chassis cover status via an IO port.

2. The device chassis intrusion detection system according to claim 1, characterized in that: In the clock generating circuit, one end of the capacitor C4 is grounded, and the other end is connected to the Schmitt trigger input terminal A; one end of the resistor R14 is connected to the Schmitt trigger input terminal A, and the other end is connected to the Schmitt trigger output terminal Y, which is the output FF_CLK of the clock generating circuit; one end of the capacitor C3 is grounded, and the other end is connected to the Schmitt trigger power supply terminal, and at the same time, this end is the uninterruptible power supply terminal VDD_SBY provided by the power supply circuit.

3. The device chassis intrusion detection system according to claim 2, characterized in that: In the intrusion memory circuit, the clock input terminal CP of the trigger is connected to the output FF_CLK of the clock generating circuit; one end of the resistor R2 is connected to the uninterruptible power supply terminal VDD_SBY, and the other end is connected to the reset terminal 1R of the trigger; one end of the resistor R4 is connected to the chassis intrusion reset signal MCU_CASE_RST, and the other end is connected to the input terminal 1K of the trigger; one end of the resistor R7 is grounded, and the other end is connected to the trigger input terminal 1K; one end of the capacitor C2 is grounded, and the other end is connected to the uninterruptible power supply terminal VDD_SBY; one end of the resistor R1 is connected to the chassis opening signal SWITCH_CASE_SIG in the sensor interface circuit, and the other end is connected to the trigger input terminal 1J; one end of the resistor R5 is grounded, and the other end is connected to the trigger output terminal 1Q, which is also the intrusion signal MCU_CASE_STATE output by the intrusion memory circuit; one end of the resistor R6 is grounded, and the other end is connected to the trigger input terminal J; the power supply terminal and the ground terminal of the trigger are respectively connected to the uninterruptible power supply terminal VDD_SBY and GND.

4. The device chassis intrusion detection system according to claim 3, characterized in that: In the intrusion memory circuit, the trigger is a JK trigger.

5. The device chassis intrusion detection system according to claim 4, characterized in that: In the battery measurement circuit, one end of the resistor R13 is connected to the base of the transistor Q2, and the other end is the input end MCU_MEAS_EN of the battery measurement circuit; one end of the resistor R12 is grounded, and the other end is connected to the base of the transistor Q2; one end of the resistor R10 is grounded, and the other end is connected to the resistor R9, which is the output MCU_ADC of the battery measurement circuit; one end of R9 is connected to R10, and the other end is connected to the drain of the field effect transistor Q1; the gate of the field effect transistor Q1 is connected to the collector of the transistor Q2, the drain is connected to R9, and the source is connected to the positive electrode VBAT of the backup battery in the power supply circuit; one end of the resistor R11 is connected to the collector of the transistor Q2, and the other end is connected to the mainboard power supply 3.3V; the emitter of the transistor Q2 is grounded.

6. The device chassis intrusion detection system according to claim 5, characterized in that: The sensor is one of mechanical button, magnetic detection, photoelectric ranging and sound wave ranging types.

7. A device chassis intrusion detection method, implemented by relying on a device chassis intrusion detection system according to any one of claims 1 to 6, characterized in that: The steps include: After a device chassis intrusion detection system is powered on, it is first determined whether a handshake with a host computer interface is successful. If it is determined to be yes, a heartbeat packet is periodically sent to the host computer interface. If it is determined to be no, an application mode of not using the host computer interface is adopted. An equipment chassis intrusion detection system performs battery power detection at regular intervals to determine whether a battery test interval has been reached. If so, the battery power is measured and a low-power alarm is issued when the backup battery is low in power. A low-power alarm notification is sent to the upper computer interface for the successful handshake with the upper computer interface in step S1; A device chassis intrusion detection system performs chassis intrusion detection. When chassis intrusion occurs, the control board triggers a hardware interrupt, triggers a sound alarm, and sends a soft interrupt notification to the upper computer interface that successfully shakes hands with the upper computer interface in step S1; For a successful handshake with the host computer interface in step S1, the host computer interface sends an intrusion release instruction to the control panel, stops the sound alarm and resets the intrusion memory circuit. A device chassis intrusion detection system releases all intrusion states and sends a confirmation release notification to the host computer interface.

8. A device chassis intrusion detection method according to claim 6, characterized in that: The power-off continuous detection is used to continuously detect chassis intrusion to protect the equipment. The implementation method is to use JK trigger and Schmitt trigger with high-capacity button lithium battery. Set the Schmitt trigger in the clock generation circuit to a multivibrator, whose operating voltage is 3.3V of a high-capacity button lithium battery, and the clock period T is: T=1.45×C4×R14 The clock signal is FF_CLK, and the clock signal frequency f is: The clock signal is provided to the intrusion memory circuit as a clock trigger. Under the trigger of FF_CLK, the intrusion memory circuit detects whether the chassis cover is opened with T as a period.

9. A device chassis intrusion detection method according to claim 8, characterized in that: The intrusion memory function is realized by the intrusion memory circuit and the sensor interface. The input signal of the intrusion memory function is the sensor, which is connected to the main control board through the sensor interface; the sensor interface J1 is used to connect the sensor; the sensor signal is input into the main control board after photoelectric isolation through the optocoupler U2; The SWITCH_CASE_SIG signal in the intrusion memory circuit is the chassis opening and closing signal transmitted by the sensor, which is connected to the J end of the JK trigger; MCU_CASE_RST is the input signal for resetting the intrusion memory circuit, which is connected to the K end of the JK trigger. Under the control of the main control chip of the control board, the intrusion state recorded by the intrusion memory circuit is reset to normal. MCU_CASE_STATE is the intrusion memory result output by the intrusion memory circuit. When it is high, it means that the chassis has been invaded. The result is: MCU_CASE_STATE=(SWITCH_CASE_SIGN×MCU_CASE_STATE+MCU_CASE_RST'×MCU_CASE_STATE)×FF_CLK↑.

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