Method for improving fault tolerance efficiency of soft topological structure based on quantum chip

Abstract

The invention relates to a method for improving fault tolerance efficiency based on a soft topological structure of a quantum chip. The method comprises the following steps: determining a quantum bit demand of quantum circuit operation in a quantum circuit; distributing an activation time interval for each quantum bit based on the quantum bit demand, and designing a control pulse sequence; and evolving each quantum bit according to the control pulse sequence in the activation time interval to realize the dynamic quantum circuit. By constructing a soft topological structure, namely, quantum bits are used for calculating activation time according to a model, generating and releasing the quantum bits as required and dynamically activating and closing the quantum bits, so that the time of exposing the quantum bits in environmental noise is shortened, the de-coherence rate and the error rate are reduced, and the overall fault tolerance of quantum calculation is improved; and the reliability of quantum calculation is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing, and in particular to a method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip. Background Art

[0002] Quantum computing is becoming a research hotspot in the global science and technology field due to its potential in solving complex computing problems. However, quantum computers face many challenges in their actual implementation. As the basic unit of quantum computing, the quantum state of qubits is easily affected by environmental noise, decoherence and other factors. Due to the characteristics of quantum superposition and entanglement, any slight interference may lead to the loss or erroneous propagation of quantum information. The error rate and fault tolerance of qubits are key issues that need to be solved urgently. Summary of the invention

[0003] In view of this, the present disclosure proposes a method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip.

[0004] This application constructs a soft topology structure for dynamically generating quantum bits, that is, quantum bits are generated and released on demand according to computing needs, which reduces the time they are exposed to environmental noise, reduces the risk of decoherence, and reduces the physical error rate of quantum bits accordingly. This improves the overall fault tolerance of quantum computing. When the soft topology structure is combined with quantum error correction codes, the reduction in physical error rate enables the error correction codes to function more effectively, further improving the reliability of logical quantum bits.

[0005] According to one aspect of the present application, a method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip is provided, comprising: Determine the qubit requirements for quantum circuit operations in a quantum circuit; Based on the qubit requirements, an activation time interval is allocated to each qubit, and a control pulse sequence is designed; During the activation time interval, each quantum bit evolves according to the control pulse sequence to realize a dynamic quantum circuit.

[0006] In a possible implementation, determining the quantum bit requirement of a quantum circuit operation in a quantum circuit includes: obtaining each quantum gate operation in the quantum circuit; and determining the quantum bit requirement of each quantum gate operation.

[0007] In a possible implementation, when allocating an activation time interval to each quantum bit, the activation time interval is calculated based on a trained time-varying quantum bit activation model.

[0008] In a possible implementation, during the activation time interval, each quantum bit evolves according to the control pulse sequence, further comprising: When not in the activation time interval, each quantum bit remains in the ground state or the isolated state.

[0009] In a possible implementation, the trained time-varying quantum bit activation model includes the following steps: Assigning an activation time and a deactivation time to each quantum bit in the quantum circuit, wherein the time interval between the activation time and the deactivation time is the activation time interval assigned to the quantum bit; Defining a quantum bit activation function, designing a control pulse sequence, each quantum bit undergoes state evolution according to the control pulse, and calculating the physical error rate of the evolution; Predict parameters such as minimum activation time, number of gates, circuit depth, number of qubits, and physical error rate; A loss function is calculated according to the parameters, the loss function is minimized to update the parameters, and the quantum circuit is input for multiple training until the optimal parameters are found.

[0010] In a possible implementation, calculating the evolved physical error rate further includes: a logic error rate and an overall physical error rate; For each qubit, the physical error rate of a single qubit is calculated based on the activation time of each qubit; For a system with multiple qubits, the overall physical error rate of the system is calculated based on the physical error rate of a single qubit; The logical error rate is obtained based on the quantum error correction code and the physical error rate of a single quantum bit.

[0011] In a possible implementation, the fault tolerance efficiency is evaluated by comparing the logic error rate with a preset system requirement; The quantum bit activation time is adjusted according to the evaluation result of the fault tolerance efficiency.

[0012] According to another aspect of the present disclosure, a system for improving fault tolerance efficiency based on a soft topology structure of a quantum chip is provided, comprising: an analysis module, an allocation module; The analysis module is configured to determine the quantum bit requirements in the quantum circuit; The allocation module is configured to allocate an activation time interval for each qubit based on the qubit requirement and design a control pulse sequence; During the activation time interval, each quantum bit evolves according to the control pulse sequence to realize a dynamic quantum circuit.

[0013] According to another aspect of the present disclosure, a device for improving fault tolerance efficiency based on a soft topology structure of a quantum chip is provided, comprising: a processor; a memory for storing processor executable instructions; wherein the processor is configured to execute the above method.

[0014] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0015] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0017] Figure 1 A flow chart showing a method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to an embodiment of the present application; Figure 2 A diagram showing a soft topological structure of a quantum biton in an embodiment of the present application is shown; Figure 3 A diagram showing a soft topology structure of a quantum bit in an embodiment of the present application is shown; Figure 4 A schematic diagram of a QFT circuit before optimization in an embodiment of the present application is shown; Figure 5 A schematic diagram of an optimized QFT circuit according to an embodiment of the present application is shown; Figure 6 A probability distribution comparison diagram showing the soft topology structure of an embodiment of the present application and the original topology structure; Figure 7 A schematic diagram showing a comparison of the logic error rate according to the embodiment of the present application as the code distance changes; Figure 8 A schematic diagram showing a comparison of the fault tolerance efficiency between the soft topology structure of an embodiment of the present application and the original topology structure is shown. DETAILED DESCRIPTION

[0018] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0019] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0020] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0021] The solution of the present application is implemented in a quantum computing device based on a soft topology structure, and the specific implementation examples for calculation are as follows.

[0022] Example 1 Figure 1 A flow chart of a method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to an embodiment of the present application is shown. The method of this embodiment includes the following steps: Step S100: Determine the quantum bit requirements for quantum circuit operations in the quantum circuit. Quantum circuit refers to a model of quantum computing based on a soft topology structure, which represents a quantum logic circuit that operates on quantum bits under an abstract concept. Quantum circuit operations in quantum circuits include quantum gate operations, measurement operations, and entanglement operations. This step calculates the quantum bit requirements for all operations of the quantum circuit currently being executed. The quantum bit requirement refers to the quantum bits required for each quantum gate operation when executing the quantum circuit operation, and the quantum bit requirements required for different operations are also different.

[0023] Step S200: Based on the quantum bit requirements, an activation time interval is assigned to each quantum bit, and a control pulse sequence is designed. The activation time interval is the interval between the activation time and the shutdown time. The control pulse sequence is obtained according to the activation function. The activation function a i (t) is a function of time t, ti,on and ti,off are the activation and deactivation time of the quantum bit qi, respectively. In this step, an activation time interval is assigned to each quantum bit to ensure that the quantum bit is in an activated state when it needs to participate in the operation. When the value of the activation function is 1, it means that the quantum bit is in an activated state; when the value of the activation function is 0, it means that the quantum bit is in an inactive state, including the ground state and the isolated state, reducing the exposure time of the quantum bit to reduce the decoherence effect.

[0024] Step S300: During the activation time interval, each qubit is evolved according to the control pulse sequence to realize a dynamic quantum circuit. The control pulse sequence refers to the control signal of the qubit, which controls the qubit to evolve in state according to a predetermined quantum operation. By applying a pulse modulation signal to the qubit, interaction and state modification between qubits are realized, thereby realizing dynamic quantum computing.

[0025] When determining the quantum bit requirements of quantum circuit operations in a quantum circuit, it includes: obtaining each quantum gate operation in the quantum circuit; determining the quantum bit requirements of each quantum gate operation. Since the quantum bit topological relationship of the actual hardware may not match the computational route structure of the quantum logic circuit, the high-level quantum gates are decomposed into the basic gates (basis gates) operations that can be supported by the quantum computing device based on the soft topological structure of this application. Based on the decomposed quantum gate operations, the quantum bit requirements for each gate operation are determined.

[0026] Considering the topology and connectivity of the device, the logical qubits are mapped to the physical qubits, and the activation time interval is calculated based on the trained time-varying qubit activation model. The training steps of the trained time-varying qubit activation model include: Assigning an activation time and a deactivation time to each quantum bit in the quantum circuit, wherein the time interval between the activation time and the deactivation time is the activation time interval assigned to the quantum bit; Define the qubit activation function, design the control pulse sequence, each qubit evolves according to the control pulse, and calculates the physical error rate of the evolution; the control pulse sequence refers to the control signal that controls the qubit, which is used to realize the interaction between qubits. Since it is difficult for the physical device to couple all qubits during execution, the necessary SWAP gate is inserted to ensure the connectivity of the quantum computing device. Among them, the SWAP gate is a swap gate, which is used to exchange the execution order of two qubits during evolution.

[0027] Predict parameters such as minimum activation time, number of gates, circuit depth, number of qubits, and physical error rate; A loss function is calculated according to the parameters, the loss function is minimized to update the parameters, and the quantum circuit is input for multiple training until the optimal parameters are found.

[0028] Based on the time-varying quantum bit activation model trained in the above steps, when a new quantum circuit is input, the activation time and shutdown time of each quantum bit in the quantum circuit are calculated according to the optimized parameters, and an activation time interval is assigned to each quantum bit. The activation function of the quantum bit is defined based on the activation time and shutdown time of the quantum bit, and the control pulse sequence is designed according to the activation function, so that each quantum bit in the quantum circuit evolves according to the control pulse.

[0029] The quantum computing soft topology based on the Time-Dependent Qubit Activation (TDQA) model realizes the on-demand generation and release of quantum bits. Physically, the hardware of quantum bits may always exist, but in actual operations, the quantum bits at the corresponding position on the timeline are activated only when needed, so that the quantum bits in the quantum circuit participate in the calculation only when needed, and enter the idle or isolated state when not needed, thereby reducing the time that the quantum bits are exposed to environmental noise and improving the fault tolerance of quantum computing.

[0030] In the activation time interval, each qubit evolves according to the control pulse sequence; in the set activation time and shutdown time interval, the qubit is in an activated state; at other times outside the activation time and shutdown time interval, the qubit is in an inactive state. In the activation time interval, each qubit is executed according to the predetermined gate operation, and when not in the activation time interval, each qubit maintains a predetermined ground state or isolated state.

[0031] After each quantum bit in the quantum circuit evolves its state according to the control pulse, the physical error rate of a single quantum bit is calculated for each quantum bit based on the activation time of each quantum bit. During the quantum computing process, steps such as quantum gate operations and measurement operations will introduce errors, and will gradually accumulate with the increase in computing depth. The physical error rate refers to the error rate generated by each operation in the quantum physical circuit, which is subject to the physical implementation of quantum computing, the manipulation method and the environmental noise mechanism.

[0032] For a system with multiple qubits, the overall physical error rate of the system is calculated based on the physical error rate of a single qubit; The logical error rate is obtained based on the quantum error correction code and the physical error rate of a single quantum bit. The error correction code can be adjusted according to the actual application environment, and no specific parameters are limited in this application. The fault tolerance efficiency is evaluated by comparing the logical error rate with the preset requirements of the system; the quantum bit activation time is adjusted according to the evaluation result of the fault tolerance efficiency.

[0033] Specifically, first determine all quantum circuit operations in the quantum circuit, including quantum gates, measurements, and entanglement. Analyze the quantum bit requirements required for all quantum operations, and then allocate activation intervals based on the quantum bit requirements. First, decompose the high-level quantum gates into the basic gate set (basis gates) supported by the target device. Since the quantum bit topology of the actual hardware may not match the structure of the required logical quantum bit topology circuit, it is difficult to couple all quantum bits during execution. Therefore, considering the topology and connectivity of the physical device, insert the necessary SWAP gates in the circuit to meet the connection restrictions between physical bits and map the logical quantum bits to the physical quantum bits.

[0034] like Figure 2 and Figure 3 As shown, Figure 2 It is the topological diagram of the original topological structure of the quantum bit; Figure 3 This is the dynamic topological structure diagram of the quantum bit soft topological structure.

[0035] The red part in the figure represents the quantum bits in the activated state, and the green part represents the quantum bits in the inactivated state. In the original topological structure, all the quantum bits are in the activated state at the beginning of the circuit. In the soft topological structure proposed in this application, the quantum bits are not all activated, but are activated and released on demand. The quantum bits that are not participating in quantum computing at the current moment maintain the ground state or the isolated state to reduce the time the quantum bits are exposed to environmental noise.

[0036] It should be noted that what is shown in the figure is only an exemplary description of an embodiment of the present application. The actual topological structure is not limited to a mesh structure and can be any topological structure, which is not specifically limited in the present application.

[0037] The activation time interval is calculated based on the time-varying quantum bit activation model. The training steps of the time-varying quantum bit activation model are as follows, minimizing the overall number of gates, depth, number of quantum bits, and physical error rate under the premise of equivalent calculation: Among them, G represents the number of gate operations, that is, the number of circuit gates; D represents the circuit depth; Q represents the number of quantum bits; Pphys represents the physical error rate; ti,on represents the activation time of the corresponding quantum bit; ti,off represents the shutdown time of the corresponding quantum bit.

[0038] The form of calculating the loss function is as follows: in, is the weight parameter, and by adjusting the importance of different optimization objectives, the function L is minimized to reduce the number of gate operations, depth, number of quantum bits, physical error rate, and activation time.

[0039] For each quantum bit qi, an activation time interval [ti,on and ti,off] is assigned according to the algorithm steps to ensure that the quantum bit is in an activated state when it needs to participate in the operation.

[0040] Among them: ti,on and ti,off are the activation and deactivation time of quantum bit qi respectively.

[0041] According to the activation function a i (t), design control pulse sequences to minimize interference with adjacent qubits.

[0042] During activation, the quantum bit evolves its state according to predetermined quantum operations, including executing quantum gate operations, participating in entanglement, etc.

[0043] When not in the activation time interval, the quantum bit remains in the ground state or isolated state to reduce the decoherence effect A large amount of quantum circuit data is input to obtain a trained time-varying quantum bit activation model (i.e., a deep learning model), and the optimal parameters are found through the trained time-varying quantum bit activation model, that is, under the premise of equivalent calculation, the overall number of gates, depth, number of quantum bits and physical error rate are minimized, the depth and number of gates of the circuit are reduced, and the execution efficiency and reliability are improved. The method of using a deep learning model to find the optimal solution is a conventional technical means in the technical field of this application and will not be described in detail in this application.

[0044] In a specific embodiment of the present application, a quantum Fourier transform (QFT) calculation of 4 qubits is performed. Figure 4 The QFT circuit in the original topology before optimization is shown. The circuit includes multiple gate operations: Hadamard gate, phase gate P(π / 2), phase gate P(π / 4) and phase gate P(π / 8). The four quantum bits (q0, q1, q2, q3) are in operation at the same time, and they are finally measured at the end of the circuit.

[0045] like Figure 5 In the QFT circuit under the optimized soft topology, the qubits perform different operations at different times, rather than performing operations at the same time all the time. The measurement of the qubits is not measured together at the end but there are intermediate measurements, which shows that the qubits under the soft topology are activated on demand.

[0046] For the exposure time Ti of each quantum bit qi, there is the following calculation method: By controlling ti,on and ti,off, the exposure time of the qubit can be adjusted: Among them, the physical error rate Pphys,i, the exposure time Ti of the quantum bit, the environmental decoherence rate ℷ, ℷ = 1 / T2, T2 is the coherence time. The coherence time is directly measured by other physical devices. The measurement of the coherence time is a conventional technical means in this field and will not be repeated in this application.

[0047] For a system with N qubits, the physical error rate of all qubits is accumulated, and the overall physical error rate is: According to the physical error rate and computational requirements, select an appropriate quantum error correction code and code distance. Using a quantum error correction code, the relationship between the logical error rate \(p_{log}\) and the physical error rate is: where \(A\) is a constant related to the specific implementation of the error correction code. Preferably, in a specific embodiment of the present application, it is preset to 0.1. By comparing the logical error rate \(P_{log}\) with the system requirements, evaluate whether the fault tolerance meets the requirements. According to the evaluation results, adjust the activation time of the qubits and the error correction code parameters to optimize the system performance.

[0048] \(P_{th}\) is the fault tolerance threshold of the error correction code, and \(d\) is the code distance of the error correction code, representing the number of errors that can be corrected. Preferably, in a specific embodiment of the present application, \(P_{th}\) is set to 1%, and \(d\) takes a value of 5; it should be noted that the error correction code and the code distance can be adjusted according to the actual situation of the superconducting qubits, and no specific limitation is made.

[0049] Minimize the overall error rate of each calculation and reduce the exposure time \(T\). According to the physical error rate calculation formula: Reducing the exposure time \(T\) will reduce \(P_{phys}\). Making the physical error rate lower than the threshold error rate enables the error correction code to work effectively. Under the condition of meeting the error correction conditions, by appropriately increasing the code distance \(d\), the logical error rate decreases exponentially. Among them, the threshold error rate depends on the selection of the error correction code and the nature of the environmental noise.

[0050] In a specific embodiment of the present application, the original topological structure and the soft topological structure process the same quantum circuit. The following table shows the comparison of the operation time and error rate of the original topological structure and the soft topological structure of the same equivalent quantum calculation: The operation time of the original topological structure is 10 μs, and the operation time of the soft topological structure is 2 μs. The exposure time of the qubits is shortened by 5 times, and the physical error rate is also reduced accordingly.

[0051] Specifically, calculate the physical error rates of the original topological structure and the soft topological structure respectively: Physical error rate of the original topological structure: Physical error rate of the soft topological structure: Since \(P_{phys,soft} = 0.40\% \lt p_{th} = 1\%\), by reducing the exposure time, the physical error rate is reduced below the threshold error rate, and the quantum error correction code can effectively correct errors. The physical error rate of the quantum calculation based on the soft topological structure is also reduced by 4.95 times accordingly.

[0052] Calculate the logical error rate based on the physical error rate: Logical error rate of the original topology: Soft topology logic error rate: Based on the soft topology structure proposed in this application, the logical error rate for the same quantum circuit was reduced from 77.61% to 0.64%, a significant reduction of 121.58 times.

[0053] All qubits in the original topological quantum circuit are activated at the same time at the beginning, and the exposure time of qubits is long, which cannot effectively reduce the error rate. However, in the soft topological quantum circuit of the present application, qubits are generated and released on demand, which significantly reduces the overall error rate of each calculation by reducing the exposure time of qubits to the environment.

[0054] The experimental measurement results before and after optimization show that Figure 6 ,The circuits before and after optimization have the same probability distribution, which shows that the adjusted soft ,topology structure has the same function as the original topology structure.

[0055] Comparison of logical error rates between soft topology and hard topology under the same code distance. The logical error rates of different code distances d (5, 7, 9, 13, 19, 21, 29) are calculated and compared. By increasing the code distance d, the logical error rate Plog can be reduced and the error correction effect can be improved. Figure 7 This is a schematic diagram of the change of logical error rate with code distance. Under the same code distance, the soft topology structure can further reduce the logical error rate than the hard topology structure, thus improving the reliability of quantum computing.

[0056] The above embodiments illustrate that the quantum bits of the soft topology structure are generated on demand rather than being in working state at the same time when the circuit starts.

[0057] According to another aspect of the present disclosure, there is also provided a system for improving fault tolerance efficiency based on a soft topology structure of a quantum chip, comprising: an analysis module, an allocation module; The analysis module is configured to determine the quantum bit requirements of quantum circuit operations in the quantum circuit; The allocation module is configured to allocate an activation time interval for each qubit based on the qubit requirement and design a control pulse sequence; During the activation time interval, each quantum bit evolves according to the control pulse sequence to realize a dynamic quantum circuit.

[0058] In order to quantify the fault tolerance of the system in a noisy environment, a fault tolerance efficiency formula is defined to represent the fault tolerance performance of a quantum bit under a specific exposure time: Among them, η is the fault tolerance efficiency of the system, and the higher the value, the stronger the fault tolerance capability; α is the noise factor, which indicates the intensity of the environmental noise to which the quantum bit is subjected. The default value is α=2000Sˆ-1 (coherence time is 500 microseconds). texposed is the time the quantum bit is exposed to the noise. In the original hard topology (hereinafter referred to as the hard topology), the quantum bits are exposed to the environmental noise for a long time, so the fault tolerance efficiency is low: Under the soft topology of this application, the quantum bit is exposed to environmental noise for a shorter time, so the fault tolerance is higher: The soft topology significantly improves fault tolerance by reducing the exposure time of quantum bits to environmental noise.

[0059] like Figure 8 The comparison of the fault tolerance efficiency between the soft topology and the hard topology is shown. The dotted part SoftTopology represents the fault tolerance efficiency of the soft topology generated on demand at different time steps. The fluctuation is relatively stable and the overall fault tolerance efficiency range is maintained between 0.8 and 1.0. It should be noted that the hard topology is only used to describe the original quantum computing topology in contrast to the soft topology of quantum computing in this application, and cannot be understood as an indicated technical feature.

[0060] The solid line part Origin Topology represents the fault tolerance efficiency of the fixed hard topology structure at different time steps, and the overall fault tolerance efficiency ranges from 0.4 to 0.6. The gray area is the gap in fault tolerance efficiency between the soft topology structure and the hard topology structure. In most time steps, the soft topology structure is better than the hard topology structure. The soft topology structure proposed in this application can significantly improve the accuracy and reliability of calculations in quantum computing.

[0061] Furthermore, according to another aspect of the present disclosure, a device for improving fault tolerance efficiency based on the soft topology structure of a quantum chip is also provided. The device for improving fault tolerance efficiency based on the soft topology structure of a quantum chip in the embodiment of the present disclosure includes a processor and a memory for storing processor executable instructions. Wherein, the processor is configured to implement any of the above methods when executing executable instructions. It should be noted here that the number of processors can be one or more. The processor and the memory can be connected via a bus or in other ways, which are not specifically limited here.

[0062] The memory, as a computer-readable storage medium, can be used to store software programs, computer executable programs and various modules, such as the program or module corresponding to the method for improving fault tolerance efficiency based on the soft topology structure of quantum chips in the embodiment of the present disclosure. The processor executes various functional applications and data processing of the device for improving fault tolerance efficiency based on the soft topology structure of quantum chips by running the software programs or modules stored in the memory.

[0063] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, any of the above-mentioned methods for improving fault tolerance efficiency based on a soft topology structure of a quantum chip is implemented.

[0064] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for improving fault tolerance efficiency based on a soft topological structure of a quantum chip, characterized in that: include: Determine the qubit requirements for quantum circuit operations in a quantum circuit; Based on the qubit requirements, an activation time interval is allocated to each qubit, and a control pulse sequence is designed; During the activation time interval, each quantum bit evolves according to the control pulse sequence to realize a dynamic quantum circuit.

2. The method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to claim 1, characterized in that: Determining the quantum bit requirement of a quantum circuit operation in a quantum circuit includes: obtaining each quantum gate operation in the quantum circuit; The quantum bit requirement for each quantum gate operation is determined.

3. The method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to claim 1, characterized in that: When allocating an activation time interval to each quantum bit, the activation time interval is calculated based on a trained time-varying quantum bit activation model.

4. The method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to claim 1, characterized in that: During the activation time interval, each quantum bit evolves according to the control pulse sequence, further comprising: When not in the activation time interval, each quantum bit remains in the ground state or the isolated state.

5. The method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to claim 3, characterized in that: The training steps of the trained time-varying quantum bit activation model include: Assigning an activation time and a deactivation time to each quantum bit in the quantum circuit, wherein the time interval between the activation time and the deactivation time is the activation time interval assigned to the quantum bit; Defining a quantum bit activation function, designing a control pulse sequence, each quantum bit undergoes state evolution according to the control pulse, and calculating the physical error rate of the evolution; Predict parameters such as minimum activation time, number of gates, circuit depth, number of qubits, and physical error rate; A loss function is calculated according to the parameters, the loss function is minimized to update the parameters, and the quantum circuit is input for multiple training until the optimal parameters are found.

6. The method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to claim 5, characterized in that: Calculating the evolved physical error rate also includes: a logical error rate and an overall physical error rate; For each qubit, the physical error rate of a single qubit is calculated based on the activation time of each qubit; For a system with multiple qubits, the overall physical error rate of the system is calculated based on the physical error rate of a single qubit; The logical error rate is obtained based on the quantum error correction code and the physical error rate of a single quantum bit.

7. The method for improving fault tolerance efficiency based on a soft topology structure of a quantum chip according to claim 6, characterized in that: By comparing the logic error rate with the preset requirements of the system, the fault tolerance efficiency is evaluated; The quantum bit activation time is adjusted according to the evaluation result of the fault tolerance efficiency.

8. A system for improving fault tolerance efficiency based on a soft topological structure of a quantum chip, characterized in that: include: Analysis module, allocation module; The analysis module is configured to determine the quantum bit requirements of quantum circuit operations in the quantum circuit; The allocation module is configured to allocate an activation time interval for each qubit based on the qubit requirement and design a control pulse sequence; During the activation time interval, each quantum bit evolves according to the control pulse sequence to realize a dynamic quantum circuit.

9. A device for improving fault tolerance efficiency based on a soft topological structure of a quantum chip, characterized in that: include: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the method described in any one of claims 1 to 7 when executing the executable instructions.

10. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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