High-heat-dissipation inverted packaging structure and method

Abstract

The invention discloses a high-heat-dissipation inverted packaging method and structure, and relates to the technical field of packaging heat dissipation. The method comprises the following steps: preparing a semi-finished substrate; placing a first flip chip on the conductive structure in the cavity, and enabling a pin of the first flip chip to be conductively connected with the second circuit layer; covering the second surface of the dielectric layer with a packaging material, and enabling the packaging material to cover the first conduction column and the first flip chip; and arranging a heat dissipation structure on the surface of the first circuit layer. According to the high-heat-dissipation inverted packaging method provided by the embodiment of the invention, the heat dissipation structure is adopted to dissipate heat of the chip, so that the chip is directly packaged by the heat dissipation structure, heat generated during operation of the chip and a device can be quickly taken away through the heat dissipation structure, and the heat dissipation performance of packaging is greatly improved; the manufacturing process is simple, the cost is low, the heat dissipation performance of the product is greatly improved, and the product has more excellent reliability and stability.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging heat dissipation, and in particular to a high heat dissipation inverted packaging structure and method. Background Art

[0002] With the development and progress of electronic technology, electronic products are evolving towards being short, light and thin, and the functional requirements of electronic products are becoming increasingly powerful, which has promoted the packaging structure of electronic products to develop towards a highly integrated and miniaturized direction, and embedded packaging of components such as chips has emerged; at the same time, the application of electronic components is also developing towards high frequency, high speed and high power, resulting in a rapid increase in heat flux density per unit area. As we all know, with the increase in the operating environment temperature, the operating speed of electronic components decreases, and the loss increases. At the same time, the reliability of electronic products is relatively reduced when they are operated in a high temperature environment for a long time. Therefore, if the heat generated by high-frequency, high-speed and high-power electronic components cannot be dissipated in time, the performance and reliability of electronic products will be seriously affected. Therefore, under the general trend of high frequency, high speed and high power, how to reasonably optimize the heat dissipation performance of the packaging structure is an important topic at present. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a high heat dissipation inverted packaging structure and method, which can optimize the heat dissipation performance of the packaging structure.

[0004] On the one hand, a high heat dissipation inverted packaging method according to an embodiment of the present invention comprises the following steps:

[0005] Prepare a semi-finished substrate; the semi-finished substrate comprises a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, the dielectric layer is provided with a cavity penetrating the dielectric layer, a conductive structure is provided in the cavity, the conductive structure is conductively connected to the first circuit layer, and a first conductive column is provided on the surface of the second circuit layer;

[0006] Placing a first flip chip on the conductive structure in the cavity, and conductively connecting the pins of the first flip chip to the second circuit layer;

[0007] Covering the second surface of the dielectric layer with packaging material, so that the packaging material covers the first conductive pillar and the first flip chip;

[0008] A heat dissipation structure is arranged on the surface of the first circuit layer.

[0009] According to some embodiments of the present invention, a third circuit layer and a second conductive pillar are further disposed inside the dielectric layer, and the third circuit layer is conductively connected to the second circuit layer through the second conductive pillar.

[0010] According to some embodiments of the present invention, the conductive structure comprises:

[0011] An insulating medium is disposed in the cavity;

[0012] A third conductive column is disposed in the insulating medium, and one end of the third conductive column is conductively connected to the first circuit layer;

[0013] A conductive layer is disposed on the surface of the insulating medium and is conductively connected to the other end of the third conductive column. The first flip chip is disposed on the conductive layer.

[0014] According to some embodiments of the present invention, the step of placing a first flip chip on the conductive structure in the cavity and conductively connecting the pins of the first flip chip to the second circuit layer further includes:

[0015] A plurality of second flip chips or components are placed on the second circuit layer.

[0016] According to some embodiments of the present invention, the method further comprises the following steps:

[0017] A ball is planted on the surface of the first conductive column.

[0018] On the other hand, the high heat dissipation inverted packaging method according to an embodiment of the present invention includes the following steps:

[0019] Prepare a semi-finished substrate; the semi-finished substrate comprises a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, a surface of the second circuit layer is provided with a first conductive column, a fourth conductive column is provided in the dielectric layer, and the fourth conductive column is conductively connected to the first circuit layer and the second circuit layer respectively;

[0020] Placing a first flip chip on the surface of the second circuit layer, and electrically connecting the pins of the first flip chip to the second circuit layer;

[0021] Covering the second surface of the dielectric layer with packaging material, so that the packaging material covers the first conductive pillar and the first flip chip;

[0022] A heat dissipation structure is arranged on the surface of the first circuit layer.

[0023] According to some embodiments of the present invention, a third circuit layer and a second conductive pillar are further disposed inside the dielectric layer, and the third circuit layer is conductively connected to the second circuit layer through the second conductive pillar.

[0024] According to some embodiments of the present invention, the method further comprises the following steps:

[0025] A ball is planted on the surface of the first conductive column.

[0026] On the other hand, a high heat dissipation inverted package structure according to an embodiment of the present invention includes:

[0027] A semi-finished substrate, the semi-finished substrate comprising a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, the dielectric layer is provided with a cavity penetrating the dielectric layer, a conductive structure is provided in the cavity, the conductive structure is conductively connected to the first circuit layer, and a first conductive column is provided on the surface of the second circuit layer;

[0028] A first flip chip is disposed on the conductive structure in the cavity, and a pin of the first flip chip is conductively connected to the second circuit layer;

[0029] A packaging material is covered on the second surface of the dielectric layer, and the packaging material covers the first conductive pillar and the first flip chip;

[0030] The heat dissipation structure is arranged on the surface of the first circuit layer.

[0031] On the other hand, a high heat dissipation inverted package structure according to an embodiment of the present invention includes:

[0032] A semi-finished substrate, the semi-finished substrate comprising a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, a surface of the second circuit layer is provided with a first conductive column, a fourth conductive column is provided in the dielectric layer, and the fourth conductive column is conductively connected to the first circuit layer and the second circuit layer respectively;

[0033] A first flip chip is disposed on the surface of the second circuit layer, and a pin of the first flip chip is conductively connected to the second circuit layer;

[0034] A packaging material is covered on the second surface of the dielectric layer, and the packaging material covers the first conductive pillar and the first flip chip;

[0035] The heat dissipation structure is arranged on the surface of the first circuit layer.

[0036] The high heat dissipation inverted packaging structure and method according to the embodiments of the present invention have at least the following beneficial effects:

[0037] The heat dissipation structure is used to dissipate heat from the chip, so that the chip is directly packaged by the heat dissipation structure, so that the heat generated by the chip and the device during operation can be quickly taken away by the heat dissipation structure, greatly improving the heat dissipation performance of the packaging structure. According to the high heat dissipation inverted packaging method of the embodiment of the present invention, the manufacturing process is simple and the cost is low, which greatly improves the heat dissipation performance of the product, and the product has more superior reliability and stability.

[0038] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0040] Figure 1 A flowchart of the steps of a high heat dissipation inverted packaging method according to a first embodiment of the present invention;

[0041] Figure 2 A schematic structural diagram of a semi-finished substrate according to a first embodiment of the present invention;

[0042] Figure 3 It is a schematic structural diagram of a first embodiment of the present invention after a first flip chip is placed on a semi-finished substrate;

[0043] Figure 4 It is a schematic structural diagram of a first embodiment of the present invention after placing a first flip chip and a second flip chip on a semi-finished substrate;

[0044] Figure 5 For Figure 3 A schematic structural diagram of the first flip chip after wire bonding;

[0045] Figure 6 For Figure 4 A schematic structural diagram of the first flip chip after wire bonding;

[0046] Figure 7 For Figure 5 A schematic diagram of the structure after the structure is encapsulated;

[0047] Figure 8 For Figure 6 A schematic diagram of the structure after the structure is encapsulated;

[0048] Fig. 9 For Figure 7 A schematic diagram of the structure after the first conductive column is ball-planted;

[0049] Fig.10 For Figure 8 A schematic diagram of the structure after the first conductive column is ball-planted;

[0050] Fig.11 For Fig. 9 A schematic diagram of the structure after the heat dissipation structure is set;

[0051] Fig.12 For Fig.10 A schematic diagram of the structure after the heat dissipation structure is set;

[0052] Fig.13 A flowchart of the steps of a high heat dissipation inverted packaging method according to a second embodiment of the present invention;

[0053] Fig.14 A schematic structural diagram of a semi-finished substrate according to a second embodiment of the present invention;

[0054] Fig.15 It is a schematic structural diagram of a second embodiment of the present invention after a first flip chip is placed on a semi-finished substrate;

[0055] Fig.16 It is a schematic structural diagram of a second embodiment of the present invention after placing a first flip chip and a second flip chip on a semi-finished substrate;

[0056] Fig.17 For Fig.15 A schematic structural diagram of the first flip chip after wire bonding;

[0057] Fig.18 For Fig.16 A schematic structural diagram of the first flip chip after wire bonding;

[0058] Fig.19 For Fig.17 A schematic diagram of the structure after the structure is encapsulated;

[0059] Fig. 20 For Fig.18 A schematic diagram of the structure after the structure is encapsulated;

[0060] Fig.21 For Fig.19 A schematic diagram of the structure after the first conductive column is ball-planted;

[0061] Fig. 22 For Fig. 20 A schematic diagram of the structure after the first conductive column is ball-planted;

[0062] Fig.23 For Fig.21 A schematic diagram of the structure after the heat dissipation structure is set;

[0063] Fig.24 For Fig. 22 A schematic diagram of the structure after the heat dissipation structure is set;

[0064] Reference numerals:

[0065] Semi-finished substrate 100, dielectric layer 110, first surface 111, second surface 112, cavity 113, first circuit layer 120, second circuit layer 130, conductive structure 140, insulating medium 141, third conductive pillar 142, conductive layer 143, first conductive pillar 150, third circuit layer 160, second conductive pillar 170, first flip chip 200, pin 210, packaging material 300, heat dissipation structure 400, second flip chip 500, ball planting 600, fourth conductive pillar 700, bonding wire 800. DETAILED DESCRIPTION

[0066] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0067] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0068] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0069] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0070] With the development and progress of electronic technology, electronic products are evolving towards being short, light and thin, and the functional requirements of electronic products are becoming increasingly powerful, which has promoted the packaging structure of electronic products to develop towards a highly integrated and miniaturized direction, and embedded packaging of components such as chips has emerged; at the same time, the application of electronic components is also developing towards high frequency, high speed and high power, resulting in a rapid increase in heat flux density per unit area. As we all know, with the increase in the operating environment temperature, the operating speed of electronic components decreases, and the loss increases. At the same time, the reliability of electronic products is relatively reduced when they are operated in a high temperature environment for a long time. Therefore, if the heat generated by high-frequency, high-speed and high-power electronic components cannot be dissipated in time, the performance and reliability of electronic products will be seriously affected. Therefore, under the general trend of high frequency, high speed and high power, how to reasonably optimize the heat dissipation performance of the packaging structure is an important topic at present.

[0071] To this end, the embodiment of the present invention proposes a high heat dissipation inverted packaging method and structure, which uses a heat dissipation structure to dissipate heat from the chip, so that the chip is directly packaged by the heat dissipation structure, so that the heat generated by the chip and the device during operation can be quickly taken away by the heat dissipation structure, greatly improving the heat dissipation performance of the packaging structure. According to the high heat dissipation inverted packaging method of the embodiment of the present invention, the manufacturing process is simple and the cost is low, which greatly improves the heat dissipation performance of the product, and the product has more superior reliability and stability.

[0072] The following is combined with Figure 1 To Attachment Fig.24 , the high heat dissipation inverted packaging method and structure of the embodiment of the present invention are described in detail.

[0073] On the one hand, if Figure 1 As shown, the high heat dissipation inverted packaging method according to an embodiment of the present invention includes the following steps:

[0074] Step S100: preparing a semi-finished substrate 100; the semi-finished substrate 100 comprises a dielectric layer 110, a first surface 111 of the dielectric layer 110 is provided with a first circuit layer 120, a second surface 112 of the dielectric layer 110 is provided with a second circuit layer 130, the first surface 111 is opposite to the second surface 112, the dielectric layer 110 is provided with a cavity 113 penetrating the dielectric layer 110, a conductive structure 140 is provided in the cavity 113, the conductive structure 140 is conductively connected to the first circuit layer 120, and a first conductive column 150 is provided on the surface of the second circuit layer 130;

[0075] Step S200: placing a first flip chip 200 on the conductive structure 140 in the cavity 113, and making the pins of the first flip chip 200 conductively connected to the second circuit layer 130;

[0076] Step S300: Covering the second surface 112 of the dielectric layer 110 with a packaging material 300 so that the packaging material 300 covers the first conductive pillar 150 and the first flip chip 200;

[0077] Step S400 : disposing a heat dissipation structure 400 on the surface of the first circuit layer 120 .

[0078] Specifically, Figure 2 As shown, in this example, the semi-finished substrate 100 includes a dielectric layer 110, a first surface 111 (eg, Figure 2 The lower surface shown in FIG. 1 is provided with a first circuit layer 120, and the second surface 112 of the dielectric layer 110 (as shown in FIG. 11) is provided with a first circuit layer 120. Figure 2 A second circuit layer 130 is provided on the upper surface shown in the figure, the dielectric layer 110 is provided with a cavity 113 penetrating the dielectric layer 110, a conductive structure 140 is provided in the cavity 113, the conductive structure 140 is conductively connected to the first circuit layer 120, and a first conductive column 150 is provided on the surface of the second circuit layer 130.

[0079] It should be noted that the specific number of the first conductive pillars 150 and the cavities 113 can be designed according to actual needs. The material of the dielectric layer 110 can be glass fiber, epoxy resin or BT (bismaleimide) with good strength and rigidity, or a mixture of the two.

[0080] It should be noted that the semi-finished substrate 100 can be designed as a substrate with different numbers of layers. When the semi-finished substrate 100 is a multi-layer board, a third circuit layer 160 and a second conductive column 170 are also provided inside the dielectric layer 110, and the third circuit layer 160 is conductively connected to the second circuit layer 130 through the second conductive column 170.

[0081] like Figure 2As shown, in some embodiments of the present invention, the conductive structure 140 includes an insulating medium 141, a third conductive pillar 142 and a conductive layer 143, wherein the insulating medium 141 is disposed in the cavity 113, the third conductive pillar 142 is disposed in the insulating medium 141, one end of the third conductive pillar 142 is conductively connected to the first circuit layer 120; the conductive layer 143 is disposed on the surface of the insulating medium 141 and conductively connected to the other end of the third conductive pillar 142, and the first flip chip 200 is disposed on the conductive layer 143. Specifically, the material of the insulating medium 141 can be the same as the material used in the dielectric layer 110; the number of the third conductive pillars 142 can be multiple, and when the number of the third conductive pillars 142 is multiple, the multiple third conductive pillars 142 are spaced apart in the insulating medium 141, the lower end of the third conductive pillar 142 is conductively connected to the first circuit layer 120, and the upper end of the third conductive pillar 142 is conductively connected to the conductive layer 143. The conductive layer 143 may be made of a conductive metal such as a copper layer. The first flip chip 200 is inverted on the conductive layer 143 , and the front side of the first flip chip 200 is conductively connected to the conductive layer 143 .

[0082] like Figure 3 As shown, when there is only one chip, that is, only one first flip chip 200, the first flip chip 200 is disposed on the conductive layer 143; Figure 4 As shown, when there are multiple chips, that is, in addition to the first flip chip 200, there are also several second flip chips 500 or components, the second flip chip 500 and the components are placed on the second circuit layer 130. It should be noted that the first flip chip 200 and the second flip chip 500 can be fixed using epoxy resin or DAF (DieAttach Film, an ultra-thin film adhesive used to connect semiconductor chips and packaging substrates, chips and chips in the semiconductor packaging process) or sintering materials.

[0083] like Figure 5 and Figure 6 As shown, in some embodiments of the present invention, after placing the first flip chip 200, the pins 210 of the first flip chip 200 are conductively connected to the second circuit layer 130 through bonding wires 800 by using technologies such as wire bonding. The bonding wires 800 may be gold wires or copper wires.

[0084] like Figure 7 and Figure 8 As shown, in some embodiments of the present invention, after the pins 210 of the first flip chip 200 are connected to the second circuit layer 130, the first flip chip 200 and the second flip chip 500 are packaged with a packaging material 300. The packaging material 300 covers the second surface 112 of the dielectric layer 110, and further covers the first conductive pillar 150 and the first flip chip 200.

[0085] like Fig. 9 and Fig.10 As shown, in some embodiments of the present invention, when the packaging material 300 is thick, the packaging material 300 needs to be ground so that the surface of the first conductive column 150 is flush with the surface of the packaging material 300, so as to facilitate the subsequent connection of the first conductive column 150 with external devices.

[0086] Furthermore, if Fig. 9 and Fig.10 As shown, in some embodiments of the present invention, it is also necessary to plant a ball 600 on the surface of the first conductive pillar 150 to facilitate the connection between the first conductive pillar 150 and external devices.

[0087] Furthermore, if Fig.11 and Fig.12 As shown, in some embodiments of the present invention, after the chip is packaged and connected, a heat dissipation structure 400 needs to be provided on the surface of the first circuit layer 120. The heat dissipation structure 400 may include a plurality of heat dissipation columns or heat sinks. The heat generated by the first flip chip 200 during operation can reach the heat dissipation structure 400 through the conductive structure 140, and then dissipate the heat through the heat dissipation structure 400.

[0088] According to the high heat dissipation inverted packaging method of the embodiment of the present invention, the heat dissipation structure 400 is used to dissipate heat from the chip, so that the chip is directly packaged by the heat dissipation structure 400, so that the heat generated by the chip and the device during operation can be quickly taken away by the heat dissipation structure 400, greatly improving the heat dissipation performance of the package. According to the high heat dissipation inverted packaging method of the embodiment of the present invention, the manufacturing process is simple and the cost is low, which greatly improves the heat dissipation performance of the product, and the product has more superior reliability and stability.

[0089] On the other hand, Fig.13 As shown, the present invention also proposes another high heat dissipation inverted packaging method, which includes the following steps:

[0090] Step S500: preparing a semi-finished substrate 100; the semi-finished substrate 100 includes a dielectric layer 110, a first surface 111 of the dielectric layer 110 is provided with a first circuit layer 120, a second surface 112 of the dielectric layer 110 is provided with a second circuit layer 130, the first surface 111 is opposite to the second surface 112, a first conductive column 150 is provided on the surface of the second circuit layer 130, a fourth conductive column 700 is provided in the dielectric layer 110, and the fourth conductive column 700 is conductively connected to the first circuit layer 120 and the second circuit layer 130 respectively;

[0091] Step S600: placing the first flip chip 200 on the surface of the second circuit layer 130, and making the pins 210 of the first flip chip 200 conductively connected to the second circuit layer 130;

[0092] Step S700: Covering the second surface 112 of the dielectric layer 110 with the packaging material 300 so that the packaging material 300 covers the first conductive pillar 150 and the first flip chip 200;

[0093] Step S800 : disposing a heat dissipation structure 400 on the surface of the first circuit layer 120 .

[0094] Specifically, Fig.14 As shown, in this example, the semi-finished substrate 100 includes a dielectric layer 110, a first surface 111 (eg, Fig.14 The lower surface shown in FIG. 1 is provided with a first circuit layer 120, and the second surface 112 of the dielectric layer 110 (as shown in FIG. 11) is provided with a first circuit layer 120. Fig.14 A second circuit layer 130 is disposed on the upper surface shown in the figure, a first conductive column 150 is disposed on the surface of the second circuit layer 130, a fourth conductive column 700 is disposed in the dielectric layer 110, and the fourth conductive column 700 is conductively connected to the first circuit layer 120 and the second circuit layer 130 respectively.

[0095] It should be noted that the specific number of the first conductive pillars 150 and the fourth conductive pillars 700 can be designed according to actual needs. The material of the dielectric layer 110 can be glass fiber, epoxy resin or BT (bismaleimide) with good strength and rigidity, or a mixture of the two.

[0096] It should be noted that the semi-finished substrate 100 can be designed as a substrate with different numbers of layers, such as Fig.14 As shown, when the semi-finished substrate 100 is a multi-layer board, a third circuit layer 160 and a second conductive column 170 are further disposed inside the dielectric layer 110 , and the third circuit layer 160 is conductively connected to the second circuit layer 130 through the second conductive column 170 .

[0097] like Fig.15 and Fig.16As shown, the chip can be one or more. When there is only one chip, that is, there is only one first flip chip 200, the first flip chip 200 is arranged on the second circuit layer 130; when there are multiple chips, that is, in addition to the first flip chip 200, it also includes a plurality of second flip chips 500 or components, the first flip chip 200, the second flip chip 500 and the components are placed on the second circuit layer 130. It should be noted that the first flip chip 200 and the second flip chip 500 can be fixed using epoxy resin or DAF (Die Attach Film, an ultra-thin film adhesive used to connect semiconductor chips and packaging substrates, chips and chips in the semiconductor packaging process) or sintering materials.

[0098] like Fig.17 and Fig.18 As shown, in some embodiments of the present invention, after placing the first flip chip 200, the pins 210 of the first flip chip 200 are conductively connected to the second circuit layer 130 through bonding wires 800 by using technologies such as wire bonding. The bonding wires 800 may be gold wires or copper wires.

[0099] like Fig.19 and Fig. 20 As shown, in some embodiments of the present invention, after the pins 210 of the first flip chip 200 are connected to the second circuit layer 130, the first flip chip 200 and the second flip chip 500 are packaged with a packaging material 300. The packaging material 300 covers the second surface 112 of the dielectric layer 110, and further covers the first conductive pillar 150 and the first flip chip 200.

[0100] like Fig.21 and Fig. 22 As shown, in some embodiments of the present invention, when the packaging material 300 is thick, the packaging material 300 needs to be ground so that the surface of the first conductive column 150 is flush with the surface of the packaging material 300, so as to facilitate the subsequent connection of the first conductive column 150 with external devices.

[0101] Furthermore, if Fig.21 and Fig. 22 As shown, in some embodiments of the present invention, it is also necessary to plant a ball 600 on the surface of the first conductive pillar 150 to facilitate the connection between the first conductive pillar 150 and external devices.

[0102] Furthermore, if Fig.23 and Fig.24As shown, in some embodiments of the present invention, after the chip is packaged and connected, a heat dissipation structure 400 needs to be provided on the surface of the first circuit layer 120. The heat dissipation structure 400 may include a plurality of heat dissipation columns or heat sinks. The heat generated by the first flip chip 200 during operation can reach the heat dissipation structure 400 through the conductive structure 140, and then dissipate the heat through the heat dissipation structure 400.

[0103] According to the high heat dissipation inverted packaging method of the embodiment of the present invention, there is no need to set a cavity, and the heat dissipation structure 400 is used to dissipate heat from the chip, so that the chip is directly packaged by the heat dissipation structure 400, so that the heat generated by the chip and the device during operation can be quickly taken away by the heat dissipation structure 400, greatly improving the heat dissipation performance of the package. According to the high heat dissipation inverted packaging method of the embodiment of the present invention, the manufacturing process is simple and the cost is low, which greatly improves the heat dissipation performance of the product, and the product has more superior reliability and stability.

[0104] On the other hand, the embodiment of the present invention also proposes a high heat dissipation inverted packaging structure, such as Figure 2-Figure 12 As shown, the structure includes:

[0105] A semi-finished substrate 100, comprising a dielectric layer 110, a first surface 111 of the dielectric layer 110 being provided with a first circuit layer 120, a second surface 112 of the dielectric layer 110 being provided with a second circuit layer 130, the first surface 111 being opposite to the second surface 112, the dielectric layer 110 being provided with a cavity 113 penetrating the dielectric layer 110, a conductive structure 140 being provided in the cavity 113, the conductive structure 140 being conductively connected to the first circuit layer 120, and a first conductive pillar 150 being provided on the surface of the second circuit layer 130;

[0106] The first flip chip 200 is disposed on the conductive structure 140 in the cavity 113, and the pins 210 of the first flip chip 200 are conductively connected to the second circuit layer 130;

[0107] The packaging material 300 covers the second surface 112 of the dielectric layer 110 , and the packaging material 300 covers the first conductive pillar 150 and the first flip chip 200 ;

[0108] The heat dissipation structure 400 is disposed on the surface of the first circuit layer 120 .

[0109] It should be noted that the contents of the above method embodiments are all applicable to this embodiment, the functions specifically implemented by this embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0110] On the other hand, the embodiment of the present invention also proposes a high heat dissipation inverted packaging structure, such as Figure 14-Figure 24As shown, the structure includes:

[0111] A semi-finished substrate 100, comprising a dielectric layer 110, a first surface 111 of the dielectric layer 110 being provided with a first circuit layer 120, a second surface 112 of the dielectric layer 110 being provided with a second circuit layer 130, the first surface 111 being opposite to the second surface 112, a surface of the second circuit layer 130 being provided with a first conductive pillar 150, a fourth conductive pillar 700 being provided in the dielectric layer 110, and the fourth conductive pillar 700 being conductively connected to the first circuit layer 120 and the second circuit layer 130 respectively;

[0112] The first flip chip 200 is disposed on the surface of the second circuit layer 130 , and the pins 210 of the first flip chip 200 are conductively connected to the second circuit layer 130 ;

[0113] The packaging material 300 covers the second surface 112 of the dielectric layer 110 , and the packaging material 300 covers the first conductive pillar 150 and the first flip chip 200 ;

[0114] The heat dissipation structure 400 is disposed on the surface of the first circuit layer 120 .

[0115] It should be noted that the contents of the above method embodiments are all applicable to this embodiment, the functions specifically implemented by this embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0116] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0117] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A high heat dissipation inverted packaging method, characterized in that: The following steps are involved: Prepare a semi-finished substrate; the semi-finished substrate comprises a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, the dielectric layer is provided with a cavity penetrating the dielectric layer, a conductive structure is provided in the cavity, the conductive structure is conductively connected to the first circuit layer, and a first conductive column is provided on the surface of the second circuit layer; Placing a first flip chip on the conductive structure in the cavity, and conductively connecting the pins of the first flip chip to the second circuit layer; Covering the second surface of the dielectric layer with packaging material, so that the packaging material covers the first conductive pillar and the first flip chip; A heat dissipation structure is arranged on the surface of the first circuit layer.

2. The high heat dissipation inverted packaging method according to claim 1, characterized in that: A third circuit layer and a second conductive column are further disposed inside the dielectric layer, and the third circuit layer is conductively connected to the second circuit layer through the second conductive column.

3. The high heat dissipation inverted packaging method according to claim 1, characterized in that: The conductive structure comprises: An insulating medium is disposed in the cavity; A third conductive column is disposed in the insulating medium, and one end of the third conductive column is conductively connected to the first circuit layer; A conductive layer is disposed on the surface of the insulating medium and is conductively connected to the other end of the third conductive column. The first flip chip is disposed on the conductive layer.

4. The high heat dissipation inverted packaging method according to claim 1, characterized in that: The step of placing a first flip chip on the conductive structure in the cavity and conductively connecting the pins of the first flip chip to the second circuit layer also includes: A plurality of second flip chips or components are placed on the second circuit layer.

5. The high heat dissipation inverted packaging method according to claim 1, characterized in that: The method further comprises the following steps: A ball is planted on the surface of the first conductive column.

6. A high heat dissipation inverted packaging method, characterized in that: The following steps are involved: Prepare a semi-finished substrate; the semi-finished substrate comprises a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, a surface of the second circuit layer is provided with a first conductive column, a fourth conductive column is provided in the dielectric layer, and the fourth conductive column is conductively connected to the first circuit layer and the second circuit layer respectively; Placing a first flip chip on the surface of the second circuit layer, and electrically connecting the pins of the first flip chip to the second circuit layer; Covering the second surface of the dielectric layer with packaging material, so that the packaging material covers the first conductive pillar and the first flip chip; A heat dissipation structure is arranged on the surface of the first circuit layer.

7. The high heat dissipation inverted packaging method according to claim 6, characterized in that: A third circuit layer and a second conductive column are further disposed inside the dielectric layer, and the third circuit layer is conductively connected to the second circuit layer through the second conductive column.

8. The high heat dissipation inverted packaging method according to claim 6, characterized in that: The method further comprises the following steps: A ball is planted on the surface of the first conductive column.

9. A high heat dissipation inverted packaging structure, characterized in that: include: A semi-finished substrate, the semi-finished substrate comprising a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, the dielectric layer is provided with a cavity penetrating the dielectric layer, a conductive structure is provided in the cavity, the conductive structure is conductively connected to the first circuit layer, and a first conductive column is provided on the surface of the second circuit layer; A first flip chip is disposed on the conductive structure in the cavity, and a pin of the first flip chip is conductively connected to the second circuit layer; A packaging material is covered on the second surface of the dielectric layer, and the packaging material covers the first conductive pillar and the first flip chip; The heat dissipation structure is arranged on the surface of the first circuit layer.

10. A high heat dissipation inverted packaging structure, characterized in that: include: A semi-finished substrate, the semi-finished substrate comprising a dielectric layer, a first surface of the dielectric layer is provided with a first circuit layer, a second surface of the dielectric layer is provided with a second circuit layer, the first surface is opposite to the second surface, a surface of the second circuit layer is provided with a first conductive column, a fourth conductive column is provided in the dielectric layer, and the fourth conductive column is conductively connected to the first circuit layer and the second circuit layer respectively; A first flip chip is disposed on the surface of the second circuit layer, and a pin of the first flip chip is conductively connected to the second circuit layer; A packaging material is covered on the second surface of the dielectric layer, and the packaging material covers the first conductive pillar and the first flip chip; The heat dissipation structure is arranged on the surface of the first circuit layer.

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