Wafer testing of power transistor current characteristics

Abstract

A wafer test of a power transistor wafer test of a power transistor current characteristic is performed by using a sense transistor constructed using the same epitaxial stack as used to construct the power transistor. A current characteristic of the sense transistor is then measured, and a current characteristic of the power transistor may be determined from the measurement. Further, the sense transistor is pre-regulated by alternately turning on and off the sense transistor for a plurality of cycles while allowing the source terminal of the power transistor to float prior to the measurement. This simulates the operating conditions of the power transistor, allowing the current characteristics of the power transistor that may be in operation to be measured.

Description

Technical Field

[0001] The present application relates to the field of wafer testing, and in particular, to current testing in power transistors formed on a wafer. Background Art

[0002] Integrated circuits are typically manufactured on wafers, where each integrated circuit is manufactured within a specific area (a specific "die") of the wafer. For example, a typical wafer is composed of crystalline silicon. Integrated circuits are manufactured through a variety of semiconductor process flows, including, for example, epitaxial layer deposition, photolithographic patterning, etching, planarization, alignment, etc. During the manufacturing process, wafers move from one machine to another, typically undergoing hundreds of different semiconductor process flows. After the integrated circuits are fully manufactured, the wafers are diced so that each integrated circuit is separated into its own die.

[0003] The testing of each chip can be performed before or after the integrated circuit is cut. When the test is performed before cutting, the test is performed directly on the wafer, which is called "wafer testing". Wafer testing is performed by applying signals and / or voltages to specific points in the integrated circuit using probes and by receiving the resulting signals and / or voltages from specific points in the integrated circuit. Integrated circuits generally have small feature sizes. Therefore, wafer probes are generally very fine so that they can make appropriate contact with different points in the integrated circuit. In fact, the probes are often properly called "probes" or "needles". In any case, chips that fail the test can be identified and discarded. Chips that pass the test can be packaged later.

[0004] Integrated circuits often include transistors, whose function is to electronically switch, regulate or control the current in a circuit portion. One type of transistor is a field effect transistor, in which a voltage is applied to a gate terminal to turn the transistor on and off. A semiconductor channel region is disposed between a drain terminal and a source terminal. When the transistor is turned on, current flows through the semiconductor channel region between the source terminal and the drain terminal. When the transistor is turned off, less current or no current flows through the semiconductor channel region between the source terminal and the drain terminal. A gate terminal is disposed over the semiconductor channel region between the source terminal and the drain terminal. The voltage on the gate terminal creates a field that affects whether the semiconductor channel region conducts current, hence the name "field effect transistor."

[0005] However, there are other types of transistors. In each transistor, when the transistor is turned on by applying a sufficient voltage to the control node, current flows from the input node to the output node through the channel. For example, in a field effect transistor, the control node will be the gate terminal, the input node will be one of the source terminal or the drain terminal, and the output node will be the other of the source terminal or the drain terminal.

[0006] Typical transistors are used for amplification and switching purposes in electronic circuits. Power transistors, on the other hand, are used to carry larger amounts of current, have higher voltage ratings, and may be more typically used in power supplies, battery charging, etc. Power transistors can typically operate at currents from greater than 1 amp to a hundred amps or even more. Power transistors can carry power from greater than 1 watt to hundreds of watts or even more.

[0007] The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is merely provided to illustrate one example technology area where some embodiments described herein may be practiced. Summary of the invention

[0008] The description is provided to introduce some concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0009] The embodiments described herein relate to wafer testing of power transistors for power transistor current characteristics. Power transistors are capable of transmitting large amounts of power. Therefore, wafer testing of power transistors for current characteristics is difficult because the fine probes themselves are not capable of carrying large amounts of power. According to the principles described herein, wafer testing of power transistors is performed by using a sensing transistor that is constructed using the same epitaxial stack as used to construct the power transistor. The current characteristics of the sensing transistor are then measured, and the current characteristics of the power transistor can be determined based on the measurement.

[0010] In addition, prior to measurement, the sense transistor is pre-conditioned by alternately turning the sense transistor on and off for multiple cycles while allowing the source terminal of the power transistor to float. This simulates the operating conditions of the power transistor, allowing the current characteristics of the power transistor to be measured as it might be in operation. This test is performed while the power transistor is still on the wafer, before the wafer is cut into individual chips. In one embodiment, the wafer is also heated to more closely match the expected operating temperature that the power transistor will experience in operation. This even further simulates the operating conditions of the power transistor, further improving the measurement of the current characteristics of the power transistor.

[0011] Additional features and advantages will be set forth in the following description, and in part will be apparent from the description, or may be learned through practice of the teachings herein. The features and advantages of the present invention may be realized and obtained through the tools and combinations particularly pointed out in the appended claims. The features of the present invention will become more apparent from the following description and the appended claims, or may be understood through practice of the present invention as described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to describe the manner in which the advantages and features of the embodiments described herein can be obtained, a more particular description of the concepts briefly described above will be provided with reference to specific embodiments thereof that are illustrated in the accompanying drawings. Understanding that these drawings depict only exemplary embodiments and are therefore not to be considered limiting of the scope of the invention, certain embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0013] Figure 1 A wafer testing environment is shown in which the principles described herein may be implemented and includes a wafer probe apparatus that uses a probe to contact and test a wafer located on a wafer chuck;

[0014] Figure 2 A circuit including a power transistor and a sense transistor according to principles described herein is shown, wherein a current characteristic of the sense transistor is measured to determine a current characteristic of the power transistor;

[0015] Figure 3 A flow chart of a method for determining current characteristics of a power transistor while the power transistor is still on a wafer according to the principles described herein is shown, and the method can be used in Figure 1 Applied in wafer testing environments Figure 2 Circuit;

[0016] Figure 4 shows a signal graph illustrating a simulation of two waveforms representing a signal encountered by a sense transistor, the solid waveform representing a simulated drain-to-source voltage of the sense transistor and the dashed waveform representing a simulated current flowing through the sense transistor;

[0017] Figure 5A The actions of the method for turning on a sense transistor are shown;

[0018] Figure 5B The actions of the method for turning off the sense transistor are shown;

[0019] Figure 6 An environment in which a drain voltage applying circuit according to a first example applies a drain voltage to a sensing transistor via a drain probe is shown, wherein the drain voltage applying circuit uses a fixed high voltage source; and

[0020] Figure 7 An environment in which a drain voltage applying circuit according to a second example applies a drain voltage to a sensing transistor via a drain probe is shown, wherein the drain voltage applying circuit uses a variable or selective high voltage source. DETAILED DESCRIPTION

[0021] The embodiments described herein relate to wafer testing of power transistors for power transistor current characteristics. Power transistors are capable of transmitting large amounts of power. Therefore, wafer testing of power transistors for current characteristics is difficult because the fine probes themselves are not capable of carrying large amounts of power. According to the principles described herein, wafer testing of power transistors is performed by using a sensing transistor that is constructed using the same epitaxial stack as used to construct the power transistor. The current characteristics of the sensing transistor are then measured, and the current characteristics of the power transistor can be determined based on the measurement.

[0022] In addition, prior to measurement, the sense transistor is pre-conditioned by alternately turning the sense transistor on and off for multiple cycles while allowing the source terminal of the power transistor to float. This simulates the operating conditions of the power transistor, allowing the current characteristics of the power transistor to be measured as it might be in operation. This test is performed while the power transistor is still on the wafer, before the wafer is cut into individual chips. In one embodiment, the wafer is also heated to more closely match the expected operating temperature that the power transistor will experience in operation. This even further simulates the operating conditions of the power transistor, further improving the measurement of the current characteristics of the power transistor.

[0023] Figure 1 1 shows a wafer test environment 100 in which the principles described herein may be implemented. However, the wafer test environment 100 is only an example of a wafer test environment in which the principles described herein may be implemented. The wafer test environment 100 includes a wafer 101. The wafer 101 includes a plurality of chips formed thereon, but Figure 1 Only chips 102A, 102B, 102C, and 102D are shown. The ellipses indicate that there can be any number of chips on wafer 101, limited only by the size of the chips and the size of the wafer. Each chip includes a corresponding circuit formed by applying a semiconductor process flow to the wafer. The principles described herein are not limited to those semiconductor process flows. After the semiconductor process is completed and the circuits are fully formed, the wafer is cut to thereby physically separate each chip. However, Figure 1 Shown is a wafer prior to dicing. "Wafer testing" refers to testing of circuits formed on a wafer, and wherein the testing is performed prior to dicing the wafer.

[0024] The purpose of wafer test environment 100 is to apply probes to circuits formed on wafer 101 to verify the operation of the circuits before dicing the wafers. Figure 1 In the embodiment of the present invention, a wafer probe contacts chip 102A to test whether the circuit formed on chip 102A operates correctly. According to the principles described herein, chip 102A includes a power transistor. In this specification and claims, a "power transistor" is any transistor that can transmit more than one watt of power when turned on.

[0025] Wafer 101 is supported by wafer chuck 110, which may be, for example, a thermal chuck configured to heat wafer 101 to a specific temperature during wafer testing. In one example, wafer chuck 110 heats wafer 101 to an approximate temperature (e.g., 100 degrees Celsius) that a chip under test may encounter during operation. The principles described herein are not limited to a specific structure of wafer chuck 110, nor to whether the wafer chuck heats wafer 101.

[0026] The wafer test environment 100 also includes a wafer probe device 120, which includes a moving portion 121 and a position adjustment portion 122, the position adjustment portion 122 allowing the moving portion 121 to move in three dimensions. The probe card 130 extends from the moving portion 121 and has a probe group 131 extending from the probe card 130. The probe group 131 can be positioned so that each of the one or more probes contacts a specific respective point on the wafer 101. The principles described herein are not limited to the specific structure of the wafer probe device 120. It is sufficient to say that the probes of the probe group 131 are very fine (hence the term "probe" or "needle probe") and therefore cannot carry a large amount of power.

[0027] exist Figure 1 , probe set 131 is in contact with chip 102A. For the purpose of discussion, chip 102A will be described as forming a power transistor and a sense transistor, wherein the current characteristics of the sense transistor are measured to determine the current characteristics of the power transistor. According to the principles described herein, although each probe in probe set 131 is too fine to carry a large amount of electrical power, the current characteristics of the power transistor can be determined using probe set 131. According to one aspect described herein, probe set 131 measures the current characteristics of the sense transistor so that the current characteristics of the power transistor can then be measured based on the current characteristics of the sense transistor.

[0028] Figure 2 A circuit 200 is shown that includes a power transistor 201 and a sense transistor 202 according to the principles described herein, and wherein a current characteristic of the sense transistor 202 is measured to determine a current characteristic of the power transistor 201. As an example, the circuit 200 may be Figure 1 The sensing transistor 202 is fabricated on the chip 102A of FIG. 1 and can be tested using the wafer probe apparatus 120. The active region of the sensing transistor 202 can be constructed using at least a portion of the same epitaxial stack as the active region of the power transistor 201. Therefore, the electrical behavior of the sensing transistor 202 can closely reflect the electrical behavior of the power transistor 201 in a proportional manner.

[0029] As an example, power transistor 201 and sense transistor 202 may have a gallium nitride (GaN) channel layer formed from the same epitaxial layer initially epitaxially deposited on chip 102A. In this case, power transistor 201 and sense transistor 202 may have an aluminum gallium nitride (AlGaN) barrier layer formed from the same epitaxial layer initially epitaxially deposited on chip 102A over the GaN layer.

[0030] That is, the current flow area of ​​the current sensing transistor 202 can be much smaller than the current flow area of ​​the power transistor 201. In this specification and claims, the "current flow area" of a transistor is the cross-sectional area through which the current flows when the transistor is turned on. For example, assuming that the depth range of the current flow is constant, the current flow area will be proportional to the current flow width (e.g., gate width).

[0031] In one embodiment, current sensing transistor 202 is small enough that power transistor 201 has a current flow area that is at least 100 times (or even at least 1000 times) greater than the current flow area of ​​sensing transistor 202. In one embodiment, the current flow area of ​​power transistor 201 is approximately 7000 times greater than the current flow area of ​​sensing transistor 202. Thus, sensing transistor 202 can be very tiny but otherwise proportionally reflects the electrical characteristics of power transistor 201. As an example, the saturation current of power transistor 201 can be determined by measuring the saturation current of sensing transistor 202 and multiplying the measured saturation current by the size ratio (e.g., 7000).

[0032] Furthermore, the drain terminal 211 of the power transistor 201 is connected to the drain terminal 221 of the power transistor 202, and the gate terminal 212 of the power transistor 201 is connected to the drain terminal 222 of the sense transistor 202. Furthermore, during wafer testing of the circuit 200, the source terminal 213 of the power transistor 201 is allowed to float, but a voltage (e.g., ground) is applied to the source terminal 223 of the sense transistor 202. Thus, the same terminals used to operate the power transistor 201 can be used to test the sense transistor 202. The only difference is that instead of applying a source voltage to the source terminal 213 of the power transistor 201 as occurs during operation, a source voltage is applied to the source terminal 223 of the sense transistor 202 because the source terminal 213 of the power transistor 201 is allowed to float.

[0033] Figure 3A flow chart of a method 300 for determining current characteristics of a power transistor while the power transistor is still on a wafer according to the principles described herein is shown. Method 300 first includes applying probes to the drain terminal, source terminal, and gate terminal of a sensing transistor. For example, a first probe (also referred to herein as a "drain" probe) is applied to the drain terminal of the sensing transistor (action 301), a second probe (referred to herein as a "source probe") is applied to the source terminal of the sensing transistor (action 302), and a third probe (referred to herein as a "gate probe") is applied to the gate terminal of the sensing transistor (action 303). These actions 301, 302, and 303 are shown in parallel, merely to indicate that the principles described herein are not limited to the timing of applying the probes.

[0034] If Figure 2 The circuit 200 performs Figure 3 In the method 300 of FIG. 2 , the application of the drain probe (act 301 ) may be accomplished by applying the drain probe to the drain terminal 221 of the sense transistor 202. Furthermore, the application of the source probe (act 302 ) may be accomplished by applying the source probe to the source terminal 223 of the sense transistor 202. Furthermore, the application of the gate probe (act 303 ) may be accomplished by applying the gate probe to the gate terminal 222 of the sense transistor 202. If the circuit 200 is located at Figure 1 If the chip 102A is formed on the wafer 101, the application of the probes can be achieved by moving the probe group 131 in a three-dimensional space using the position adjustment part 122 so that the appropriate probe contacts the appropriate terminal of the sensing transistor formed on the chip 102A.

[0035] After the probes are properly placed (in actions 301, 302, and 303), the sense transistor is then pre-conditioned (action 310). This is performed by alternately turning the sense transistor on (action 311) and off (action 312) through multiple switching cycles while allowing the source terminal of the power transistor to float. Arrows 313A and 313B represent the repeated turning on and off of the sense transistor. For example, in Figure 2 In the embodiment of the present invention, the sensing transistor 202 is pre-conditioned by repeatedly turning the sensing transistor 202 on and off.

[0036] Each switching cycle can be performed relatively quickly, perhaps even at a rate greater than 10,000 times per second. Therefore, if the pre-regulation involves 100 switching cycles, the pre-regulation only takes a fraction of a second. In one embodiment, the number of switching cycles is at least 20 cycles. However, 100 switching cycles will provide a larger amount of pre-regulation. The cycling of the sense transistor (e.g., sense transistor 202) does help the sense transistor to exhibit current performance similar to that of the power transistor (but scaled down), just as the power transistor (e.g., power transistor 201) will experience during actual operating conditions of the power transistor. Specifically, the sense transistor 202 is forced to have charge capture similar to that which the power transistor 201 will encounter during normal operating conditions. This charge capture does affect the current behavior of the transistor. Therefore, forcing the sense transistor 202 to encounter charge capture will cause the sense transistor 202 to become an accurate scaled-down substitute for determining the current characteristics of the power transistor 201 during normal operation.

[0037] In the context of pre-conditioning, the terms “on gate voltage” and “off gate voltage” will be used. The “on gate voltage” can be a predetermined voltage (e.g., six volts) that, if applied long enough, will cause the sense transistor to form a conductive path from the drain terminal to the source terminal. This is in contrast to the “off gate voltage,” which is a lower predetermined voltage (e.g., zero volts) that, if applied long enough, will cause the sense transistor to disconnect from the drain terminal to the source terminal. Cycling of the sense transistor is accomplished by alternating the application of the on gate voltage and the off gate voltage very rapidly via the gate probe. For example, in Figure 2 In the embodiment of the present invention, the on-gate voltage and the off-gate voltage are rapidly and alternately applied to the gate terminal 222 of the sensing transistor via a gate probe.

[0038] However, it takes some time for the sensing transistor to switch on and off. Figure 2In the context of, when the sense transistor 202 is turned on and off quickly, turning on the sense transistor 202 will cause the resistance between the drain terminal 221 and the source terminal 223 to decrease at a certain rate, thereby causing the current flowing through the sense transistor 202 to increase at a certain rate. Similarly, when the sense transistor 202 is turned on and off quickly, turning off the sense transistor 202 will cause the resistance between the drain terminal 221 and the source terminal 223 to increase at a certain rate, thereby causing the current flowing through the sense transistor 202 to decrease at a certain rate. Therefore, during the pre-regulation stage, whether the sense transistor 202 is turned on or off, there is always some current passing through the sense transistor 202, at least when the switching cycles occur very quickly. This rapid turning on and off of the sense transistor 202 causes charge capture to occur in the sense transistor 202, simulating the charge capture that will occur in the power transistor 201 during normal operation. Therefore, in Figure 2 In the context of , pre-conditioning of the sense transistor 202 will cause the sense transistor 202 to have similar electrical characteristics (but on a smaller scale) as the power transistor 201 will experience in subsequent operation.

[0039] Figure 4 A signal diagram 400 showing two waveform simulations is shown. The solid waveform represents the simulated drain-to-source voltage of the sensing transistor. However, the dashed waveform represents the simulated current flowing through the sensing transistor. As an example, the simulated current can be Figure 2 The current I 电流_感测 . The time frames of signal graph 400 are marked from time 1.86ms to time 2.16ms. Time frame 401 corresponds to the time when pre-regulation occurs. Time frame 401 shows the last twenty or so switching cycles of the pre-regulation phase of the sensing transistor. When the sensing transistor is turned on, the drain to source voltage drops and the current increases. However, since the on time is not long, the increase in current is small. When the sensing transistor is turned off, the drain to source voltage increases and the current decreases. However, since the off time is not long, the decrease in current is small. However, during the pre-regulation process, some current flows through the sensing transistor. Since there is current when the sensing transistor switches, this is a hard switch, which can cause charge capture in the sensing transistor.

[0040] In addition to the terms “on-gate voltage” and “off-gate voltage”, the terms “on-drain voltage” and “off-drain voltage” will also be used herein. The “on-drain voltage” is the voltage applied to the drain terminal of the sense transistor when the sense transistor is turned on, and the “off-drain voltage” is the voltage applied to the drain terminal of the sense transistor when the sense transistor is turned off. Similarly, the “on-source voltage” is the voltage applied to the source terminal of the sense transistor when the sense transistor is turned on, and the “off-source voltage” is the voltage applied to the source terminal of the sense transistor when the sense transistor is turned off. However, in one embodiment, the on-source voltage and the off-source voltage are the same and may be grounded.

[0041] Therefore, reference Figure 2 , the voltage applied to the source terminal 223 of the sense transistor 202 by the source probe can simply be grounded. In this case, the reference Figure 4 , the off-drain voltage is about 400 volts because when the sense transistor is off, the drain-to-source voltage appears to be about 400 volts. On the other hand, when the sense transistor is on, the on-drain voltage is close to zero (low single digit volts). Figure 4 , when the sense transistor is turned on, the drain-to-source voltage appears to be substantially zero volts. Thus, in the pre-regulation phase 401, the drain-to-source voltage oscillates as the sense transistor is turned on and off.

[0042] Figure 5A 1 shows a flow chart of a method 500A for turning on a sense transistor. The method 500A includes applying a gate-on voltage to the gate terminal of the sense transistor via a gate probe (action 501A), while simultaneously applying a drain-on voltage to the drain terminal of the sense transistor via a drain probe (action 502A), and simultaneously applying a source-on voltage to the source terminal of the sense transistor via a source probe (action 503A). Similarly, Figure 5B A flow chart of a method 500B for turning off a sense transistor is shown. The method 500B includes applying a turn-off gate voltage to the gate terminal of the sense transistor via a gate probe (action 501B), while applying a turn-off drain voltage to the drain terminal of the sense transistor via a drain probe (action 502B), and simultaneously applying a turn-off source voltage to the source terminal of the sense transistor via a source probe (action 503B). As previously described, the turn-on source voltage and the turn-off source voltage can be the same and can be grounded. In addition, the turn-on gate voltage can be predetermined and is the voltage at which the sense transistor is designed to be turned on, and the turn-off gate voltage can also be predetermined and is the voltage at which the sense transistor is designed to be turned off.

[0043] Return to Figure 3In the method 300, after pre-conditioning the sense transistor (act 310), the sense transistor is turned on and an electrical characteristic of the sense transistor is measured (act 320). The measurement may include measuring one or both of: 1) a current flowing from a drain terminal of the sense transistor to a source terminal of the sense transistor through the sense transistor when the current increases, and 2) a drain-to-source voltage between the drain terminal of the sense transistor and the source terminal of the sense transistor when the drain-to-source voltage increases.

[0044] For example, in Figure 4 In the example of FIG. 4 , during time frame 402, the sense transistor is turned on and allowed to remain on for a longer period of time, which causes the current through the sense transistor to increase. The current flowing through the sense transistor is allowed to increase so that various characteristics of the current can be determined. For example, the following current characteristics can be determined: the current when the current exits the linear region by a certain amount, or the saturation current. These characteristics can also be observed by measuring the drain to source voltage. For example, when the current leaves the linear region, the drain to source voltage can begin to increase, and can increase rapidly when the current enters saturation. Alternatively or additionally, the current characteristics can be determined in the form of current slope versus time.

[0045] refer to Figure 4 , the on-drain voltage and the off-drain voltage depend on whether the transistor is on or off. In one embodiment, the on-drain voltage and the off-drain voltage are applied using a circuit connected to a drain probe. Figure 6 An environment 600 is shown in which a drain voltage application circuit 610 applies a drain voltage to a drain terminal 621 of a sense transistor 602 via a drain probe 611. The sense transistor 602 may be, for example, Figure 2 The drain probe 611 is symbolically represented as a circle and may be, for example Figure 1 As an example, the drain voltage applying circuit 610 may be located at Figure 2 The wafer probe apparatus 120 is within the moving portion 121 of the wafer probe apparatus 120. Although not shown, a gate probe may be applied to the gate terminal 622 of the sense transistor 602 for applying a gate-on voltage and a gate-off voltage, and a source probe may be applied to the source terminal 623 of the sense transistor 602 for applying a source-on voltage (e.g., ground) and a source-off voltage (e.g., also ground).

[0046] The drain voltage applying circuit 610 includes a resistor 612 connected in series between a first voltage source 613 and a drain probe 611. In addition, an inductor 614 is coupled in series between a second voltage source 615 and the drain probe 611. A first diode 616 is connected in series between the inductor 614 and the drain probe 611 and has a forward direction from the inductor 614 to the drain probe 611. A second diode 617 is connected between both ends of the inductor 614 and has a forward direction toward the second voltage source 615. The first voltage source 613 provides a higher voltage than the second voltage source 615. As an example, the first voltage source 613 can provide a relatively fixed voltage, such as 400 volts, while the second voltage source 615 can provide a relatively fixed voltage of 6 volts.

[0047] When the sensing transistor 602 is turned on, current flows from the first voltage source 613 through the resistor 612 and through the transistor 602. The resistor 612 has a high resistance value so that even though the first voltage source 613 provides a high voltage, the voltage at the drain probe 611 is low enough so that the diode 616 is forward biased, thereby allowing current to flow from the second voltage source 615, through the inductor 614, through the diode 616 and through the transistor 602. Therefore, when the sensing transistor 602 is turned on, current flows from the first voltage source 613 through the resistor 612 and from the second voltage source 615 through the inductor 614 and the diode 616 and through the sensing transistor.

[0048] In one embodiment, resistor 612 is large enough so that most of the current flowing through sense transistor 602 comes from second voltage source 615 through inductor 614 and diode 616. In this case, the amount of current through sense transistor 602 (when sense transistor 602 is turned on) can be approximated by measuring the amount of current through inductor 614. In any case, when sense transistor 602 is turned on, the on-drain voltage is quite low (e.g., single digit volts).

[0049] When the sense transistor 602 is turned off, the parasitic capacitance at the drain terminal 621 of the sense transistor 602 charges until no more current flows from the first voltage source 613, and the entire voltage provided by the first voltage source 613 is applied to the drain terminal 621 of the sense transistor 602 via the drain probe 611. For example, if the first voltage source 613 provides 400 volts, the 400 volts appear at the drain terminal 621 of the sense transistor 602. In this case, the diode 616 is reverse biased, and current circulates around the inductor 614 and the forward biased diode 617. This circulating current allows current to be quickly applied again through the diode 616 when the sense transistor 602 is next turned on.

[0050] Figure 7An environment 700 is shown in which a drain voltage application circuit 710 applies a drain voltage to a drain terminal 621 of a sense transistor 602 via a drain probe 611 . Figure 7 The drain voltage applying circuit 710 and Figure 6 The drain voltage applying circuit 610 of FIG. 6 has some similarities. However, the first voltage source 613 and the resistor 612 are replaced by a voltage source 713 that selectively applies different voltages depending on whether the sensing transistor is turned on or off.

[0051] The drain voltage applying circuit 710 includes an inductor 714 coupled in series between a second voltage source 715 and the drain probe 611. A first diode 716 is connected in series between the inductor 714 and the drain probe 611 and has a forward direction from the inductor 714 to the drain probe 611. A second diode 717 is connected between the two ends of the inductor 714 and has a forward direction toward the second voltage source 715. The maximum voltage of the first voltage source 713 is greater than the voltage provided by the second voltage source 715. As an example, the first voltage source 713 can provide 400 volts when the transistor 602 is turned off, but provide a low voltage when the transistor 602 is turned on (so that the diode 716 is forward biased). Therefore, the operation of the drain voltage applying circuit 710 is similar to the operation of the drain voltage applying circuit 610, except for how to apply a low voltage when the sensing transistor 602 is fully turned on to forward bias the diode.

[0052] Thus, methods and circuits for wafer testing current characteristics of power transistors are described. Because the current characteristics of a smaller sense transistor are measured, and the current characteristics of a power transistor are determined based on the current characteristics of the smaller sense transistor, the amount of current passing through the drain probe is smaller and can therefore be applied via the drain probe. In addition, since the active regions of the power transistor and the sense transistor are formed by the same epitaxial stack, the behavior of the sense transistor is similar to that of the power transistor, but on a smaller scale, so the sense transistor is a good scaled-down substitute for the power transistor. In addition, by applying pre-conditioning to the sense transistor, the sense transistor can be appropriately stressed to simulate the same conditions that the power transistor may encounter during operation. In addition, heat can also be applied to simulate the same conditions that the power transistor may encounter during operation. Therefore, accurate wafer testing of the current characteristics of the power transistor can be performed before the wafer is cut.

[0053] Text support part

[0054] Clause 1. A method for determining current characteristics of a power transistor while the power transistor is still on a wafer, the method comprising: applying a first probe (drain probe) to a drain terminal of a sense transistor that shares a drain node with a power terminal, the sense transistor being constructed using at least a portion of the same epitaxial stack as used to construct the power transistor, the sense transistor having a lower current flow area than the power transistor; applying a second probe (source probe) to the source terminal of the sense transistor; applying a third probe (gate probe) to the gate terminal of the sense transistor; pre-conditioning the sense transistor by alternately turning the sense transistor on and off for multiple cycles while allowing the source terminal of the power transistor to float, wherein , turning on the sensing transistor includes 1) applying a gate-on voltage to the gate terminal of the sensing transistor via the gate probe, 2) applying a drain-on voltage to the drain terminal of the sensing transistor via the drain probe, and 3) applying a source-on voltage to the source terminal of the sensing transistor via the second probe; wherein, turning off the sensing transistor includes 1) applying a gate-off voltage to the gate terminal of the sensing transistor via the gate probe, 2) applying a drain-off voltage to the drain terminal of the sensing transistor via the drain probe, the drain-off voltage being greater than the drain-on voltage, and 3) applying a source-off voltage to the source terminal of the sensing transistor via the second probe. After pre-adjusting the sensing transistor, turning on the sensing transistor and measuring at least one of: 1) a current flowing from the drain terminal of the sensing transistor to the source terminal of the sensing transistor through the sensing transistor as the current increases, and 2) a drain-to-source voltage between the drain terminal of the sensing transistor and the source terminal of the sensing transistor as the drain-to-source voltage increases; and determining a current characteristic of the power transistor based on the measurement results.

[0055] Clause 2. The method of clause 1, wherein the current characteristic comprises a current when the current exits a linear region by a specific amount.

[0056] Clause 3. The method of clause 1, wherein the current characteristic comprises a saturation current.

[0057] Clause 4. The method of clause 1, the current characteristic comprising a current slope with respect to time when operating in a linear region.

[0058] Clause 5. The method of Clause 1, wherein the power transistor has a gallium nitride (GaN) channel layer, and the sensing transistor further has a GaN channel layer formed from the same epitaxial layer as the GaN channel layer of the power transistor.

[0059] Clause 6. The method of Clause 1, wherein a current flow area of ​​the power transistor is at least 100 times greater than a current flow area of ​​the sense transistor.

[0060] Clause 7. The method of Clause 1, wherein a current flow area of ​​the power transistor is at least 1000 times greater than a current flow area of ​​the sense transistor.

[0061] Clause 8. The method of clause 1, wherein each cycle is repeated at a rate of at least 10,000 times per second.

[0062] Item 9. A method according to Item 1, wherein the measurement includes measuring both of: 1) the current flowing from the drain terminal of the sensing transistor to the source terminal of the sensing transistor through the sensing transistor when the current increases, and 2) the drain-to-source voltage between the drain terminal of the sensing transistor and the source terminal of the sensing transistor when the drain-to-source voltage increases.

[0063] Clause 10. The method of clause 1, wherein the plurality of cycles comprises at least twenty cycles.

[0064] Clause 11. The method of clause 1, the off-source voltage and the on-source voltage being the same.

[0065] Clause 12. The method of clause 1, wherein the off-source voltage and the on-source voltage are both grounded.

[0066] Clause 13. The method of Clause 1, applying the turn-on drain voltage and the turn-off drain voltage during the preconditioning using circuitry connected to the drain probe.

[0067] Item 14. A method according to Item 13, wherein the circuit includes: a resistor connected in series between a first voltage source and the drain probe; an inductor coupled in series between a second voltage source and the drain probe; a first diode connected in series between the inductor and the drain probe and having a forward direction from the inductor to the drain probe; a second diode connected between two ends of the inductor and with a forward direction toward the second voltage source; and a maximum voltage of the first voltage source is higher than a maximum voltage of the first voltage source.

[0068] Clause 15. The method of clause 14, wherein the first voltage source provides a fixed voltage.

[0069] Clause 16. The method of clause 14, the first voltage source providing a first voltage when the transistor is off and providing a second voltage when the power transistor is on, the first voltage being higher than the second voltage.

[0070] Item 17. According to the method described in Item 13, the circuit includes: a first voltage source, which provides a first voltage when the transistor is turned off and provides a second voltage when the power transistor is turned on, and the first voltage is higher than the second voltage; an inductor, which is coupled in series between the second voltage source and the drain probe, and the second voltage source provides a higher voltage; a first diode, which is connected in series between the inductor and the drain probe, and has a forward direction from the inductor to the drain probe; a second diode, which is connected between the two ends of the inductor and has a forward direction toward the second voltage source; the maximum voltage of the first voltage source is higher than the maximum voltage of the first voltage source.

[0071] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the above described features or acts, or the order of the above acts. Instead, the features and acts described are disclosed as example forms of implementing the claims.

[0072] Without departing from its essential features, the present disclosure may be implemented in other specific forms. The described embodiments should be considered in all respects as merely illustrative and not restrictive. All changes within the meaning and scope of the equivalents of the claims are included within their scope.

[0073] When introducing elements in the appended claims, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

1. A method for determining a current characteristic of a power transistor while the power transistor is still on a wafer, the method comprising: applying a first probe (drain probe) to a drain terminal of a sense transistor that shares a drain node with a power terminal, the sense transistor being constructed using at least a portion of the same epitaxial stack as used to construct the power transistor, the sense transistor having a lower current flow area than the power transistor; applying a second probe (source probe) to the source terminal of the sense transistor; applying a third probe (gate probe) to the gate terminal of the sensing transistor; pre-conditioning the sense transistor by alternately turning the sense transistor on and off for a plurality of cycles while allowing the source terminal of the power transistor to float, wherein turning on the sensing transistor comprises 1) applying a gate-on voltage to the gate terminal of the sensing transistor via the gate probe, 2) applying a drain-on voltage to the drain terminal of the sensing transistor via the drain probe, and 3) applying a source-on voltage to the source terminal of the sensing transistor via the second probe; Wherein, turning off the sensing transistor comprises 1) applying a gate-off voltage to the gate terminal of the sensing transistor via the gate probe, 2) applying a drain-off voltage to the drain terminal of the sensing transistor via the drain probe, the drain-off voltage being greater than the drain-on voltage, and 3) applying a source-off voltage to the source terminal of the sensing transistor via the second probe; After pre-conditioning the sensing transistor, turning on the sensing transistor and measuring at least one of: 1) a current flowing through the sensing transistor from the drain terminal of the sensing transistor to the source terminal of the sensing transistor as the current increases, and 2) a drain-to-source voltage between the drain terminal of the sensing transistor and the source terminal of the sensing transistor as the drain-to-source voltage increases; and A current characteristic of the power transistor is determined based on the measurement result. 2 . The method according to claim 1 , wherein the current characteristic comprises a current when the current exits a linear region by a specific amount. The method of claim 1 , wherein the current characteristic comprises a saturation current. The method of claim 1 , the current characteristic comprising a current slope with respect to time when operating in a linear region. 5 . The method of claim 1 , wherein the power transistor has a gallium nitride (GaN) channel layer, and the sensing transistor further has a GaN channel layer formed of the same epitaxial layer as the GaN channel layer of the power transistor. 6 . The method of claim 1 , a current flow area of ​​the power transistor being at least 100 times greater than a current flow area of ​​the sense transistor. 7 . The method of claim 1 , a current flow area of ​​the power transistor being at least 1000 times greater than a current flow area of ​​the sense transistor.

8. The method of claim 1, wherein each cycle is repeated at a rate of at least 10,000 times per second.

9. The method of claim 1 , wherein the measuring comprises measuring both: 1) the current flowing through the sensing transistor from the drain terminal of the sensing transistor to the source terminal of the sensing transistor as the current increases, and 2) the drain-to-source voltage between the drain terminal of the sensing transistor and the source terminal of the sensing transistor as the drain-to-source voltage increases.

10. The method of claim 1, the plurality of cycles comprising at least twenty cycles.

11. The method of claim 1, wherein the off-source voltage and the on-source voltage are the same. 12 . The method according to claim 1 , wherein the off-source voltage and the on-source voltage are both grounded.

13. The method of claim 1, applying the turn-on drain voltage and the turn-off drain voltage during the preconditioning using a circuit connected to the drain probe.

14. The method of claim 13, wherein the circuit comprises: a resistor connected in series between the first voltage source and the drain probe; an inductor coupled in series between a second voltage source and the drain probe; a first diode connected in series between the inductor and the drain probe and having a forward direction from the inductor to the drain probe; as well as The second diode is connected between two ends of the inductor and faces the second voltage source in a forward direction; the maximum voltage of the first voltage source is higher than the maximum voltage of the first voltage source. The method of claim 14 , wherein the first voltage source provides a fixed voltage. 16 . The method of claim 14 , the first voltage source providing a first voltage when the transistor is turned off, and providing a second voltage when the power transistor is turned on, the first voltage being higher than the second voltage.

17. The method of claim 13, wherein the circuit comprises: a first voltage source, providing a first voltage when the transistor is turned off, and providing a second voltage when the power transistor is turned on, the first voltage being higher than the second voltage; an inductor coupled in series between a second voltage source and the drain probe, the second voltage source providing a higher voltage; a first diode connected in series between the inductor and the drain probe and having a forward direction from the inductor to the drain probe; as well as The second diode is connected between two ends of the inductor and faces the second voltage source in a forward direction; the maximum voltage of the first voltage source is higher than the maximum voltage of the first voltage source.

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