Semiconductor structure, manufacturing method thereof, laser cutting method and semiconductor unit

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof, a laser cutting method and a semiconductor unit, the semiconductor structure comprises a substrate, the substrate is provided with a plurality of cutting channels, and the plurality of cutting channels divide the substrate into a plurality of chip areas; at least part of the cutting channels are provided with at least one air gap. According to the invention, the air gaps are arranged in the substrate corresponding to the positions of the cutting channels, and the air gaps can effectively reduce the mechanical strength of the cutting channels, facilitate the separation of the adjacent chip areas in the chip expansion process, prevent the damage of external force to the chip areas during chip expansion, facilitate the reduction of the sizes of the cutting channels, facilitate the arrangement of more chip areas on the substrate, and improve the chip expansion efficiency. And the effective utilization rate of the substrate is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, a laser cutting method, and a semiconductor unit. Background Art

[0002] In the semiconductor manufacturing process, after the integrated circuit is formed on the wafer, the wafer needs to be cut into several independent dies, and then the independent dies are packaged individually or stacked to make independent chips. With the continuous improvement of device integration and cutting technology, the laser stealth dicing (SD) process has gradually become the mainstream.

[0003] However, the laser invisible cutting process still has inevitable precision defects, which makes it impossible to further reduce the size of the cutting path. At the same time, during the expansion process of laser invisible cutting, the damage area caused by cutting is large, which is easy to cause damage to the bare die. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a semiconductor structure and a manufacturing method thereof, a laser cutting method, and a semiconductor unit.

[0006] In a first aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a substrate, the substrate being provided with a plurality of cutting lanes, the plurality of cutting lanes dividing the substrate into a plurality of chip regions;

[0007] At least a portion of the scribe line is provided with at least one air gap.

[0008] In some embodiments, the scribe line is provided with a structural layer, and the air gap is provided in the structural layer.

[0009] In some embodiments, the structural layer includes a plurality of conductive layers disposed at intervals, and the air gap is disposed in at least a portion of the conductive layers.

[0010] In some embodiments, the structure layer is provided with a device structure, and the air gap is provided in the device structure.

[0011] In some embodiments, the structural layer is provided with a device structure, and the air gap is provided in the dicing street near the chip region on both sides of the device structure.

[0012] In some embodiments, a structure layer is disposed on the scribe line, and the air gap is disposed in the substrate below the structure layer.

[0013] In some embodiments, the air gaps are disposed in both the structural layer and the substrate below the structural layer, and the air gaps in the structural layer are disposed correspondingly to the air gaps in the substrate.

[0014] In some embodiments, a cross section perpendicular to the extension direction of the cutting road is set as a preset cross section;

[0015] The projection pattern of the air gap in the structural layer on the preset cross section is in the shape of a shuttle, and / or the projection pattern of the air gap in the substrate on the preset cross section is in the shape of a funnel.

[0016] In some embodiments, a plurality of the air gaps are discretely arranged in the cutting street, or a plurality of the air gaps are connected in the cutting street to form a groove.

[0017] In some embodiments, the air gap is disposed on both sides of the scribe line close to the chip region.

[0018] A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0019] providing a substrate;

[0020] At least one air gap is formed in at least a portion of the cutting lines of the substrate, wherein a plurality of the cutting lines divide the substrate into a plurality of chip regions.

[0021] In some embodiments, the manufacturing method includes:

[0022] forming a structural layer on the cutting path;

[0023] The air gap is formed in the structural layer.

[0024] In some embodiments, forming the air gap in the structural layer includes:

[0025] forming a device structure on the structural layer;

[0026] The air gap is formed in the device structure.

[0027] In some embodiments, forming the air gap in the structural layer includes:

[0028] forming a device structure on the structural layer;

[0029] The air gap is formed in the scribe line near the chip region on both sides of the device structure.

[0030] In some embodiments, the manufacturing method further comprises:

[0031] forming the air gap in the substrate;

[0032] The structural layer is formed above the air gap.

[0033] A third aspect of the present disclosure provides a laser cutting method, comprising: using a laser to cut the semiconductor structure provided by the first aspect of the present disclosure to obtain a chip.

[0034] In some embodiments, the laser cutting method includes:

[0035] Using a first laser beam to cut the cutting path of the semiconductor structure along two mutually parallel first cutting tracks;

[0036] The first cutting track is located on the cutting road and is located near the chip area of ​​the semiconductor structure.

[0037] In some embodiments, the laser cutting method includes:

[0038] Using a second laser beam to perform a single cut on a scribe line of the semiconductor structure along a second cutting track;

[0039] Wherein, the second cutting track is located in the middle of the cutting road.

[0040] A fourth aspect of the present disclosure provides a semiconductor unit, comprising: a chip obtained by the laser cutting method provided by the third aspect of the present disclosure.

[0041] In the semiconductor structure and its manufacturing method, laser cutting method and semiconductor unit provided by the present invention, an air gap is set inside the substrate corresponding to the cutting line position. The air gap can effectively reduce the mechanical strength of the cutting line, facilitate the separation of adjacent chip areas during the expansion process, prevent external forces during expansion from causing damage to the chip area, help reduce the size of the cutting line, and facilitate the setting of more chip areas on the substrate, thereby improving the effective utilization rate of the substrate.

[0042] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0045] Figure 2 According to an exemplary embodiment, Figure 1 A partial schematic diagram of area A in the middle.

[0046] Figure 3 According to an exemplary embodiment, Figure 2 Cross-sectional view along direction BB.

[0047] Figure 4 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0048] Figure 5 According to an exemplary embodiment, Figure 2 Cross-sectional view along CC direction.

[0049] Figure 6 According to another exemplary embodiment Figure 2 Cross-sectional view along CC direction.

[0050] Figure 7 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0051] Figure 8 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0052] Fig. 9 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0053] Fig.10 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0054] Fig.11 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0055] Fig.12 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0056] Fig.13 According to another exemplary embodiment Figure 2 Cross-sectional view along direction BB.

[0057] Fig.14 is a schematic diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0058] Fig.15 The diagram is a schematic diagram showing the formation of a structural layer during the manufacturing process of a semiconductor structure according to an exemplary embodiment.

[0059] Fig.16 The diagram is a schematic diagram showing the formation of partitions during the manufacturing process of a semiconductor structure according to an exemplary embodiment.

[0060] Fig.17 FIG. 4 is a schematic diagram showing the formation of an air gap during the manufacturing process of a semiconductor structure according to an exemplary embodiment.

[0061] Fig.18 According to an exemplary embodiment, Figure 1 A local schematic diagram of setting two first cutting tracks in area A.

[0062] Fig.19 According to an exemplary embodiment, Fig.18 Cross-sectional view along DD direction.

[0063] Fig. 20 According to an exemplary embodiment, Figure 1 A local schematic diagram of setting the second cutting track in area A.

[0064] Fig.21 According to an exemplary embodiment, Fig. 20 Cross-sectional view along EE direction.

[0065] Fig. 22 According to another exemplary embodiment Fig. 20 Cross-sectional view along EE direction.

[0066] Reference numerals:

[0067] 100, semiconductor structure; 101, substrate; 102, first cutting track; 103, second cutting track; 10, cutting road; 20, chip area; 21, detection pin; 30, air gap; 31, first air gap; 32, second air gap; 40, structural layer; 41, conductive layer; 42, insulating area; 43, conductive plug; 44, device structure; 50, partition. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0069] In the related art, in order to test the performance of bare dies in a wafer (for example, wafer acceptance test), detection pins are set on the cutting path to detect whether each process section meets the standard. Usually, the detection pins are set on the cutting path, which occupies the area of ​​the cutting path, resulting in an excessively large cutting path area, thereby reducing the area on the wafer where the chip area can be set.

[0070] In order to reduce the area of ​​the cutting path and form more bare chips on the wafer, the detection pins are set at the edge of the bare chips to avoid the detection pins occupying the area of ​​the cutting path. At the same time, in the process of expanding the wafer, in order to reduce the damaged area of ​​the cutting path area and the chip area adjacent to the cutting path during the expansion process, the use of a more accurate laser stealth cutting (SD) process has gradually become the mainstream. Among them, the laser stealth cutting process is to focus the laser on the inside of the wafer, irradiate the material inside the wafer, form a modified layer, and then separate the multiple bare chips formed on the wafer by splitting or expanding the film. It can be applied to the production process of thin chips or ultra-thin chips of MEMS (Micro-Electro-Mechanical System), storage and logic devices.

[0071] When using the laser invisible cutting process to cut wafers, the intensity of the cutting laser must be high, so that the range of the modified layer formed is larger, which is conducive to wafer expansion. At the same time, the spot diameter of the cutting laser must be small to avoid the laser cutting spot from deviating from the cutting track due to the accuracy of the cutting laser, which will affect the bare die (that is, the chip area).

[0072] However, when the laser invisible cutting process is actually adopted, when controlling the movement of the cutting laser spot with a smaller spot diameter, it is difficult to control the laser spot to fall accurately on the preset cutting track. When the laser spot deviates from the cutting track and approaches the bare chip, the laser spot will deviate from the position of the modified layer after deviation, which can easily cause damage to the bare chip when expanding the chip. In order to reduce the damage to the bare chip caused by the laser spot that deviates from the cutting track, it is necessary to reserve an offset for the laser spot in the cutting path, that is, it is necessary to set a wider cutting path size as the working area of ​​the laser spot, resulting in the size of the cutting path being larger than the actual size of the laser spot. However, such a setting will reduce the number of chip areas that can be set on the wafer and reduce the effective utilization rate of the wafer.

[0073] In view of this, the present disclosure provides a semiconductor structure, which includes a substrate, and the substrate is provided with a plurality of cutting paths, and the plurality of cutting paths divide the substrate into a plurality of chip areas; at least part of the cutting paths is provided with at least one air gap. The present disclosure provides an air gap inside the substrate corresponding to the cutting path position, and the air gap reduces the mechanical strength of the cutting path, facilitates separation of adjacent chip areas during chip expansion, prevents external forces during chip expansion from causing damage to the chip area, is conducive to reducing the size of the cutting path, facilitates the provision of more chip areas on the substrate, and improves the effective utilization rate of the substrate.

[0074] In the exemplary embodiments of the present disclosure, Figure 1 , Figure 2 and Figure 3 As shown, the present disclosure provides a semiconductor structure 100, which may be a wafer or a semi-finished product in the process of making a wafer. The semiconductor structure 100 includes a substrate 101, and the substrate 101 is provided with a plurality of cutting lanes 10, and the plurality of cutting lanes 10 divide the substrate 101 into a plurality of chip areas 20. The plurality of cutting lanes 10 include a plurality of cutting lanes 10 along a first direction (e.g., Figure 1 The plurality of first cutting paths extending in the transverse direction (shown in FIG. 1 ) and along the second direction (such as Figure 1 Multiple second cutting lanes extending in the vertical direction (as shown in the figure), the multiple first cutting lanes are parallel to each other, the multiple second cutting lanes are parallel to each other, there is an angle between the first direction and the second direction, the first cutting lanes and the second cutting lanes intersect with each other, and the substrate 101 is divided into multiple chip areas 20.

[0075] In one example, the first direction and the second direction are perpendicular to each other, and the plurality of cutting paths 10 divide the substrate 101 into a plurality of chip regions 20 arranged in an array. Figure 1 As shown, Figure 1 The lateral direction shown in is a first direction, Figure 1 The vertical direction shown in is the second direction.

[0076] The substrate 101 is used as a carrier for forming a plurality of chip regions 20. The substrate 101 may be a circular plate-like structure with a certain thickness. The substrate 101 may be formed of materials such as silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), etc., or may be formed of materials such as silicon on insulator (SOI), germanium on insulator (GOI), etc., or may be formed of other materials, such as III-V compounds such as gallium arsenide. The substrate 101 is used to form a wafer. After determining the positions of the cutting road 10 and the chip region 20 on the substrate 101, the plurality of chip regions 20 are arranged in an array of rows and columns on the substrate 101. According to the layout of different functional areas, circuit structures may be arranged inside the substrate 101 corresponding to the positions of the cutting road 10 and the chip region 20, for example, a circuit structure may be arranged inside the chip region 20 (not shown in the figure). There are dicing lanes 10 between adjacent chip areas 20. Since the chip areas 20 are arranged in an array on the substrate 101, and the dicing lanes 10 are arranged crosswise on the substrate 101, the chip areas 20 on the substrate 101 can be divided along the dicing lanes 10 in the subsequent dicing process to obtain bare chips formed by several independent chip areas 20. In some embodiments, since the dicing lanes 10 refer to the areas used to implement the dicing function, the dicing lanes 10 may not be provided with circuit structures, or may be provided with circuits for testing, which may be discarded after completing the testing purpose. Therefore, even if the dicing lanes 10 are cut after the test is completed, the damage to the circuits will not affect the functionality and reliability of the chip areas 20.

[0077] In this embodiment, in the subsequent cutting process of the wafer formed by the substrate 101, laser irradiation is used to perform cutting at the position of the cutting road 10. When the semiconductor structure 100 is subjected to the laser invisible cutting process, the cutting laser penetrates the material on the surface of the cutting road 10 and focuses in the substrate 101 at the corresponding position of the cutting road 10, and modifies the material inside the substrate 101 at the corresponding position of the cutting road 10 and forms cracks. The cracks can extend to the top and bottom surfaces of the substrate 101. As the cutting laser moves along the extension direction of the cutting road 10, multiple cracks are also arranged along the extension direction of the cutting road 10, thereby forming a modified layer (not shown in the figure) in the substrate 101 at the corresponding position of the cutting road 10. Further, a wafer expander is used to apply external forces in opposite directions to the chip areas 20 on both sides of the cutting road 10 after the cutting laser irradiation, so that the two adjacent chip areas 20 are broken with the modified layer at the corresponding position of the cutting road 10 as the starting point of separation, thereby forming two independent chip areas 20.

[0078] refer to Figure 2 and Figure 3 As shown, Figure 2 yes Figure 1 A partial enlarged view of area A in the middle. Figure 3 yes Figure 2 The cross-sectional view along the BB direction in FIG. The substrate 101 is provided with an air gap 30, which can be formed by not fully filling the groove or opening after etching the cutting road 10 area to form a groove or opening. The air gap 30 is provided at a position corresponding to the cutting road 10 inside the substrate 101. For example, the air gap 30 can be provided at a position corresponding to a part of the cutting road 10 of the substrate 101, or at a position corresponding to all the cutting roads 10 of the substrate 101.

[0079] In some embodiments, an air gap 30 may be provided in the substrate 101 corresponding to the position of each cutting street 10 among several cutting streets 10 , or an air gap 30 may be provided in the substrate 101 corresponding to the position of each cutting street 10 among all cutting streets 10 .

[0080] In other embodiments, two or more air gaps 30 may be provided in the substrate 101 corresponding to the position of each cutting street 10 among several cutting streets 10, or two or more air gaps 30 may be provided in the substrate 101 corresponding to the position of each cutting street 10 among all cutting streets 10.

[0081] The present disclosure has no restrictions on the number, shape, etc. of the air gaps 30 in each cutting street 10, as long as they are provided in the substrate 101 and in the area where the cutting street 10 is located, for example, they can be provided in the circuit structure area or the non-circuit structure area in the cutting street 10. Since the air gaps 30 are provided in the cutting street 10, the mechanical strength of the cutting street 10 area is reduced, and when laser cutting is performed, a lower laser intensity can be used to obtain a better cutting effect.

[0082] Since the air gap 30 is set in the cutting path 10, it is equivalent to pre-processing the fracture position of the substrate 101 in the expansion process in the cutting path 10, which has reduced the structural strength of the cutting path 10 to a certain extent, and a better cutting effect can be achieved by using a laser with a lower intensity. At the same time, as the laser intensity decreases, the laser spot does not need to be too small to focus the energy, so a cutting laser with a larger spot diameter can be used to cut the cutting path 10 to increase the cutting speed. Further, since the laser spot is directly enlarged, the probability of deviating from the cutting trajectory is smaller, and the precision requirement of the spot positioning movement of the cutting laser is reduced, so there is no need to reserve the cutting path distance to avoid the laser spot offset, and the size of the narrower cutting path 10 can be set, which is conducive to setting more chip areas 20 on the substrate 101 and improving the effective utilization rate of the substrate 101. Further, since the fracture position of the chip area 20 in the expansion process is accurate, the size of the remaining cutting path 10 on the chip area 20 after cutting is consistent, which can reduce the subsequent processing steps of the bare chip formed in the chip area 20, and reduce the size of the packaged chip after the bare chip formed in the chip area 20 is packaged.

[0083] In addition, an air gap 30 is provided in the substrate 101 corresponding to the cutting path 10, so that in the subsequent cutting process, it is convenient to expand and separate the two chip areas 20 adjacent to the cutting path 10, and prevent the external force during the expansion from causing damage to the chip area 20. When there is a precision error in the laser invisible cutting process, for example, when the cutting laser deviates from the cutting track and approaches the chip area 20, since the air gap 30 is provided at the position corresponding to part of the cutting path 10 or all of the cutting paths 10, the position where the material breaks during the expansion process of the chip area 20 can be located at the position where the air gap 30 is provided, thereby reducing the damage to the chip area 20 caused by the material rupture during the expansion process of the chip area 20, thereby reducing the impact caused by the precision error, and therefore, it is beneficial to reduce the size of the cutting path 10, facilitate the arrangement of more chip areas 20 on the substrate 101, and improve the effective utilization rate of the substrate 101.

[0084] In some possible implementations, reference Figure 2 and Figure 4 As shown, the air gap 30 is set on both sides of the cutting path 10 close to the chip area 20. That is to say, along the extension direction of the cutting path 10, two air gaps 30 parallel to each other can be set in the cutting path 10, so that the setting position of the air gap 30 is closer to the chip area 20 on both sides of the cutting path 10. When the cutting laser forms a modified layer on the cutting path 10, each air gap 30 forms a cutting track for the cutting laser to cut. The cutting laser can be irradiated between the two air gaps 30 in the cutting path 10, or two cutting lasers can be set to irradiate the positions where the two air gaps 30 are located at the same time. When the chip area 20 is expanded, two adjacent chip areas 20 can be separated based on the air gaps 30 adjacent to them as the starting point of separation, so that the material of the cutting path 10 remaining at the edge of the chip area 20 obtained after the segmentation is less, and the subsequent processing of the bare chip formed by the chip area 20 is reduced, which is conducive to the miniaturization of the packaged chip after the bare chip is packaged.

[0085] In some possible implementations, such as Figure 2 , Figure 5 and Figure 6 As shown, each cutting street 10 is provided with a plurality of air gaps 30 . Along the extending direction of the cutting street 10 , the plurality of air gaps 30 are independent of each other and are discretely distributed on the cutting street 10 , or the plurality of air gaps 30 are interconnected to form grooves.

[0086] Among the multiple cutting lanes 10 set on the substrate 101, at least one cutting lane 10 or each cutting lane 10 is provided with a plurality of air gaps 30, so that when the cutting laser moves along the extension direction of the cutting lane 10 and forms a modified layer inside the cutting lane 10, the plurality of air gaps 30 can reduce the mechanical strength of the cutting lane 10, thereby assisting in expanding the chip areas 20 on both sides of the cutting lane 10, thereby reducing the damage to the chip areas 20 during the expansion process and improving production efficiency.

[0087] In some embodiments, in combination Figure 2 and Figure 5 As shown, Figure 5 yes Figure 2 In the cross-sectional view along the CC direction, along the extension direction of the cutting road 10, multiple air gaps 30 are independent of each other and discretely distributed on the cutting road 10, so that the mechanical strength of the area along the extension direction of the cutting road 10 is reduced. The multiple air gaps 30 can locate the fracture position of the chip area 20 when the chip area 20 is expanded, so as to reduce the influence of the material fracture of the cutting road 10 on the chip area 20 during the expansion process of the chip area 20 on both sides of the cutting road 10.

[0088] In other embodiments, in combination Figure 2 and Figure 6 As shown, Figure 6 yes Figure 2 In the cross-sectional view along the CC direction in FIG. 1 , along the extension direction of the cutting road 10, a plurality of air gaps 30 are interconnected in the cutting road 10 to form a groove. For example, the plurality of air gaps 30 are interconnected, and the shapes of the plurality of air gaps 30 may be consistent and connected, that is, Figure 6 The groove shape shown may also be that a plurality of air gaps 30 are independently arranged, and a connecting channel is arranged between two adjacent air gaps 30, so that the plurality of air gaps 30 are interconnected. The plurality of air gaps 30 are interconnected along the extension direction of the cutting road 10 to form a groove, so as to further reduce the mechanical strength of the cutting road 10 and further reduce the damage to the chip area 20 during the wafer expansion process.

[0089] In an exemplary embodiment, reference Figure 2 , Figures 7 to 9 As shown, the dicing street 10 is provided with a structural layer 40 , and the air gap 30 is provided in the structural layer 40 .

[0090] Since a plurality of chip regions 20 are provided in the semiconductor structure 100, after the substrate 101 is manufactured to form a wafer, the plurality of chip regions 20 need to be tested to determine the yield of the bare chips formed by the plurality of chip regions 20 in the semiconductor structure 100, determine the bare chips with qualified quality and those with unqualified quality and mark them, so as to facilitate the packaging of the bare chips with qualified quality after cutting. A structural layer 40 is provided at a position corresponding to the cutting path 10, and the structural layer 40 may include a conductive layer 41 provided inside the substrate 101 and an insulating region 42 in the cutting path 10 region, and may also include a device structure 44. The structural layer 40 is provided inside the substrate 101 at a position corresponding to the cutting path 10, so that when the plurality of chip regions 20 on the substrate 101 are tested, the test excitation signal given to the chip region 20 by the external circuit can be transmitted through the conductive layer 41 in the structural layer 40, so as to complete the test of the bare chips formed by the chip region 20. The insulating region 42 may be formed of insulating materials such as silicon dioxide or silicon nitride, so that when a plurality of chip regions 20 in the semiconductor structure 100 are tested simultaneously, adjacent chip regions 20 are insulated from each other, thereby ensuring the accuracy of the test.

[0091] refer to Figure 7 As shown, in the structure layer 40, the air gap 30 can be set in the structure layer 40. Exemplarily, the air gap 30 can be set in the insulating region 42 (not shown in the figure), can also be set in the conductive layer 41, can also be set in both the insulating region 42 and the conductive layer 41 (not shown in the figure), and can also be set in the device structure 44 (refer to Fig.10 , which will be described in detail later). It should be noted that when the air gap 30 is provided in the conductive layer 41 in the structural layer 40, the setting position of the air gap 30 cannot disconnect the electrical signal path of the structural layer 40 corresponding to the chip area 20. That is to say, even if the air gap 30 is provided in the structural layer 40 corresponding to the chip area 20, it is necessary to ensure that the conductive layer 41 in the structural layer 40 has its normal function of transmitting electrical signals.

[0092] In an exemplary embodiment, reference Figure 2 , Figure 8 and Fig. 9As shown, the structural layer 40 includes a plurality of conductive layers 41 arranged at intervals. Since the test device for testing the chip area 20 is arranged inside the substrate 101, and the surface of the chip area 20 can be provided with a detection pin 21 for contacting a probe for applying a test electrical excitation signal to an external circuit. The structural layer 40 is provided to include a plurality of conductive layers 41 arranged at intervals. The conductive layers 41 arranged at intervals can be electrically connected through conductive plugs 43, so that the device structure 44 and the detection pin 21 at two different positions in the thickness direction of the substrate 101 are electrically connected, that is, the detection pin 21 on the chip area 20 transmits the received electrical excitation signal to the device structure 44 through the conductive layer 41 and the conductive plug 43, so as to test the corresponding chip area 20.

[0093] Exemplarily, the detection pin 21 may be a pad or a bump disposed on the surface of the chip region 20, and the detection pin 21 is used to contact a probe that applies a test electrical excitation signal to an external circuit, so that the chip region 20 can receive the electrical excitation signal for testing. The conductive layer 41 may be a metal layer formed of copper, and an insulating region 42 is disposed between two adjacent conductive layers 41. Adjacent conductive layers 41 are electrically connected through conductive plugs 43, and the conductive plugs 43 penetrate the insulating region 42 between two adjacent conductive layers 41 in the thickness direction of the substrate 101. Exemplarily, the multi-layer spaced conductive layers 41 may be formed using a Damascus process.

[0094] An air gap 30 is provided in at least part of the conductive layer 41, that is, an air gap 30 may be provided in one or more conductive layers 41. Based on the position of the electrical connection between the conductive layer 41 and the device structure 44 in each structural layer 40 corresponding to the chip region 20, the air gap 30 may be provided in as many conductive layers 41 as possible, provided that the conductive layer 41 satisfies the electrical connection between the detection pin 21 of the chip region 20 and the device structure 44.

[0095] In some embodiments, reference Figure 8 As shown, for example, when the structural layer 40 includes three conductive layers 41 arranged at intervals, due to Figure 8 The device structure 44 corresponding to the chip area 20 on the middle left is arranged on the right side farther away from the chip area 20. In order to ensure that the detection pin 21 is electrically connected to the device structure 44, an air gap 30 can be set in two of the three conductive layers 41 to assist in the subsequent expansion of the chip area 20.

[0096] In some embodiments, reference Fig. 9As shown, for example, when the structural layer 40 includes three conductive layers 41 arranged at intervals, and the device structure 44 corresponding to each chip area 20 is arranged at a position relatively close to the chip area 20, air gaps 30 can be set in all the conductive layers 41 corresponding to the positions of the cutting paths 10 without affecting the electrical connection between the detection pin 21 and the device structure 44, so as to assist in the subsequent expansion of the chip area 20.

[0097] It should be noted that, in order to improve the test efficiency, when testing the chip area 20, multiple chip areas 20 can be tested at the same time. In order to ensure the accuracy of the test, during the test, each chip area 20 and the structural layer 40 corresponding to each chip area 20 are insulated from each other. Fig. 9 , each chip area 20 is provided with a structural layer 40 corresponding thereto, and the structural layers 40 corresponding to the two adjacent chip areas 20 are insulated. Exemplarily, the device structure 44 in each structural layer 40 can be provided in an insulating material. In the actual manufacturing process, in order to improve production efficiency, when forming the structural layer 40, two structural layers 40 corresponding to the two adjacent chip areas 20 can be formed at the same time, and the two structural layers 40 are in a connected state; then all the conductive layers 41 in the structural layer 40 at the corresponding position of the cutting path 10 are etched, so as to set the air gap 30 in the conductive layer 41. In other words, the air gap 30 is provided in all the conductive layers 41, so that the conductive layer 41 originally in a connected state can be divided into two at the position corresponding to the cutting path 10, so that the structural layers 40 corresponding to the two adjacent chip areas 20 are insulated.

[0098] In some possible implementations, reference Figures 8 to 10 As shown, the structural layer 40 is provided with a device structure 44, and the device structure 44 is used to test the chip area 20, and a test circuit is provided in the device structure 44. Exemplarily, since the dicing street 10 is cut after all the chip areas 20 on the substrate 101 are tested, the bare die formed by the cut independent chip areas 20 does not need to be tested by the device structure 44, so the device structure 44 can be set in the structural layer 40 of the dicing street 10. That is to say, after the chip area 20 on the substrate 101 is cut and separated, the device structure 44 can be discarded.

[0099] refer to Fig.10As shown, when the air gap 30 is provided in the structural layer 40, the air gap 30 can be provided separately in the device structure 44 (not shown in the figure). In some embodiments, the air gap 30 can also be provided in the conductive layer 41 and the device structure 44 at the same time. Exemplarily, the air gap 30 can be provided at a position in the device structure 44 where no effective device is provided to avoid affecting the normal function of the device structure 44. The air gap 30 is provided in the device structure 44 to further reduce the mechanical strength of the corresponding area of ​​the cutting road 10, which is conducive to expanding the chip area 20.

[0100] In some possible implementations, reference Figure 2 and Fig.12 As shown, when the structural layer 40 is provided with a device structure 44, and the device structure 44 is located in the middle of the cutting road 10 and the device structure 44 is at a certain distance from two adjacent chip areas 20, an air gap 30 can be provided in the cutting road 10 near the chip areas 20 on both sides of the device structure 44. The air gap 30 can be provided in the conductive layer 41 on both sides of the device structure 44, or in the substrate 101 on both sides of the device structure 44, or in the conductive layer 41 and the substrate 101 on both sides of the device structure 44. The air gap provided in the conductive layer 41 on both sides of the device structure 44 is used as the first air gap 31, and the air gap provided in the substrate 101 on both sides of the device structure 44 is used as the second air gap 32. The positions of the first air gap 31 and the second air gap 32 are provided correspondingly to reduce the mechanical strength of the cutting road 10 where the air gap 30 is provided.

[0101] By setting air gaps 30 in the cutting path 10 near the chip area 20 on both sides of the device structure 44, the mechanical strength of the cutting path 10 can be reduced while the distance between the setting position of the air gap 30 and the chip area 20 on both sides of the cutting path 10 can be made closer. When the cutting laser forms a modified layer on the cutting path 10, each air gap 30 forms a cutting track for the cutting laser to cut. The cutting laser can be irradiated between two air gaps 30 in the cutting path 10, that is, the area corresponding to the device structure 44, or two cutting lasers can be set to irradiate the positions where the two air gaps 30 are located at the same time. When the chip area 20 is expanded, two adjacent chip areas 20 can be separated based on the air gaps 30 adjacent to them as the starting point of separation, so that the residual cutting path 10 material at the edge of the chip area 20 obtained after the segmentation is less, and the subsequent processing of the bare chip formed by the chip area 20 is reduced, which is conducive to the miniaturization of the packaged chip after the bare chip is packaged.

[0102] In an exemplary embodiment, reference Figure 2 and Fig.11 As shown, the dicing street 10 is provided with a structure layer 40 , and an air gap is provided in the substrate 101 below the structure layer 40 .

[0103] The structural layer 40 may include a conductive layer 41 disposed inside the substrate 101 and an insulating region 42 in the region of the scribe line 10, and may also include a device structure 44. The structural layer 40 is disposed inside the substrate 101 at a position corresponding to the scribe line 10, so that when testing a plurality of chip regions 20 on the substrate 101, a test excitation signal given to the chip region 20 by an external circuit may be transmitted through the conductive layer 41 in the structural layer 40, so as to complete the test of the bare die formed by the chip region 20.

[0104] In this embodiment, an air gap may not be provided in the structural layer 40, but an air gap may be provided in the substrate 101 below the structural layer 40, and the air gap provided in the substrate 101 below the structural layer 40 is used as the second air gap 32, and the second air gap 32 may be provided in the substrate 101 on the side of the device structure 44 away from the conductive layer 41 to reduce the mechanical strength of the cutting path 10. The laser intensity during the cutting process is reduced, the laser spot diameter is increased, the positioning and moving accuracy requirements of the laser spot are reduced, and the influence of damage to the chip area 20 caused by the spot positioning error is reduced, so that the size of the narrower cutting path 10 can be set, which is conducive to setting more chip areas 20 on the substrate 101 and improving the effective utilization rate of the substrate 101.

[0105] For example, along the extension direction of the cutting path 10 where the second air gap 32 is located, one or more second air gaps 32 may be provided in the substrate 101. When multiple second air gaps 32 are provided in the cutting path 10, the multiple second air gaps 32 may be independent of each other and discretely distributed in the cutting path 10, or the multiple second air gaps 32 may be interconnected. During the manufacturing process, before forming the structural layer 40, the substrate 101 may be etched to form an opening, and in the subsequent filling process, the filling process is controlled to insufficiently fill the opening to form the second air gap 32.

[0106] In some embodiments, the second air gap 32 in the substrate 101 can be set as a through groove extending along the extension direction of the cutting road 10 where it is located. Compared with the second air gap 32 being set as independent and discretely distributed grooves, the second air gap 32 is a through groove extending along the extension direction of the cutting road 10 where it is located, which can reduce the mechanical strength of the material of the cutting road 10 along the extension direction of the cutting road 10. The second air gap 32 can locate the fracture position when the chip area 20 is expanded, so as to further reduce the damage to the chip area 20 caused by the fracture of the cutting road 10 material during the expansion process.

[0107] It is understandable that the second air gap 32 may be disposed in the middle region of the cutting path 10 (eg Fig.11 As shown in the figure), it can also be arranged on both sides close to the chip area 20 (not shown in the figure), the cross section of the second air gap 32 in the extension perpendicular to the cutting road 10 (ie Fig.11The shape of the figure on the cross section (shown in FIG. 1 ) can be circular, elliptical, shuttle-shaped, funnel-shaped, etc. The present embodiment does not limit the setting manner of the second air gap 32.

[0108] In some possible implementations, reference Fig.12 and Fig.13 As shown, air gaps 30 are simultaneously provided in the structural layer 40 and the substrate 101 below the structural layer 40, and the first air gap 31 in the structural layer 40 is correspondingly provided with the second air gap 32 in the substrate 101, so that the mechanical strength of the positions where the first air gap 31 and the second air gap 32 are simultaneously provided in the cutting path 10 becomes lower, thereby reducing the laser intensity required in the cutting process, thereby increasing the laser spot diameter, reducing the positioning and movement accuracy requirements of the laser spot, and reducing the impact of damage to the chip area 20 caused by the spot positioning error.

[0109] In some possible implementations, reference Figure 2 , Fig.11 and Fig.12 As shown, a cross section perpendicular to the extension direction of the cutting path 10 is set as a preset cross section. In one example, the projection pattern of the first air gap 31 in the structural layer 40 on the preset cross section is shuttle-shaped; in another example, the projection pattern of the second air gap 32 in the substrate 101 on the preset cross section is funnel-shaped. Of course, it can be understood that different air gaps in the structural layer 40 can adopt the same shape or different shapes.

[0110] In this embodiment, the preset cross section is a cross section extending along the thickness direction of the substrate 101 and perpendicular to the extending direction of the cutting street 10 where the air gap 30 is located. That is, for the cutting street 10 extending in the horizontal direction, Figure 2 The cross section in the BB direction shown in FIG. 1 is the preset cross section. Since the cracks formed by the cutting laser in the cutting path 10 extend toward the top and bottom surfaces of the substrate 101, the projection pattern of the first air gap 31 on the preset cross section is shuttle-shaped. Fig.11 and Fig.13 As shown, the shuttle shape is a shape with pointed ends and a wide middle, so that the wider middle position of the first air gap 31 can be used as the starting point for separating two adjacent chip areas 20, so as to facilitate the expansion of the chip area 20 and reduce the damage to the chip area 20 caused by material rupture during the expansion process of the chip area 20.

[0111] Exemplarily, the projection pattern of the second air gap 32 on the preset cross section is funnel-shaped, referring to Fig.11 and Fig.13As shown, the funnel shape can be a shape with a wide top and a narrow bottom, or an inverted cone. The second air gap 32 is arranged in a funnel shape, so that the position where the second air gap 32 is wider is close to the middle position of the substrate 101 on the preset cross section, so as to be close to the crack formed by the cutting laser inside the cutting path 10, so that the second air gap 32 assists the chip area 20 in expanding the chip.

[0112] In an exemplary embodiment, the present disclosure further provides a method for manufacturing a semiconductor structure, the manufacturing method is used to manufacture the semiconductor structure provided in the above embodiment of the present disclosure, referring to Fig.14 As shown, the method for manufacturing a semiconductor structure includes the following steps:

[0113] Step S100, providing a substrate;

[0114] Step S200: forming at least one air gap in at least a portion of the cutting lines of the substrate, wherein the plurality of cutting lines divide the substrate into a plurality of chip regions.

[0115] In step S100, refer to Figure 1 As shown, the substrate 101 is used to make a wafer. The substrate 101 can be a circular plate-like structure with a certain thickness. The substrate 101 can be formed of materials such as silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), etc., and can also be formed of materials such as silicon on insulator (SOI), germanium on insulator (GOI), etc., or can also be formed of other materials, such as III-V compounds such as gallium arsenide. In step S200, reference Figures 1 to 3 As shown, according to the IC design layout, the various functional areas of the wafer formed on the substrate 101 are determined, and a plurality of cross-arranged cutting lanes 10 are defined in the substrate 101. The plurality of cutting lanes 10 divide the substrate 101 into rectangular block spaces distributed in an array and defined as chip areas 20, so that the circuit structures can be set accordingly in different functional areas during the subsequent photolithography process.

[0116] In the process of making a wafer on the substrate 101, since the wafer includes a plurality of chip areas 20, each chip area 20 corresponds to a bare die to be formed later, the IC design layout can be formed in the chip area 20 by photolithography, and the design layout corresponding to the cutting road 10 can be formed in the cutting road 10 by photolithography. After the pattern corresponding to the cutting road 10 is formed, etching is performed at the position where the air gap 30 is set in part or all of the cutting roads 10, and the subsequent filling process is controlled, for example, by using the characteristics of the material or controlling the process parameters, so that the filling material is not completely filled at the position where the air gap 30 is set, thereby forming the air gap 30. Exemplarily, after the pattern of the chip area 20 is formed, ions are doped in the corresponding area, and impurities are injected into the structure of silicon to control the local conductivity, so as to manufacture transistors and form electronic components such as diodes. After the electronic components such as transistors and diodes are manufactured, a metal interconnection process is performed to connect the transistors in the circuit structure in the chip area 20 to form a chip area.

[0117] An air gap 30 is set in at least part of the cutting road 10 of the substrate 101 to reduce the mechanical strength of the position corresponding to the cutting road 10, so that in the subsequent cutting process, it is convenient to expand and separate the two chip areas 20 adjacent to the cutting road 10 to prevent the external force during expansion from causing damage to the chip area 20. In addition, when there is a precision error in the cutting process, for example, when the cutting laser deviates from the cutting track and approaches the chip area 20, since the air gap 30 is set at the position corresponding to part of the cutting road 10 or all of the cutting road 10, the position where the material breaks during the expansion process of the chip area 20 can be located at the position where the air gap 30 is set, thereby reducing the damage to the chip area 20 caused by material rupture during the expansion process of the chip area 20, thereby reducing the impact of the precision error. Therefore, it is beneficial to reduce the size of the cutting road 10, facilitate the arrangement of more chip areas 20 on the substrate 101, and improve the effective utilization rate of the substrate 101.

[0118] In an exemplary embodiment, the method for manufacturing a semiconductor structure further includes the following steps:

[0119] Step S101, forming a structural layer on the cutting path;

[0120] Step S102: forming air gaps in the structural layer.

[0121] In step S101, refer to Fig.15As shown, based on the design layout corresponding to the cutting road 10, at the position of the cutting road 10 defined on the substrate 101, the layout corresponding to the structure layer 40 is photolithographically developed to form a photolithographic pattern corresponding to the structure layer 40. The structure layer 40 may include a conductive layer 41 and an insulating region 42 separating multiple conductive layers 41. After the photolithographic pattern is formed, etching is performed at the position where the conductive layer 41 is required to be formed to form an opening, and a metal material such as copper, aluminum, tungsten and other conductive materials are filled in the opening to form the conductive layer 41. Exemplarily, after each conductive layer 41 is formed, an insulating material is deposited on the surface of the conductive layer 41 to form an insulating region 42 separating multiple conductive layers 41, and then the insulating region 42 is partially etched to form a through hole, so that metal is filled in the through hole to form a conductive plug 43 connecting two adjacent conductive layers 41. Exemplarily, the Damascene process may be used to form the structure layer 40 including multiple conductive layers 41 and a conductive plug 43 connecting multiple conductive layers 41.

[0122] Combination Fig. 9 and Fig.15 As shown, since the structural layer 40 is used to test the corresponding chip area 20, in order to ensure that each chip area 20 is tested independently during the testing process, each structural layer 40 is only connected to the detection pin 21 of a certain chip area 20, and the structural layers 40 corresponding to different chip areas 20 are insulated.

[0123] In step S102, combining Fig. 9 and Fig.16 As shown, since each structure layer 40 is only connected to the detection pin 21 of a certain chip area 20, that is, for each chip area 20, a corresponding structure layer 40 is set. Fig.16 As shown, at the position corresponding to the cutting path 10, the structural layer 40 is etched to form a partition 50. The partition 50 can be an opening that penetrates multiple conductive layers 41. The partition 50 divides the structural layer 40 formed in step S101 into two independent structural layers 40. That is to say, the etching formed 50 insulates the structural layers 40 corresponding to each chip area 20 from each other, so that each structural layer 40 is electrically connected to the detection pin 21 of the chip area 20 corresponding to it, thereby realizing the simultaneous testing of multiple chip areas 20 before cutting the semiconductor structure 100.

[0124] Combination Fig.16 and Fig.17As shown, the insulating dielectric layer is formed in the partition 50, and the insulating dielectric layer can be formed in the partition 50 by a chemical vapor deposition method, a plasma vapor deposition method, or the like. When forming the insulating dielectric layer, by adjusting the material for forming the insulating dielectric layer or adjusting the process parameters for forming the insulating dielectric layer, when filling the partition 50 corresponding to each conductive layer 41, an incomplete filling is formed to form an air gap 30 in each conductive layer 41, thereby forming an air gap 30 in the structural layer 40. Exemplarily, the projection figure of the cross section of the air gap 30 extending along the thickness direction of the substrate 101 and perpendicular to the extension direction of the cutting path 10 where the air gap 30 is located is a shuttle shape.

[0125] In some possible implementations, in step S102, forming an air gap in the structural layer includes:

[0126] Step S1021, forming a device structure on the structural layer;

[0127] Step S1022: forming an air gap in the device structure.

[0128] In step S1021, refer to Fig.15 As shown, the position of the cutting path 10 is defined on the substrate, and the position of the device structure 44 is determined based on the position of the cutting path 10. Based on the transistors and electrical connectors arranged in the circuit pattern corresponding to the device structure 44, a corresponding test circuit is formed on the circuit pattern using processes such as ion doping and metal interconnection to form the device structure 44.

[0129] In step S1022, refer to Fig.10 As shown, a position in the device structure 44 where no effective device is provided is determined, and the position in the device structure 44 where no effective device is provided is etched to form an opening or a through hole. The opening or the through hole is filled with an insulating material, and when filling the insulating material, the ratio of the insulating material or the process parameters when filling the insulating material is adjusted, so that when the opening or the through hole is filled, an incomplete filling is formed, so as to form an air gap 30 in the device structure 44.

[0130] In some possible implementations, in step S102, forming an air gap in the structural layer includes:

[0131] Step S1023, forming a device structure on the structural layer;

[0132] Step S1024 , forming air gaps in the dicing lanes near the chip region on both sides of the device structure.

[0133] In this embodiment, step S1023 is similar to or the same as step S1021 in the above embodiment, and will not be described in detail here.

[0134] In step S1024, refer to Fig.12 As shown, when the device structure 44 is located in the middle of the dicing road 10 and the device structure 44 is at a certain distance from two adjacent chip regions 20, after the device structure 44 is formed, air gaps 30 may be formed in the dicing road 10 near the chip regions 20 on both sides of the device structure 44. The air gaps 30 may be provided in the conductive layer 41 on both sides of the device structure 44, or in the substrate 101 on both sides of the device structure 44. The air gaps provided in the conductive layer 41 on both sides of the device structure 44 are used as the first air gaps 31, and the method for forming the first air gaps 31 may be the same as or similar to the method shown in step S102, and will not be described in detail herein.

[0135] The air gaps in the substrate 101 on both sides of the device structure 44 are used as the second air gaps 32. When forming the second air gaps 32, the material of the substrate 101 on both sides of the device structure 44 can be etched to form two openings based on the distance between the device structure 44 and two adjacent chip regions 20. The two openings correspond to the positions of the first air gaps 31 in the thickness direction of the substrate 101. Then, the openings on both sides of the device structure 44 are filled with insulating material. When filling the insulating material, the proportion of the insulating material or the process parameters when filling the insulating material are adjusted to form incomplete filling when the two openings are filled, so as to form the second air gaps 32 in the cutting streets 10 near the chip regions 20 on both sides of the device structure 44.

[0136] In some possible implementations, the method for manufacturing a semiconductor structure further includes the following steps:

[0137] Step S201, forming an air gap in the substrate;

[0138] Step S202: forming a structural layer above the air gap.

[0139] In this embodiment, reference Fig.13 As shown, the air gap formed in the substrate 101 is used as the second air gap 32. Before forming the structural layer 40, the substrate 101 is etched in the area corresponding to the cutting road 10. The etching can be done by wet etching or dry etching to form a groove. For example, the cross-sectional projection of the groove extending along the thickness direction of the substrate 101 and perpendicular to the extension direction of the cutting road 10 where the groove is located is funnel-shaped. The material for filling the groove can be an insulating material such as silicon dioxide and silicon nitride. When filling the groove, by adjusting the composition of the material for filling the groove or adjusting the process parameters for filling the groove, when filling the groove, incomplete filling is formed to form the second air gap 32 in the substrate 101.

[0140] After the second air gap 32 is formed, a photolithography pattern corresponding to the structure layer 40 is formed by photolithography development on the layout corresponding to the structure layer 40 above the second air gap 32, and the photolithography pattern is etched, circuits are made, metal interconnections are performed, and other processes are performed to form the structure layer 40. Exemplarily, the structure layer 40 may include a device structure 44 close to the second air gap 32, a conductive layer 41 electrically connected to the device structure 44, and an insulating region 42 separating the multiple conductive layers 41. The method for forming the structure layer 40 is the same as or similar to the method shown in the above step S101, and is not described in detail here.

[0141] In some possible implementations, the method for manufacturing a semiconductor structure further includes:

[0142] Step S300, forming a detection pin for testing on the surface of the chip area;

[0143] Step S400: forming an electrical connection between a structure layer corresponding to the chip region and a detection pin.

[0144] In step S300, Figures 7 to 13 As shown, a detection pin 21 for testing is formed on the surface of the chip area 20. For example, a pad, a solder joint, or a bump connected to the internal circuit of the chip area 20 may be formed on the surface of the chip area 20 to serve as the detection pin 21, or the chip area 20 may be etched to expose the circuit layer inside the chip area 20 as the detection pin 21.

[0145] In step S400, since the chip area 20 corresponds to the structural layer 40 one by one, for each chip area 20, a conductive plug 43 can be set between the chip area 20 and the corresponding structural layer 40. For example, a via can be formed between the chip area 20 and the structural layer 40 by laser drilling or mechanical drilling, and then a conductive material is filled into the via to form a conductive plug 43, so that an electrical connection is formed between the structural layer 40 corresponding to the chip area 20 and the detection pin 21, so that the electrical signal can be transmitted between the detection pin 21 and the structural layer 40, thereby realizing the function of testing the chip area 20.

[0146] The semiconductor structure formed by the manufacturing method of the semiconductor structure provided by the present disclosure sets an air gap at the position corresponding to the cutting path inside the substrate to reduce the mechanical strength of the position corresponding to the cutting path, so that in the subsequent cutting process, it is convenient to expand and separate the two chip areas adjacent to the cutting path, and prevent the external force during the expansion from causing damage to the chip area. In addition, when there is a precision error in the laser invisible cutting process, for example, when the cutting laser deviates from the cutting track and approaches the chip area, since the air gap is set at the position corresponding to part of the cutting path or all of the cutting path, the position where the material breaks during the expansion process of the chip area can be located at the position where the air gap is set, thereby reducing the damage to the chip area caused by the material rupture during the expansion process of the chip area, thereby reducing the impact caused by the precision error, and therefore, it is beneficial to reduce the size of the cutting path, facilitate the setting of more chip areas on the substrate, and improve the effective utilization rate of the substrate.

[0147] In an exemplary embodiment, the present disclosure further provides a laser cutting method, comprising: using a laser to cut the semiconductor structure 100 provided in the above embodiment of the present disclosure to obtain a chip. The laser cutting method may be a laser stealth cutting (SD) method. When performing the laser stealth cutting process on the semiconductor structure 100, refer to Figures 18 to 22 As shown, the cutting laser penetrates the material on the surface of the cutting path 10 and focuses inside the semiconductor structure 100 at the corresponding position of the cutting path 10, modifies the material of the substrate 101 at the corresponding position of the cutting path 10 and forms cracks, and the cracks can extend to the top and bottom surfaces of the substrate 101. As the cutting laser moves along the extension direction of the cutting path 10, multiple cracks are also arranged along the extension direction of the cutting path 10, thereby forming a modified layer (not shown in the figure) in the substrate 101 at the corresponding position of the cutting path 10. Furthermore, a wafer expander is used to apply external forces in opposite directions to the chip areas 20 on both sides of the cutting path 10 after the cutting laser is irradiated, so that the two adjacent chip areas 20 are broken with the modified layer at the corresponding position of the cutting path 10 as the starting point of separation, thereby obtaining two independent chips.

[0148] When the semiconductor structure 100 provided by the present disclosure is cut by laser, since an air gap 30 is provided in the cutting path 10, it is equivalent to pre-processing the fracture position of the substrate 101 in the expansion process in the cutting path 10, which has reduced the structural strength at the cutting path 10 to a certain extent. The use of a laser with a lower intensity can achieve a better cutting effect and prevent the chip area 20 from being damaged during the expansion process. At the same time, as the laser intensity decreases, the laser spot does not need to be too small to focus the energy. Therefore, a cutting laser with a larger spot diameter can be used to cut the cutting path 10 to increase the cutting speed. Furthermore, since the laser spot is directly increased, the probability of deviating from the cutting trajectory is smaller, and the accuracy requirement of the spot positioning movement of the cutting laser is reduced, so there is no need to reserve a cutting path distance to avoid the laser spot offset, and a narrower cutting path 10 size can be set, which is conducive to setting more chip areas 20 on the substrate 101 and improving the effective utilization rate of the substrate 101. Furthermore, since the fracture position of the chip area 20 during the expansion process is accurate, the size of the remaining cutting lanes 10 on the chip area 20 after cutting is consistent, the subsequent processing steps for the bare die formed by the chip area 20 can be reduced, and the size of the packaged chip after the bare die formed by the chip area 20 is packaged can be reduced. In addition, when there is a precision error in the cutting laser, since the air gap 30 is set at the position corresponding to part of the cutting lanes 10 or all of the cutting lanes 10, the position where the material breaks during the expansion process of the chip area 20 can be located at the position where the air gap 30 is set, thereby reducing the damage to the chip area 20 caused by the material rupture during the expansion process of the chip area 20, thereby reducing the impact caused by the precision error.

[0149] In some possible implementations, reference Fig.18 and Fig.19 As shown, the laser cutting method provided by the present disclosure includes:

[0150] Step S1, using a first laser beam to cut a cutting path of a semiconductor structure along two mutually parallel first cutting paths; wherein the first cutting paths are located on the cutting paths and at positions close to a chip region of the semiconductor structure.

[0151] The path of the cutting laser moving in the extending direction of the cutting path 10 is the cutting track. Fig.18 and Fig.19It is shown by dotted lines, that is, during the cutting process, the cutting laser is continuously irradiated or intermittently irradiated along the route defined by the cutting track located on the cutting road 10, so as to form cracks inside the cutting road 10 corresponding to the position where the cutting track is set, so as to facilitate the expansion of the chip area 20 on the semiconductor structure 100. It should be noted that since the path defined by the cutting track extends along the extension direction of the cutting road 10 where it is located, when the cutting track is set on the cutting road 10, the projection of the cutting track on the cutting road 10 and the projection of the air gap 30 on the cutting road 10 should partially overlap or completely overlap, so that the air gap 30 can assist the expansion process of the chip area 20 after the cutting laser cuts the cutting road 10, so as to reduce the damage to the chip area 20 caused by the expansion process.

[0152] refer to Fig.18 and Fig.19 As shown, since the obtained chip after cutting does not need to be subjected to other tests through the structural layer 40, the structural layer 40 arranged on the cutting path 10 can be discarded or damaged. An air gap 30 is formed in the cutting path 10 near the chip area 20 on both sides of the device structure in the structural layer 40, so that two mutually parallel first cutting tracks 102 are respectively arranged at the positions of the semiconductor structure 100 near the chip area 20 on the cutting path 10, that is, the device structure in the structural layer 40 is arranged between the two mutually parallel first cutting tracks 102. The cutting path 10 is cut along the two mutually parallel first cutting tracks 102 using a first laser beam. Since the first cutting track 102 is arranged near the chip area 20, the spot area of ​​the first laser beam should be controlled to be smaller to avoid damage to the chip area 20. After the first laser beam cuts along two mutually parallel first cutting tracks 102, two adjacent chip areas 20 can be separated based on the first cutting tracks 102 adjacent to them as the starting points for separation, and the device structure in the structural layer 40 is completely discarded. No damaged device structure 44 will remain on the chip area 20, and the edges of the chips obtained after segmentation have less residual cutting path 10 material, which reduces the subsequent processing steps of the chips and is beneficial to the miniaturization of the packaged chips after packaging.

[0153] In some possible implementations, reference Figure 20 to Figure 22 As shown, the laser cutting method includes:

[0154] Step S2, using a second laser beam to perform a single cut on the cutting path along a second cutting track; wherein the second cutting track is located in the middle of the cutting path, and the spot area of ​​the second laser beam is larger than the spot area of ​​the first laser beam.

[0155] In some embodiments, in combination Figure 20 to Figure 21As shown, when only one air gap 30 is set in the cutting road 10 in two adjacent chip areas 20, since the independent chip obtained by cutting does not need to pass through the device structure in the structural layer 40 for other tests, the device structure set in the cutting road 10 can be discarded or damaged. By setting a second cutting track 103 in the middle position of the cutting road 10, the second cutting track 103 partially overlaps or completely overlaps with the position where the air gap 30 is located, so that after the second laser beam cuts the cutting road 30 once along the second cutting track 103, the modified layer generated by the second laser beam partially corresponds to or completely corresponds to the position of the air gap 30 on the second cutting track 103, so that the air gap 30 on the second cutting track 103 can play an auxiliary role in separating the two adjacent chip areas 20. Exemplarily, the second cutting track 103 can pass through the device structure in the structural layer 40, so that in the subsequent expansion process, the device structure set inside the cutting road 10 is damaged, and there is no complete device structure in the chip obtained by segmentation. Since the second cutting track 103 is disposed in the middle of the cutting street 10 , the second laser beam is unlikely to cause damage to the chip regions 20 on both sides of the cutting street 10 .

[0156] In some embodiments, the spot area of ​​the second laser beam is set to be larger than the spot area of ​​the first laser beam, and a wider modified layer can be formed in the substrate 101 corresponding to the second cutting track 103, which can improve the speed of laser stealth cutting while ensuring that adjacent chip areas 20 are well separated.

[0157] In other embodiments, in combination Fig. 20 and Fig. 22 As shown, when the air gap 30 is arranged on both sides of the cutting path 10 close to the chip area 20, that is, along the extension direction of the cutting path 10, two air gaps 30 parallel to each other are arranged in the cutting path 10, and the second cutting track 103 is arranged in the middle of the cutting path 10. Since the spot area of ​​the second laser beam is large, the spot area of ​​the second laser beam can cover the area between the two air gaps 30, that is, the spot of the second laser beam does not overlap with the position where the air gap 30 is arranged. The second laser beam can form a wider modified layer in the substrate 101 corresponding to the second cutting track 103, while improving the speed of laser invisible cutting, since the air gaps 30 are arranged on both sides of the cutting path 10 close to the chip area 20, in the subsequent expansion process, the position where the air gap 30 is located is the position where the chip area 20 is broken, and the chip area 20 will not be damaged due to the large spot area of ​​the second laser beam.

[0158] In an exemplary embodiment, the present disclosure further provides a semiconductor unit, which includes a chip obtained by the above-mentioned laser cutting method. The semiconductor unit can be a packaged chip including one chip, or an HBM (High Bandwidth Memory) including multiple chips, and the present disclosure does not limit this. Since the chip in the semiconductor unit is obtained by the laser cutting method in the above-mentioned embodiment of the present disclosure, the edge structure of the chip is less damaged, the reliability of the chip is higher, and the semiconductor unit formed by using the chip has good electrical performance and functional reliability. In addition, since there is less cutting road material remaining at the edge of the chip, the semiconductor unit formed by using the chip has a smaller volume.

[0159] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0160] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0161] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0162] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0163] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0164] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises a substrate, wherein the substrate is provided with a plurality of cutting paths, and the plurality of cutting paths divide the substrate into a plurality of chip areas; At least a portion of the scribe line is provided with at least one air gap.

2. The semiconductor structure according to claim 1, characterized in that: The cutting path is provided with a structural layer, and the air gap is provided in the structural layer.

3. The semiconductor structure according to claim 2, characterized in that: The structural layer includes a plurality of conductive layers arranged at intervals, and the air gap is arranged in at least a portion of the conductive layers.

4. The semiconductor structure according to claim 2, characterized in that: The structural layer is provided with a device structure, and the air gap is provided in the device structure.

5. The semiconductor structure according to claim 2, characterized in that: The structural layer is provided with a device structure, and the air gap is provided in the cutting path close to the chip region on both sides of the device structure.

6. The semiconductor structure according to claim 1, characterized in that The cutting road is provided with a structural layer, and the air gap is provided in the substrate below the structural layer.

7. The semiconductor structure according to claim 6, characterized in that: The air gap is disposed in both the structural layer and the substrate below the structural layer, and the air gap in the structural layer is disposed correspondingly to the air gap in the substrate.

8. The semiconductor structure according to claim 6, characterized in that: Setting a cross section perpendicular to the extending direction of the cutting path as a preset cross section; The projection pattern of the air gap in the structural layer on the preset cross section is in the shape of a shuttle, and / or the projection pattern of the air gap in the substrate on the preset cross section is in the shape of a funnel.

9. The semiconductor structure according to claim 1, characterized in that: A plurality of the air gaps are discretely arranged in the cutting street, or a plurality of the air gaps are connected in the cutting street to form a groove.

10. The semiconductor structure according to claim 1, wherein: The air gap is arranged on two sides of the dicing road close to the chip area.

11. A method for manufacturing a semiconductor structure, characterized in that: The production method comprises: providing a substrate; At least one air gap is formed in at least a portion of the cutting lines of the substrate, wherein a plurality of the cutting lines divide the substrate into a plurality of chip regions.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The production method comprises: forming a structural layer on the cutting path; The air gap is formed in the structural layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The forming of the air gap in the structural layer comprises: forming a device structure on the structural layer; The air gap is formed in the device structure.

14. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The forming of the air gap in the structural layer comprises: forming a device structure on the structural layer; The air gap is formed in the scribe line near the chip region on both sides of the device structure.

15. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: The production method further comprises: forming the air gap in the substrate; The structural layer is formed above the air gap.

16. A laser cutting method, characterized in that: include: The semiconductor structure according to any one of claims 1 to 8 is cut by laser to obtain a chip.

17. The laser cutting method according to claim 16, characterized in that: The laser cutting method comprises: Using a first laser beam to cut the cutting path of the semiconductor structure along two mutually parallel first cutting tracks; The first cutting track is located on the cutting road and is located at a position of the semiconductor structure close to the chip area.

18. The laser cutting method according to claim 16, characterized in that: The laser cutting method comprises: Using a second laser beam to perform a single cut on a scribe line of the semiconductor structure along a second cutting track; Wherein, the second cutting track is located in the middle of the cutting road.

19. A semiconductor unit, characterized in that: include: A chip obtained by the laser cutting method according to any one of claims 16 to 18.

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