Overcurrent protection circuit and method and electronic equipment

Abstract

The invention provides an overcurrent protection circuit, an overcurrent protection method and electronic equipment, the overcurrent protection circuit is applied to at least two current output circuits, and the overcurrent protection circuit comprises at least two current detection modules and a common reference current generation module; the current detection module is correspondingly connected with the current output circuit, and the current detection module is used for sampling a real-time current value output by the current output circuit to obtain a sampling current; the output end of the common reference current generation module is connected with each current detection module; the common reference current generation module is used for generating at least two paths of reference current and providing one path of reference current for each current detection module; and the current detection module is also used for comparing the sampling current with the reference current and carrying out circuit protection based on a comparison result. For each path of current output circuit, multiple paths of reference current can be generated only by trimming one path of common reference current generation module, so that the device layout cost is saved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit design, and in particular to an overcurrent protection circuit, method and electronic device. Background Art

[0002] Overcurrent protection circuits are widely used in various IC (Integrated Circuits) chips. Adding overcurrent protection circuits to IC chips can prevent burning caused by large currents. In practical applications, when the current exceeds the set overcurrent threshold, the overcurrent protection can shut down the IC chip in time to prevent damage to the electronic equipment. In the display field, the LS (Level Shifter) chip converts the low-voltage control signal input by the TCON (Timing Controller) into the high-voltage control signal required for the TFT (Thin Film Transistor) to turn on and off. Therefore, an overcurrent protection circuit needs to be added to the LS chip to prevent the screen from being burned by large currents under abnormal conditions.

[0003] There are multiple output high-voltage control signals in the LS chip, which require multiple overcurrent protection circuits to detect them. To ensure current accuracy, multiple output currents must be generated by fine-tuning the reference current generation circuit to generate corresponding reference currents, which increases the circuit area. Summary of the invention

[0004] The embodiments of the present application provide an overcurrent protection circuit, method and electronic device to solve the problem in the prior art that multiple output currents need to be configured with corresponding reference current generation circuits, resulting in a large circuit area.

[0005] In a first aspect, an embodiment of the present application provides an overcurrent protection circuit, which is applied to at least two current output circuits, and the overcurrent protection circuit includes: at least two current detection modules, and a common reference current generation module;

[0006] The current detection module is correspondingly connected to the current output circuit, and the current detection module is used to sample the real-time current value output by the current output circuit to obtain a sampled current;

[0007] The output end of the common reference current generating module is respectively connected to each of the current detection modules; the common reference current generating module is used to generate at least two reference currents and provide one reference current for each current detection module; the current detection module is also used to compare the sampled current with the reference current and perform circuit protection based on the comparison result.

[0008] In a second aspect, an embodiment of the present application provides an overcurrent protection method, which is applied to the overcurrent protection circuit described in the first aspect, and the method includes:

[0009] Acquire a sampled current obtained by sampling the real-time current value output by the current output circuit by the current detection module, and acquire a reference current corresponding to each current output circuit generated by a common reference current generation module;

[0010] For each current output circuit, compare the sampled current with the reference current to obtain a comparison result;

[0011] Circuit protection is performed according to the comparison result.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising the overcurrent protection circuit as described in the first aspect.

[0013] The overcurrent protection circuit disclosed in the embodiment of the present application is applied to at least two current output circuits, and the overcurrent protection circuit includes: at least two current detection modules and a common reference current generating module; the current detection module is connected to the current output circuit correspondingly, and the current detection module is used to sample the real-time current value output by the current output circuit to obtain a sampled current; the output end of the common reference current generating module is respectively connected to each of the current detection modules; the common reference current generating module is used to generate at least two reference currents and provide a reference current for each current detection module; the current detection module is also used to compare the sampled current with the reference current, and perform circuit protection based on the comparison result. In the circuit of the present application, each current output circuit is correspondingly provided with a current detection module to sample the real-time current value output to obtain a sampled current, and the multi-channel current output circuit is only provided with a common reference current generating module. For the multi-channel current output circuit, only one common reference current generating module needs to be adjusted, and multiple reference currents are generated by one common reference current generating module, which is used to perform overcurrent protection on the multi-channel current output circuit, thereby reducing the area of ​​the circuit generating the reference current and saving the device layout cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An overcurrent protection circuit is provided in an embodiment of the present application;

[0015] Figure 2 is a circuit structure diagram of a common reference current generating module provided in an embodiment of the present application;

[0016] Figure 3 is a circuit structure diagram of a current detection module provided in an embodiment of the present application;

[0017] Figure 4is a flow chart of an overcurrent protection method provided by an embodiment of the present application;

[0018] Figure 5 It is a structural block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0020] Figure 1 An overcurrent protection circuit is provided in an embodiment of the present application, which is applied to at least two current output circuits. The overcurrent protection circuit includes: at least two current detection modules and a common reference current generating module; the current detection module is connected to the current output circuit accordingly, and the current detection module is used to sample the real-time current value output by the current output circuit to obtain a sampled current; the output end of the common reference current generating module is respectively connected to each of the current detection modules; the common reference current generating module is used to generate at least two reference currents and provide one reference current for each current detection module; the current detection module is also used to compare the sampled current with the reference current, and perform circuit protection based on the comparison result.

[0021] In the examples of this application, refer to Figure 1 , Figure 1 An overcurrent protection circuit architecture diagram is shown. In the present application, the current output circuit may include devices that need to be protected from overcurrent, such as MOS tube circuits, such as PMOS (P-Metal-Oxide-Semiconductor) tubes, or NMOS (N-Metal-Oxide-Semiconductor) tubes. An integrated circuit composed of MOS tubes is called a MOS integrated circuit, a circuit composed of NMOS is an NMOS integrated circuit, a circuit composed of PMOS tubes is a PMOS integrated circuit, and a complementary MOS circuit composed of NMOS and PMOS tubes is a CMOS circuit. In the present application, the current output circuit is an NMOS circuit as an example to illustrate the overcurrent protection of the NMOS circuit, and reference is made to FIG. Figure 1, including VGH pin, VGHM5 pin, LVGLP5 pin and LVGL pin, wherein VGH pin and LVGLP5 pin are pins for providing high voltage power supply to the circuit, and VGHM5 pin and LVGL pin are pins for providing low voltage to the circuit; the gate of the PMOS tube is connected to the driving circuit pdrive, the driving circuit includes a logic driving circuit and an amplifier, the amplifier is used to amplify the logic driving signal output by the logic driving circuit and input it to the PMOS tube to drive the PMOS tube to turn on, similarly, the gate of the NMOS tube is connected to the driving circuit ndrive, the driving circuit ndrive includes a logic driving circuit and an amplifier, the amplifier is used to amplify the logic driving signal output by the logic driving circuit and input it to the NMOS tube to drive the NMOS tube to turn on. The driving circuit is used to drive the power MOS tube so that the output outputs a high-voltage control signal according to the timing setting. Figure 1 The current detection module in the circuit may be a circuit for sampling the real-time current value flowing through the NMOS circuit.

[0022] The current detection module is used to sample the output current of the current output circuit, obtain the sampled current, and compare the sampled current with the reference current to determine whether to perform overcurrent protection on the current output circuit. The common reference current generation module is used to provide multiple reference currents to achieve overcurrent protection for each current output circuit.

[0023] Specifically, refer to Figure 1 ,pdrive <n:1>That is, n PMOS tubes correspond to n drive circuits pdrive, ndrive <n:1>That is, n NMOS tubes correspond to n drive circuits ndrive, isns <n:1>That is, when there are n MOS tube output currents, n sampling circuits are required to sample the currents, iref <n:1>That is, when there are n MOS tube output currents, the common reference current generating module needs to generate n reference currents, iref_trim represents a preset input current, and n reference currents are generated by this preset input current, that is, only one circuit of the common reference current generating module needs to be adjusted to generate multiple reference currents, thereby realizing overcurrent protection for multiple current output circuits.

[0024] That is, in the present application, for multiple current output circuits, when the multiple current output circuits each include the same NMOS circuit, since the same NMOS circuit can perform overcurrent protection by setting the same reference current, it is only necessary to adjust one common reference current generating module so that the reference current output by it meets the overcurrent protection requirement for the current output circuit. In this way, after the common reference current generating module is adjusted, the multiple reference currents it outputs are provided to the multiple current output circuits respectively, thereby realizing overcurrent protection for the multiple current output circuits, saving the time spent on adjusting the circuit that generates the reference current for each current output circuit, and saving the layout area occupied by the circuit that generates the reference current for each current output circuit.

[0025] Optionally, the common reference current generating module includes a voltage conversion unit and a reference current output unit; the voltage conversion unit is used to convert a preset input current into a reference voltage, and the reference current output unit is used to generate a reference current based on the reference voltage and convert the reference current into multiple identical reference currents.

[0026] In the examples of this application, refer to Figure 2 The common reference current generating module includes a voltage conversion unit and a reference current output unit, wherein the voltage conversion unit is used to receive a preset input current iref_trim, and the MOS tubes M1-M4 are pulled down to ground to convert the preset input current into a reference voltage. At this time, a reference voltage is generated at the non-inverting input terminal of the amplifier, and the reference voltage is amplified by the operational amplifier and acts on the MOS tube M5 to adjust the output current size from the drain to the source of the MOS tube M5, so that the MOS tube M5 outputs the reference current. The reference current output by the MOS tube M5 is copied by the current mirrors M6-M7 and converted into multiple identical reference currents.

[0027] Optionally, the reference current output unit includes: a first resistor, a first MOS tube and a current mirror unit; the source of the first MOS tube is connected to one end of the first resistor, the drain of the first MOS tube is connected to the current mirror unit, the gate of the first MOS tube is connected to the output end of the voltage conversion unit, and the other end of the first resistor is grounded.

[0028] In the examples of this application, refer to Figure 2 The reference current output unit is a unit for outputting a reference current, and includes: a first resistor R1, a first MOS tube M5 and a current mirror unit (M6-Mx); a source of the first MOS tube M5 is connected to one end of the first resistor R1, a drain of the first MOS tube M5 is connected to the current mirror unit, a gate of the first MOS tube M5 is connected to the output end of the voltage conversion unit, the other end of the first resistor R1 is grounded, and the first resistor R1 is connected to the negative end of the amplifier, so as to control the magnitude of the output reference current.

[0029] Optionally, the current mirror unit comprises: a plurality of current mirror branches connected in parallel; the number of the current mirror branches is the same as the number of the current output circuit; and the plurality of current mirror branches are used to output a plurality of identical reference currents.

[0030] In the examples of this application, refer to Figure 2 The current mirror unit includes: multiple parallel current mirror branches, the current flowing through the MOS tube M6 is the same as the current flowing through the first MOS tube M5, the current mirror branch can realize current mirroring, wherein the MOS tube M6 can be used as a reference transistor, the current passes through the MOS tube M6, and the MOS tube M6 can automatically adjust the driving voltage of the transistor so that the output transistors M7, M8...Mx output the same reference current, and the reference current output by the current mirror branch is compared with the sampling current of the current detection module to realize overcurrent protection of the current output circuit.

[0031] Optionally, the voltage conversion unit includes: a plurality of second MOS tubes and an operational amplifier connected in series; the inverting input terminal of the operational amplifier is connected to one end of the first resistor, and the output terminal of the operational amplifier is connected to the gate of the first MOS tube; the drain of the first second MOS tube among the plurality of second MOS tubes connected in series is connected to the non-inverting input terminal of the operational amplifier, and the drain of the first second MOS tube is also used to receive a preset input current; the plurality of second MOS tubes connected in series are used to convert the preset input current into a reference voltage and input it into the non-inverting input terminal of the operational amplifier; the source of the last second MOS tube among the plurality of second MOS tubes connected in series is grounded; and the gate of each second MOS tube is connected to a power supply terminal.

[0032] In the embodiment of the present invention, reference Figure 2 The voltage conversion unit is used to convert the preset input current iref_trim into a reference voltage, including: a plurality of second MOS tubes and operational amplifiers connected in series in sequence, the plurality of second MOS tubes connected in series in sequence include: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, the source of MOS tube M1 is connected to the drain of MOS tube M2, the source of MOS tube M2 is connected to the drain of MOS tube M3, the source of MOS tube M3 is connected to the drain of MOS tube M4, the source of MOS tube M4 is grounded, and the plurality of second MOS tubes connected in series in sequence are connected to a common gate voltage, and the gate voltage can change the conductivity between the source and the drain. When the second MOS tube is connected in series and pulled down to ground, its working state is controlled by the gate voltage, thereby affecting the current and voltage distribution in the circuit. In the circuit design, by connecting NMOS tubes in series and pulling down to ground, the input current can be converted into voltage. Among them, the second MOS tube can be a plurality of NMOS tubes with the same parameters.

[0033] When the preset input current passes through the second MOS tube, if the second MOS tube is turned on, the current can flow from the source to the drain, and the voltage of the drain (output voltage) will change according to the size of the preset input current and the degree of conduction of the second MOS tube. If the second MOS tube is cut off (that is, the gate voltage is less than the threshold voltage), almost no current can pass through the second MOS tube, and the output voltage is close to 0V. Therefore, by controlling the degree of conduction of the NMOS tube, the size of the output voltage can be adjusted to achieve the conversion from current to voltage. That is, the drain of the first second MOS tube among the multiple second MOS tubes connected in series is connected to the non-inverting input terminal of the operational amplifier, and the multiple second MOS tubes connected in series are used to convert the preset input current into a reference voltage to obtain the voltage of the non-inverting input terminal of the amplifier.

[0034] refer to Figure 2 , input the preset current iref_trim, M1-M4 are pulled down to ground, and the preset input current is converted into a reference voltage. At this time, a voltage is generated at the positive input terminal of the amplifier, which acts on the first MOS tube M5 after being amplified by the operational amplifier, and the emitter current of M5 acts on the first resistor R1. When the amplifier is working, the positive terminal voltage and the negative terminal voltage are the same, and the positive terminal voltage is: iref_trim*k*Rdson, where k*Rdson is the impedance value of the second MOS tubes M1 to M4, the voltage at the negative terminal of the amplifier is the voltage across the first resistor R1, and the current flowing through the first resistor R1 is the current flowing through the MOS tubes M6 and the first MOS tube M5. The current flowing through M6 is equal to Iref <1> 、Iref <2> The first resistor R1 is connected to the inverting terminal of the amplifier, where no current is generated. Therefore, the voltage across the first resistor R1 is Iref <1> *R1, therefore, according to the positive terminal voltage and the reverse terminal voltage are the same, we can get iref_trim*k*Rdson=Iref <1> *R1, get Iref <1> =Iref <2> =Iref <n>=iref_trim*k*Rdson / R1. That is, the reference current output by the reference current output unit is related to the preset input current, the impedance value of the second MOS tube and the first resistor R1. The reference current can be adjusted by adjusting the preset input current, the impedance value of the second MOS tube or the first resistor R1. The accuracy of k is related to the relationship between M1 to M4 and Figure 1 The second MOS tube can be related to the matching degree of the NMOS in the Figure 1 The specifications of the NMOS tube in the MOS tube are the same as those of the NMOS tube. Figure 1 The NMOS tube in the middle is turned on by the gate voltage LCGLP5. Figure 2 The second MOS tube is also turned on through LVGLP5, that is, the gate voltage of M1-M4 is the same. At this time, the impedance will be related to the width-to-length ratio. Here, k is the k-fold relationship between the impedance value of M1-M4 in series and the impedance value of NMOS. If the second MOS tube is Figure 1 The specifications of the NMOS tube in the second MOS tube are the same as those of the NMOS tube. Figure 1 The NMOS in the circuit has the same width-to-length ratio. At this time, the impedance value of the NMOS tube is Figure 2 The impedance value of any one of the second MOS tubes M1 to M4 is the same. Figure 2 Take the four MOS tubes in series as an example. After the series connection, the impedance value generated is Figure 1 The impedance value of the NMOS tube in the middle is 4 times, and the value of k is 4. The actual number of second MOS tubes will only affect the multiple of k. The specific number of high-voltage tubes connected in series can be set according to actual conditions, and the embodiment of the present application is not limited here.

[0035] Therefore, for the shared reference current generating module, it only needs to be adjusted once to obtain a suitable reference current, and the reference current is copied and outputted in N copies using a current mirror unit, where N is the same as the number of current output circuits. This can achieve overcurrent protection for multiple current output circuits, saving the area of ​​a circuit for generating a reference current in each current output circuit.

[0036] Optionally, the current detection module includes: a sampling circuit and a comparator, the positive end of the comparator is connected to the sampling circuit, the negative end of the comparator is connected to the common reference current generating module, and the output end of the comparator is connected to the input end of the current output circuit; the sampling circuit is used to sample the real-time current value output by the current output circuit to obtain a sampling current; the comparator is used to compare the sampling current with a reference current generated by the common reference current generating module, and feed back the comparison result to the input end of the current output circuit to control the working state of the current output circuit.

[0037] In the embodiment of the present invention, reference Figure 1 The current detection module includes: a sampling circuit and a comparator. The positive end of the comparator is connected to the sampling circuit to obtain the sampling current. The sampling circuit is used to sample the real-time current value output by the current output circuit and convert the real-time current value output into a physical quantity representing its size, namely the sampling current. The negative end of the comparator is connected to the common reference current generation module to obtain the reference current. The output end of the comparator is connected to the input end of the current output circuit to feed back the comparison result of the sampling current and the reference current to the input end of the current output circuit, so that the current output circuit cuts off or continues the current output based on the feedback comparison result. For example, if the sampling current is greater than the reference current, it indicates that the output current of the current output circuit is too large. At this time, the driving circuit in the current output circuit can be stopped from driving the NMOS tube, and the current output circuit can be cut off from continuing to output current, so as to protect the NMOS tube from overcurrent.

[0038] Optionally, the sampling circuit includes: an inverter circuit, a second resistor, a third resistor and a common-gate amplifier circuit; the input end of the inverter circuit is connected to the current output circuit, the output end of the inverter circuit is connected to one end of the second resistor, and the other end of the second resistor is connected to the first end of the common-gate amplifier circuit; one end of the third resistor is connected to the negative end of the power supply, and the other end of the third resistor is connected to the second end of the common-gate amplifier circuit; the second resistor and the third resistor are the same; the third end of the common-gate amplifier circuit outputs the sampling current.

[0039] In the embodiment of the present invention, reference Figure 3 The sampling circuit includes: an inverter circuit, a second resistor R2, a third resistor R3 and a common-gate amplifier circuit. The inverter circuit is connected to the current output circuit. The common-gate amplifier circuit is an internal circuit structure of the amplifier, that is, when the common-gate amplifier circuit is working, the voltage at the positive end is equal to the voltage at the negative end.

[0040] refer to Figure 3 The working principle of the sampling circuit is: after NMOS is turned on, MOS tube M9 is turned on (MOS tube M9 and MOS tube M10 form an inverter, one of which is turned on and the other is turned off). When the common gate amplifier circuit is working, the voltage at the positive end is equal to the voltage at the negative end. Therefore, the voltage at both ends of MOS tube M11 and MOS tube M12 is equal. According to this feature, the voltage at both ends of MOS tube M11 and MOS tube M12 can be calculated respectively. The current flows from positive to negative, that is, from LVGLP5 to LVGL. At this time, the voltage at the end of MOS tube M11 is: The sum of the voltage across the resistor R2 and the voltage at the NMOS terminal, the current flowing through the second resistor R2 is the current of the current source I1, at this time, the voltage across the second resistor R2 can be obtained as I1*R2, and the voltage at the NMOS terminal is: Iocp*Rdson, where Iocp is the real-time current value flowing through the NMOS tube, Rdson is the impedance value of the NMOS, the voltage at the MOS tube M12 terminal is the voltage across the third resistor R3, the current flowing through the third resistor R3 is the current of the current source I2 and the current flowing out of the MOS tube M13, and the MOS tube M1 The current of MOS tube M3 is the same as that of MOS tube M14 and MOS tube M15. The output of MOS tube M15 is sampling current isns. Therefore, the current flowing through MOS tube M13 is isns. At this time, the voltage across the third resistor R3 can be expressed as: (isns+I2)*R3. According to the characteristics of the amplifier circuit, the formula Iocp*Rdson+I1*R2=(isns+I2)*R3 can be obtained. Here, the second resistor R2 and the third resistor R3 are resistors with the same resistance value, and their resistance values ​​can be uniformly represented by R. Therefore, the above The formula can be transformed into: Iocp*Rdson+I1*R=(isns+I2)*R, the current source I1 and the current source I2 are the same current source, and the current they provide is the same. After sorting, the relationship between the sampling current and the real-time current value Iocp flowing through the NMOS tube is obtained: isns=locp*Rdson / R, that is, the size of the sampling current is related to the impedance value of the NMOS tube, the real-time current value Iocp and the resistance value R, that is, the size of the sampling current can be changed by adjusting the size of the second resistor R2 and the second resistor R3.

[0041] For multiple current output circuits, their respective corresponding sampling circuits can copy and use the above sampling circuit for sampling.

[0042] Optionally, the common-gate amplifier circuit includes: a first current source, a second current source, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; the first current source is the same as the second current source; the gate of the third MOS tube is connected to the gate of the fourth MOS tube, the source of the third MOS tube is connected to the other end of the second resistor, and the source of the fourth MOS tube is connected to the other end of the third resistor; one end of the first current source, one end of the second current source, the source of the sixth MOS tube and the source of the seventh MOS tube are all connected to the power supply end; the other end of the first current source is connected to the drain of the third MOS tube, and the other end of the second current source is connected to the drain and the gate of the fourth MOS tube; the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, the drain of the fifth MOS tube is connected to the gate and the drain of the sixth MOS tube, the source of the fifth MOS tube is connected to the other end of the third resistor, and the gate of the fifth MOS tube is connected to the other end of the first current source; the size ratio of the sixth MOS tube is the same as that of the seventh MOS tube.

[0043] In the embodiment of the present invention, reference Figure 3 The common-gate amplifier circuit includes: a first current source I1, a second current source I2, a third MOS tube M11, a fourth MOS tube M12, a fifth MOS tube M13, a sixth MOS tube M14 and a seventh MOS tube M15, wherein the current source I1 and the current source I2 can provide a stable current, one end of the current source I1 is connected to the positive electrode LVGLP5 of the power supply, and the other end is connected to the drain of the third MOS tube, so that the current of the current source flows to the negative end of the power supply through the third MOS tube M11. Similarly, one end of the current source I2 is connected to the positive electrode LVGLP5 of the power supply, and the other end is connected to the drain of the fourth MOS tube M13, so that the current of the current source I2 flows to the negative end of the power supply through the fourth MOS tube M12. The size ratio of the sixth MOS tube M14 is the same as that of the seventh MOS tube M15. The sixth MOS tube M14 and the seventh MOS tube M15 form a current mirror, wherein the current output by the seventh MOS tube M15 is the sampling current isns, then the current of the sixth MOS tube M14 is the same as the current of the seventh MOS tube M15, both are isns, the drain of the fifth MOS tube is connected to the gates of the sixth MOS tube M14 and the seventh MOS tube M15, and is connected to the drain of the sixth MOS tube M14, so that the current of the fifth MOS tube M13 is isns, and the current isns output by the fifth MOS tube flows to the negative end of the power supply through the third resistor R3, that is, the current flowing through the second resistor R3 is: the current isns flowing through the fifth MOS tube and the current I2 flowing through the fourth MOS tube M12, and it can be obtained that the voltage across the third resistor R3 is: (isns+I2)*R3.

[0044] Optionally, the inverter circuit includes: an eighth MOS tube, a ninth MOS tube and a NOT gate; the source of the eighth MOS tube is connected to the drain of the ninth MOS tube, the source of the ninth MOS tube is connected to the negative end of the power supply, and one end of the NOT gate is connected to the gate of the ninth MOS tube; the other end of the NOT gate, the gate and the drain of the eighth MOS tube are connected to the current output circuit.

[0045] In the embodiment of the present invention, the inverter circuit includes: an eighth MOS tube M9, a ninth MOS tube M10 and a NOT gate, wherein the source of the eighth MOS tube M9 is connected to the drain of the ninth MOS tube M10, and one end of the NOT gate is connected to the gate of the ninth MOS tube M10. Since the gate voltages of the eighth MOS tube M9 and the ninth MOS tube M10 are both the voltages for turning on the NMOS tube, and the NOT gate is connected in front of the ninth MOS tube M10, when the same gate voltage is provided, the eighth MOS tube M9 is turned on, and the ninth MOS tube M10 is turned off. At this time, the current passing through the second resistor R2 is the current of the current source I1, and the voltage across the second resistor R2 is I1*R2. The current flowing through the second resistor R2 passes through the eighth MOS tube M9 and the NMOS tube and finally flows to the negative power supply terminal LVGL. The current flowing through the NMOS terminal is represented by Iocp, and the voltage across the NMOS tube can be obtained as: Iocp*Rdson, where Rdson is the impedance value of the NMOS tube. Then, the source terminal voltage of M11 is the sum of the voltage across the second resistor R2 and the voltage across the NMOS tube, which can be expressed as: Iocp*Rdson+I1*R2.

[0046] Optionally, source terminal voltages of the third MOS tube and the fourth MOS tube are equal; the sampling current is a ratio of a product of a real-time current value output by the current output circuit and an impedance value of the current output circuit to a resistance value of the second resistor.

[0047] In the embodiment of the present invention, the source terminal voltages of the third MOS tube M11 and the fourth MOS tube M12 are equal, and the source terminal voltages of the third MOS tube M11 and the fourth MOS tube M12 can be regarded as the positive terminal voltage and the negative terminal voltage of the amplifier. Based on the circuit characteristics of the amplifier, the source terminal voltages of the third MOS tube M11 and the fourth MOS tube M12 are equal.

[0048] Combined with the above analysis, the source voltage of the third MOS tube M11 is Iocp*Rdson+I1*R2, and the source voltage of the fourth MOS tube M12 is: (isns+I2)*R3, then the expression is: Iocp*Rdson+I1*R2=(isns+I2)*R3. Among them, the resistance values ​​of the second resistor R2 and the third resistor R3 are the same, both expressed as R, then the above expression can be sorted out as: isns=locp*Rdson / R. That is, the sampling current is the ratio of the product of the real-time current value output by the current output circuit and the impedance value of the current output circuit to the resistance value of the second resistor.

[0049] Optionally, the reference current is the ratio of the product of the preset input current and the impedance value of the current output circuit (k times) to the resistance value of the first resistor; wherein k is obtained by the number and width-to-length ratio of the second MOS tubes.

[0050] In the embodiment of the present invention, combined with the above analysis, it can be known that the expression of the reference current is: Iref <1> =Iref <2> =Iref <n>=iref_trim*k*Rdson / R1, where iref_trim is the preset input current, k*Rdson is the impedance value of the second MOS tube, and k is obtained by the number and width-to-length ratio of the second MOS tube. If the second MOS tube is Figure 1 The NMOS tubes in the figure are NMOS tubes with the same specifications, so the width-to-length ratio of the second MOS tube is Figure 1 The width-to-length ratio of the NMOS tubes in the same, at this time, the second MOS tube and the NMMOS tube have the same impedance value. When four NMOS tubes are connected in series, the impedance value after series connection is Figure 1 4 times the impedance value of the NMOS tube in the input circuit, then k is 4. Here, four second MOS tubes are connected in series only as an example. It can be seen from the above reference current formula that the number of second MOS tubes connected in series and the width-to-length ratio affect the magnitude of the output reference current. Therefore, the output reference current can be adjusted by adjusting the number and the width-to-length ratio of the second MOS tubes to achieve adjustment of the reference current to adapt to the overcurrent protection requirements of the current output circuit in different scenarios. Similarly, the reference current can be adjusted by adjusting the preset input current and the resistance value of the first resistor R1. In actual use, one or more parameters affecting the reference current can be adjusted, and the embodiments of the present application are not limited here.

[0051] Furthermore, when the sampling current is equal to the reference current, the real-time current value Iocp output by the current output circuit is equal to the overcurrent threshold value Iocp ’ According to the relationship between the reference current isns obtained above and the real-time current value output by the current output circuit: isns = locp*Rdson / R, the overcurrent threshold Iocp of the current output circuit can be obtained. ’ The expression is:

[0052] Let isns = Iref <1> , then

[0053]

[0054] Iocp'=iref_trim*k*R / R1

[0055] According to the above expression, the overcurrent threshold of the current output circuit is related to the size of the preset input current iref_trim, k, the resistance R of the second resistor and the third resistor, and the first resistor R1. The overcurrent threshold of the current output circuit can be changed by adjusting any of the parameters of the preset input current iref_trim, k, the resistance R of the second resistor and the third resistor, and the first resistor R1. Specifically, since the size of iref_trim, k, and R1 can affect the size of the reference current, the adjustment of the parameters affecting the reference current can change the size of the reference current. If the size of the reference current changes, the overcurrent threshold of the current output circuit will change. That is, the present application can ensure the accuracy of the overcurrent threshold Iocp' by adjusting any one or any combination of parameters of iref_trim, k, the resistance R of the second resistor and the third resistor, and the first resistor R1, so that in actual application, the overcurrent threshold of the current output circuit can be adjusted according to different requirements.

[0056] Therefore, when laying out the circuit, ensuring the layout matching of the high-voltage tubes M1-M4 and the NMOS tube and the matching of the resistors R1, R2 and R3 can ensure the sampling accuracy of the NMOS tube, so that in the case of a multi-channel current output circuit, only one common reference current generation module can be set to generate multiple reference current values, meet the protection of the multi-channel current output current, and reduce the circuit area.

[0057] Optionally, the current output circuit includes a MOS tube to be protected and a driving circuit; the MOS tube to be protected and the driving circuit included in multiple current output circuits are the same; the gate of the MOS tube to be protected is connected to the driving circuit; the driving circuit is used to drive the MOS tube to be protected to be turned on; the MOS tube to be protected is connected to the current detection module, and the current detection module is used to sample the real-time current value flowing through the MOS tube to be protected to obtain a sampling current, and compare the sampling current of the MOS tube to be protected with a reference current, and when the comparison result is that the sampling current is greater than the reference current, stop the driving circuit from driving the MOS tube to be protected to be turned on.

[0058] In the embodiment of the present invention, reference Figure 1 The current output circuit includes a MOS tube to be protected and a driving circuit. Multiple current output circuits all include the same MOS tube to be protected and the driving circuit. The MOS tube to be protected is Figure 1 The NMOS tube in the embodiment of the present invention is a logic drive circuit and an amplifier for driving the NMOS tube. The amplifier is used to amplify the logic drive signal output by the logic drive circuit and input it into the NMOS tube to drive the NMOS tube to be turned on. The MOS tube to be protected is connected to the current detection module. The current detection module is used to sample the real-time current value flowing through the MOS tube to be protected to obtain a sampled current, and compare the sampled current of the MOS tube to be protected with a reference current. When the comparison result is that the sampled current is greater than the reference current, the comparison result is fed back to the current output circuit, so that the drive circuit in the current input circuit stops driving the MOS tube to be protected to be turned on, so as to realize overcurrent protection for the MOS tube to be protected.

[0059] In summary, the overcurrent protection circuit disclosed in the embodiment of the present application is applied to at least two current output circuits, and the overcurrent protection circuit includes: at least two current detection modules, and a common reference current generating module; the current detection module is connected to the current output circuit correspondingly, and the current detection module is used to sample the real-time current value output by the current output circuit to obtain a sampled current; the output end of the common reference current generating module is respectively connected to each of the current detection modules; the common reference current generating module is used to generate at least two reference currents, and provide a reference current for each current detection module; the current detection module is also used to compare the sampled current with the reference current, and perform circuit protection based on the comparison result. In the circuit of the present application, each current output circuit is correspondingly provided with a current detection module to sample the real-time current value output to obtain a sampled current, and the multi-channel current output circuit is only provided with a common reference current generating module. For the multi-channel current output circuit, only one common reference current generating module needs to be adjusted, and multiple reference currents are generated by one common reference current generating module, which is used to perform overcurrent protection on the multi-channel current output circuit, thereby reducing the area of ​​the circuit generating the reference current and saving the device layout cost.

[0060] refer to Figure 4 , Figure 4 An overcurrent protection method provided in an embodiment of the present application is shown, which is applied to the overcurrent protection circuit as described above, and the method includes:

[0061] Step 101, obtaining a sampled current obtained by sampling a real-time current value output by a current output circuit by a current detection module, and obtaining a reference current corresponding to each current output circuit generated by a common reference current generation module;

[0062] Step 102, for each current output circuit, compare the sampled current with the reference current to obtain a comparison result;

[0063] Step 103: Perform circuit protection according to the comparison result.

[0064] Optionally, step 103 includes:

[0065] Sub-step 1031 , when the comparison result is that the sampled current is greater than the reference current, cutting off the current output of the current output circuit.

[0066] In an embodiment of the present invention, for steps 101 to 103, for the overcurrent protection method of the overcurrent protection circuit, a sampling current obtained by sampling the real-time current value output by the current output circuit by the current detection module, and a reference current corresponding to each current output circuit generated by a common reference current generating module can be obtained. For each current output circuit, the sampling current and the reference current are compared to obtain a comparison result, and the comparison result is fed back to the current output circuit, thereby controlling the current output circuit to cut off the current output, thereby realizing overcurrent protection for the current output circuit.

[0067] Optionally, the method further comprises:

[0068] Step 104, in response to a first adjustment operation, adjusting the output value of the reference current;

[0069] Optionally, step 104 includes:

[0070] Sub-step 1041, in response to adjusting any one or more parameters of a preset input current, k, and the resistance value of the first resistor, adjusting the output value of the reference current; wherein k is obtained by the number and width-to-length ratio of the second MOS tubes.

[0071] In the embodiment of the present invention, with respect to step 104 and sub-step 1041, combined with the above analysis, it can be known that the expression of the reference current is: Iref <1> =Iref <2> =Iref <n>=iref_trim*k*Rdson / R1, wherein iref_trim is a preset input current, k*Rdson is an impedance value of the second MOS tube, and k is obtained by the number and width-to-length ratio of the second MOS tubes. Therefore, the output reference current can be adjusted by adjusting the number and width-to-length ratio of the second MOS tubes, and the adjustment of k*Rdson can be achieved, thereby achieving the adjustment of the reference current to adapt to the overcurrent protection requirements of the current output circuit in different scenarios. Similarly, the reference current can be adjusted by adjusting the preset input current size and the resistance value of the first resistor R1. In actual use, one or more parameters affecting the reference current size can be adjusted, and the embodiments of the present application are not limited here.

[0072] Step 105: In response to the second adjustment operation, adjust the sampling accuracy of the sampled current.

[0073] Optionally, step 105 includes:

[0074] Sub-step 1051, in response to the adjustment of any one or more parameters of the preset input current, k, the resistance value of the second resistor, and the resistance value of the first resistor, the accuracy of the sampling current is adjusted, wherein k is obtained by the number and the width-to-length ratio of the second MOS tubes.

[0075] In the embodiment of the present invention, for step 104 and sub-step 1041, when the sampled current is equal to the reference current, the real-time current value Iocp output by the current output circuit is equal to the overcurrent threshold value Iocp ’ , the relationship between the sampling current and the real-time current value output by the current output circuit: isns = locp * Rdson / R, when isns = Iref <1> When Iocp'=iref_trim*k*R / R1. The sampling current can be adjusted by adjusting the overcurrent threshold Iocp', that is, adjusting any one or more of the preset input currents iref_trim, k, R, and R1 to adjust the accuracy of the sampling current.

[0076] In summary, the overcurrent protection circuit disclosed in the embodiment of the present application is applied to at least two current output circuits, and the overcurrent protection circuit includes: at least two current detection modules, and a common reference current generating module; the current detection module is connected to the current output circuit correspondingly, and the current detection module is used to sample the real-time current value output by the current output circuit to obtain a sampled current; the output end of the common reference current generating module is respectively connected to each of the current detection modules; the common reference current generating module is used to generate at least two reference currents, and provide a reference current for each current detection module; the current detection module is also used to compare the sampled current with the reference current, and perform circuit protection based on the comparison result. In the circuit of the present application, each current output circuit is correspondingly provided with a current detection module to sample the real-time current value output to obtain a sampled current, and the multi-channel current output circuit is only provided with a common reference current generating module. For the multi-channel current output circuit, only one common reference current generating module needs to be adjusted, and multiple reference currents are generated by one common reference current generating module, which is used to perform overcurrent protection on the multi-channel current output circuit, thereby reducing the area of ​​the circuit generating the reference current and saving the device layout cost.

[0077] Reference Figure 5 An embodiment of the present application also provides an electronic device, which includes an overcurrent protection circuit.

[0078] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the embodiment implemented by the above-mentioned overcurrent protection circuit are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0079] The embodiment of the present application also provides a computer program product, which is executed by a processor to implement the various processes of the embodiment implemented by the above-mentioned overcurrent protection method, and can achieve the same technical effect. To avoid repetition, it is not repeated here. The computer program product can be stored in a storage medium.

[0080] In summary, the overcurrent protection circuit provided in the embodiments of the present application may be a chip or a chip system.

[0081] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0082] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.< / n> < / n> < / n>

Claims

1. An overcurrent protection circuit, applied to at least two current output circuits, characterized in that: The overcurrent protection circuit comprises: at least two current detection modules and a common reference current generation module; The current detection module is correspondingly connected to the current output circuit, and the current detection module is used to sample the real-time current value output by the current output circuit to obtain a sampled current; The output end of the common reference current generating module is respectively connected to each of the current detection modules; the common reference current generating module is used to generate at least two reference currents and provide one reference current for each of the current detection modules; the current detection module is also used to compare the sampled current with the reference current and perform circuit protection based on the comparison result.

2. The circuit according to claim 1, characterized in that The common reference current generating module comprises a voltage conversion unit and a reference current output unit; The voltage conversion unit is used to convert a preset input current into a reference voltage, and the reference current output unit is used to generate a reference current based on the reference voltage and convert the reference current into multiple identical reference currents.

3. The circuit according to claim 2, characterized in that The reference current output unit includes: a first resistor, a first MOS tube and a current mirror unit; The source of the first MOS tube is connected to one end of the first resistor, the drain of the first MOS tube is connected to the current mirror unit, the gate of the first MOS tube is connected to the output end of the voltage conversion unit, and the other end of the first resistor is grounded.

4. The circuit according to claim 3, characterized in that The current mirror unit comprises: a plurality of current mirror branches connected in parallel; the number of the current mirror branches is the same as the number of the current output circuit; The multiple current mirror branches are used to output multiple identical reference currents.

5. The circuit according to claim 3, characterized in that The voltage conversion unit comprises: a plurality of second MOS tubes and operational amplifiers connected in series in sequence; The inverting input terminal of the operational amplifier is connected to one end of the first resistor, and the output terminal of the operational amplifier is connected to the gate of the first MOS tube; The drain of the first second MOS transistor among the plurality of second MOS transistors connected in series is connected to the non-inverting input terminal of the operational amplifier, and the drain of the first second MOS transistor is also used to receive a preset input current; the plurality of second MOS transistors connected in series are used to convert the preset input current into a reference voltage and input it into the non-inverting input terminal of the operational amplifier; The source of the last second MOS tube among the plurality of second MOS tubes connected in series in sequence is grounded; The gate of each of the second MOS tubes is connected to the power supply terminal.

6. The circuit according to claim 1, characterized in that The current detection module comprises: a sampling circuit and a comparator, wherein the positive end of the comparator is connected to the sampling circuit, the negative end of the comparator is connected to the common reference current generating module, and the output end of the comparator is connected to the input end of the current output circuit; The sampling circuit is used to sample the real-time current value output by the current output circuit to obtain a sampled current; The comparator is used to compare the sampling current with a reference current generated by the common reference current generating module, and feed back the comparison result to the input end of the current output circuit to control the working state of the current output circuit.

7. The circuit according to claim 6, characterized in that The sampling circuit comprises: an inverter circuit, a second resistor, a third resistor and a common-gate amplifier circuit; The input end of the inverter circuit is connected to the current output circuit, the output end of the inverter circuit is connected to one end of the second resistor, and the other end of the second resistor is connected to the first end of the common-gate amplifier circuit; One end of the third resistor is connected to the negative end of the power supply, and the other end of the third resistor is connected to the second end of the common-gate amplifier circuit; the second resistor is the same as the third resistor; and the third end of the common-gate amplifier circuit outputs a sampling current.

8. The circuit according to claim 7, characterized in that The common-gate amplifier circuit comprises: a first current source, a second current source, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor; the first current source is the same as the second current source; The gate of the third MOS tube is connected to the gate of the fourth MOS tube, the source of the third MOS tube is connected to the other end of the second resistor, and the source of the fourth MOS tube is connected to the other end of the third resistor; One end of the first current source, one end of the second current source, the source of the sixth MOS transistor and the source of the seventh MOS transistor are all connected to the power supply end; The other end of the first current source is connected to the drain of the third MOS transistor, and the other end of the second current source is connected to the drain and gate of the fourth MOS transistor; The gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, the drain of the fifth MOS tube is connected to the gate and drain of the sixth MOS tube, the source of the fifth MOS tube is connected to the other end of the third resistor, and the gate of the fifth MOS tube is connected to the other end of the first current source; the size ratio of the sixth MOS tube is the same as that of the seventh MOS tube.

9. The circuit according to claim 7, characterized in that The inverter circuit comprises: an eighth MOS tube, a ninth MOS tube and a NOT gate; The source of the eighth MOS tube is connected to the drain of the ninth MOS tube, the source of the ninth MOS tube is connected to the negative end of the power supply, and one end of the NOT gate is connected to the gate of the ninth MOS tube; The other end of the NOT gate, the gate and the drain of the eighth MOS tube are connected to the current output circuit.

10. The circuit according to claim 8, characterized in that The source terminal voltages of the third MOS tube and the fourth MOS tube are equal; The sampling current is the ratio of the product of the real-time current value output by the current output circuit and the impedance value of the current output circuit to the resistance value of the second resistor.

11. The circuit according to claim 5, characterized in that The reference current is the ratio of the product of the preset input current and the impedance value of the current output circuit (k times) to the resistance value of the first resistor; wherein k is obtained by the number and width-to-length ratio of the second MOS tubes.

12. The circuit according to claim 1, characterized in that The current output circuit comprises a MOS tube to be protected and a driving circuit; the MOS tube to be protected and the driving circuit comprised by the multiple current output circuits are the same; The gate of the MOS tube to be protected is connected to the driving circuit; The driving circuit is used to drive the MOS tube to be protected to be turned on; The MOS tube to be protected is connected to the current detection module, and the current detection module is used to sample the real-time current value flowing through the MOS tube to be protected to obtain a sampling current, and compare the sampling current of the MOS tube to be protected with a reference current, and when the comparison result is that the sampling current is greater than the reference current, stop the driving circuit from driving the MOS tube to be protected to turn on.

13. An overcurrent protection method, applied to the overcurrent protection circuit according to any one of claims 1 to 12, characterized in that: The method comprises: Acquire a sampled current obtained by sampling the real-time current value output by the current output circuit by the current detection module, and acquire a reference current corresponding to each current output circuit generated by a common reference current generation module; For each current output circuit, compare the sampled current with the reference current to obtain a comparison result; Circuit protection is performed according to the comparison result.

14. The method according to claim 13, characterized in that The performing circuit protection according to the comparison result comprises: When the comparison result is that the sampling current is greater than the reference current, the current output of the current output circuit is cut off.

15. The method according to claim 13, characterized in that The method further comprises: In response to a first adjustment operation, adjusting an output value of the reference current; In response to the second adjustment operation, the sampling accuracy of the sampled current is adjusted.

16. The method according to claim 15, characterized in that The step of adjusting the output value of the reference current in response to the first adjustment operation comprises: In response to the adjustment of any one or more parameters of the preset input current, k, and the resistance value of the first resistor, the output value of the reference current is adjusted; wherein k is obtained by the number and width-to-length ratio of the second MOS tubes.

17. The method according to claim 15, characterized in that In response to the second adjustment operation, adjusting the accuracy of the sampling current includes: In response to the adjustment of any one or more parameters of the preset input current, k, the resistance value of the second resistor, and the resistance value of the first resistor, the accuracy of the sampling current is adjusted, wherein k is obtained by the number and the width-to-length ratio of the second MOS tubes.

18. An electronic device, characterized in that: The electronic device comprises: an overcurrent protection circuit as described in any one of claims 1-12.

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