Illegal switching suppression method for switching state of three-level converter and storage medium

Abstract

The invention discloses a method for inhibiting illegal switching of a switching state of a three-level converter and a storage medium. Comprises: acquiring an initial pulse signal; if the initial pulse signal comprises a continuous narrow pulse, the pulse width of a first narrow pulse with a previous time sequence is extended to a first pulse width, a second narrow pulse with a later time sequence is inserted behind the first narrow pulse, a target pulse signal is obtained, and the pulse width of the continuous narrow pulse is smaller than the minimum pulse width threshold value of a power switch of the three-level converter; and controlling output level state switching of a single-phase bridge arm of the three-level converter through the target pulse signal. While minimum pulse width suppression is realized, loss of pulse signals and illegal switching of level states are avoided.

Description

Technical Field

[0001] The invention relates to the technical field of pulse modulation, and in particular to a method and a storage medium for suppressing illegal switching of a switch state of a three-level converter. Background Art

[0002] In AC / DC power conversion applications, modulation waves and carrier waves are usually used to generate pulse signals. By controlling the output level state switching of the single-phase bridge arm of the three-level converter, minimum pulse width suppression is one of the effective means to protect power devices.

[0003] In some pulse width modulation strategies, multiple narrow pulses with narrow pulse widths may appear continuously near the zero point of the modulation wave, and the sum of the pulse widths of two adjacent narrow pulses is less than the minimum on-time or off-time required by the power device. When the first narrow pulse is extended to the minimum on-time or off-time required by the power device, the subsequent narrow pulse will be lost, and the level state switching will enter an illegal switching state, causing the converter to lock. Summary of the invention

[0004] In order to solve the above problems, the inventors have made the present invention, and provide a method and storage medium for suppressing illegal switching of the switch state of a three-level converter through specific implementation methods.

[0005] In a first aspect, an embodiment of the present invention provides a method for suppressing illegal switching of a switch state of a three-level converter, comprising:

[0006] Obtaining an initial pulse signal;

[0007] If the initial pulse signal includes continuous narrow pulses, the pulse width of a first narrow pulse in front of the timing sequence is extended to the first pulse width, and a second narrow pulse in the back of the timing sequence is inserted behind the first narrow pulse to obtain a target pulse signal, wherein the pulse width of the continuous narrow pulses is less than the minimum pulse width threshold of the power switch of the three-level converter;

[0008] The output level state switching of the single-phase bridge arm of the three-level converter is controlled by the target pulse signal.

[0009] In a second aspect, an embodiment of the present invention provides a device for suppressing illegal switching of a switch state of a three-level converter, comprising:

[0010] A signal acquisition module, used for acquiring an initial pulse signal;

[0011] A signal processing module, configured to, if the initial pulse signal includes continuous narrow pulses, extend the pulse width of a first narrow pulse in front to the first pulse width, and insert a second narrow pulse in the back to the back of the first narrow pulse, to obtain a target pulse signal, wherein the pulse width of the continuous narrow pulses is less than a minimum pulse width threshold of a power switch of the three-level converter;

[0012] A signal output module is used to control the output level state switching of the single-phase bridge arm of the three-level converter through the target pulse signal.

[0013] The beneficial effects of the above technical solution provided by the embodiment of the present invention include at least:

[0014] By acquiring an initial pulse signal; if the initial pulse signal includes continuous narrow pulses, the pulse width of the first narrow pulse in front of the timing sequence is extended to the first pulse width, and the second narrow pulse in the back of the timing sequence is inserted behind the first narrow pulse to obtain a target pulse signal; the output level state switching of the single-phase bridge arm of the three-level converter is controlled by the target pulse signal, while achieving minimum pulse width suppression, the loss of pulse signals and illegal switching of level states are avoided.

[0015] Other features and advantages of the present invention will be described in the following description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0016] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0018] Figure 1 is a flow chart of a method in an embodiment of the present invention;

[0019] Figure 2 A circuit of a single-phase bridge arm of a three-level converter in an embodiment of the present invention;

[0020] Figure 3 is an action logic diagram of a power switch of a single-phase bridge arm in an embodiment of the present invention;

[0021] Figure 4 This is a working principle diagram of pulse width modulation in an embodiment of the present invention;

[0022] Figure 5 Schematic diagram of control logic of a single-phase bridge arm in an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of a pulse signal in an embodiment of the present invention;

[0024] Figure 7 is another schematic diagram of a pulse signal in an embodiment of the present invention;

[0025] Figure 8 The figure is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0027] Flexible converters represented by three-level converters are one of the core equipment of flexible distribution networks, used to achieve AC / DC power conversion. With the increase in the power level of flexible distribution systems, it is required to further improve the power level of flexible converters. One method is to use high-power switch IGBT or IGCT devices to build three-level converters and improve the power capacity of converters. For high-power power semiconductor devices represented by IGCT and IGBT, there are restrictions on their minimum on and minimum off time to ensure that they can be turned off and on safely and reliably. By controlling the output level state switching of the single-phase bridge arm of the three-level converter, minimum pulse width suppression is one of the effective means to protect power devices.

[0028] Near the zero point of the modulation wave, due to the small value of the modulation wave, the on or off time of the power device will be less than the minimum on or off time required by the power device. For this reason, the corresponding switch state action time is usually extended to reach the minimum on or off time required by the power device. This processing method is called minimum pulse width suppression.

[0029] In some pulse width modulation strategies, multiple narrow pulses with narrow pulse widths may appear continuously near the zero point of the modulation wave, and the sum of the pulse widths of two adjacent narrow pulses is less than the minimum on-time or off-time required by the power device. When the first narrow pulse is extended to the minimum on-time or off-time required by the power device, the subsequent narrow pulse will be lost, and the level state switching will enter an illegal switching state, causing the converter to lock.

[0030] In order to solve the problems existing in the prior art, embodiments of the present invention provide a method, device, electronic device and storage medium for suppressing illegal switching of a switch state of a three-level converter.

[0031] The embodiment of the present invention provides a method for suppressing illegal switching of the switch state of a three-level converter, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0032] Step S1: obtaining an initial pulse signal;

[0033] Among them, the initial pulse signal is generated by comparing the modulated wave and the carrier.

[0034] Step S2: If the initial pulse signal includes continuous narrow pulses, the pulse width of the first narrow pulse in front of the timing sequence is extended to the first pulse width, and the second narrow pulse in the back of the timing sequence is inserted behind the first narrow pulse to obtain the target pulse signal, wherein the pulse width of the continuous narrow pulse is less than the minimum pulse width threshold of the power switch of the three-level converter.

[0035] Among them, the continuous narrow pulses include a first narrow pulse that comes earlier in time sequence and a second narrow pulse that comes later in time sequence, and the first narrow pulse and the second narrow pulse are adjacent to each other, and the first pulse width is a preset value. When the pulse width of the first narrow pulse is the first pulse width, the duration of the output level state of the single-phase bridge arm of the three-level converter is greater than the minimum pulse width threshold.

[0036] Specifically, after the initial pulse signal is obtained, it is determined whether the initial pulse signal includes continuous narrow pulses based on the pulse width and the minimum pulse width threshold of the pulse in the initial pulse signal, and it is confirmed as a continuous narrow pulse, and the pulse with an earlier timing is confirmed as the first narrow pulse, and the pulse with a later timing is confirmed as the second narrow pulse; if the initial pulse signal includes continuous narrow pulses, the first narrow pulse is extended to the first pulse width, and the second narrow pulse is inserted behind the first narrow pulse, so that the output level state of the single-phase bridge arm of the three-level converter is switched from the level state corresponding to the first narrow pulse to the level state corresponding to the second narrow pulse, thereby avoiding the loss of the level state corresponding to the second narrow pulse.

[0037] Step S3: controlling the output level state switching of the single-phase bridge arm of the three-level converter by the target pulse signal.

[0038] In the above method of this embodiment, the step of obtaining the initial pulse signal comprises the following steps:

[0039] Obtain modulation wave information and carrier wave information;

[0040] An initial pulse signal is obtained according to the modulation wave information and the carrier wave information.

[0041] In the above method of this embodiment, if the initial pulse signal includes continuous narrow pulses, the pulse width of the first narrow pulse in the front sequence is extended to the first pulse width, and the second narrow pulse in the back sequence is inserted after the first narrow pulse to obtain the target pulse signal, including the following steps:

[0042] After the initial pulse signal is acquired, the initial pulse signal is stored to obtain a stored pulse signal.

[0043] If there are continuous narrow pulses in the initial pulse signal, the pulse width of the first narrow pulse preceding in time sequence is extended to the first pulse width to obtain a first target pulse signal;

[0044] Retrieving a second narrow pulse in the stored pulse signal, and inserting the second narrow pulse behind the first narrow pulse, and inserting the second pulse segment behind the first narrow pulse, to obtain a second target pulse signal;

[0045] The method of controlling the output level state switching of the single-phase bridge arm of the three-level converter by the target pulse signal comprises the following steps:

[0046] The output level state switching of the single-phase bridge arm of the three-level converter is controlled by the second target pulse signal.

[0047] In the above method of this embodiment, after the step of inserting the second narrow pulse with a later timing sequence behind the first narrow pulse, the method further includes the following steps:

[0048] The pulse width of the second narrow pulse is extended to a second pulse width.

[0049] The above method of this embodiment further includes the following steps:

[0050] Acquire control logic of the three-level converter, and acquire level state switching information when the output level state of the three-level converter switches;

[0051] The legality of the level state switching is determined according to the control logic and the level state switching information.

[0052] The level state switching information includes the output level state and the level state to be switched. The legality of the level state switching can be determined through the output level state, the level state to be switched and the control logic.

[0053] Specifically, when the output level state is switched to the level state to be switched, it complies with the control logic, and the level state switch is confirmed as a legal level state switch; if the output level state is switched to the level state to be switched, it does not comply with the control logic, and the level state switch is an illegal level state switch.

[0054] In the above method of this embodiment, if the level state is switched to an illegal zero state, the level state to be output is switched to a target level state according to the control logic.

[0055] In the above method of this embodiment, the first pulse width and the second pulse width are both minimum pulse width thresholds of the power switch of the three-level converter.

[0056] The above method of this embodiment obtains an initial pulse signal; if the initial pulse signal includes continuous narrow pulses, the pulse width of the first narrow pulse in the front sequence is extended to the first pulse width, and the second narrow pulse in the back sequence is inserted behind the first narrow pulse to obtain a target pulse signal; the output level state switching of the single-phase bridge arm of the three-level converter is controlled by the target pulse signal, while achieving minimum pulse width suppression, avoiding the loss of pulse signals and illegal switching of level states.

[0057] Those skilled in the art can change the above sequence without departing from the protection scope of the present disclosure.

[0058] For example, Figure 2 As shown in the single-phase bridge arm circuit diagram, the single-phase bridge arm of the three-level converter may include a capacitor C1, a capacitor C2, a power switch T1, a power switch T2, a power switch T3, a power switch T4, a power switch T5, a power switch T6, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5 and a diode D6, wherein the diode D1, the diode D2, the diode D3, the diode D4, the diode D5 and the diode D6 are respectively connected in anti-parallel with the power switch T1, the power switch T2, the power switch T3, the power switch T4, the power switch T5 and the power switch T6, The power switch T1, the power switch T2, the power switch T3 and the power switch T4 are connected in series in sequence, the collector of the power switch T5 is respectively connected to the emitter of the power switch T1 and the collector of the power switch T2, the emitter of the power switch T5 is respectively connected to the negative electrode of the capacitor C1, the positive electrode of the capacitor C2 and the collector of the power switch T6, the collector of the power switch T6 is respectively connected to the negative electrode of the capacitor C1 and the positive electrode of the capacitor C2, the positive electrode of the capacitor C1 is connected to the collector of the power switch T1, and the negative electrode of the capacitor C2 is connected to the emitter of the power switch T4.

[0059] The state of the power switch of the above single-phase bridge arm is as follows: Figure 3 As shown, the working principle is as follows Figure 4 As shown, the level states of the single-phase bridge arm include a positive level P, a first zero level OU1, a second zero level OU2, a negative level N, a third zero level OL1 and a fourth zero level OL2;

[0060] In the positive half cycle of voltage, when the modulation wave is greater than the upper carrier wave and the lower carrier wave, the power switch T1 and the power switch T2 are turned on, the power switch T3, the power switch T4, the power switch T5 and the power switch T6 are turned off, and the single-phase bridge arm outputs a positive level P.

[0061] In the positive half cycle of voltage, when the modulated wave is greater than the upper carrier wave and less than the lower carrier wave, the power switch T2 and the power switch T5 are turned on, the power switch T1, the power switch T3, the power switch T4 and the power switch T6 are turned off, and the single-phase bridge arm outputs the first zero level OU1.

[0062] When the modulated wave is smaller than the upper carrier wave and larger than the lower carrier wave, the power switches T2, T4 and T5 are turned on, the power switches T1, T3 and T6 are turned off, and the single-phase bridge arm outputs a second zero level OU2.

[0063] In the negative half cycle of the voltage, when the modulation wave is smaller than the upper carrier wave and the lower carrier wave, the power switches T3, T4 and T5 are turned on, the power switches T1, T2 and T6 are turned off, and the single-phase bridge arm outputs a negative level N.

[0064] In the negative half cycle of voltage, when the modulated wave is greater than the upper carrier wave and less than the lower carrier wave, the power switch T3 and the rate switch T6 are turned on, the power switch T1, the power switch T2, the power switch T4 and the power switch T5 are turned off, and the single-phase bridge arm outputs the third zero level OL1.

[0065] In the negative half cycle of voltage, when the modulated wave is smaller than the upper carrier wave and larger than the lower carrier wave, the power switch T1, the power switch T3 and the rate switch T6 are turned on, the power switch T2, the power switch T4 and the power switch T5 are turned off, and the single-phase bridge arm outputs the fourth zero level OL2.

[0066] The control logic of the above single-phase bridge arm is as follows Figure 5 As shown, when the level state to be output and the output level state do not match the control logic, it is confirmed that the level state switching is an illegal state switching.

[0067] like Figure 6 As shown in the modulation wave and carrier, when the modulation wave passes through the zero point, continuous short pulses will be generated, one narrow pulse corresponds to the high level P, and the other narrow pulse corresponds to the first zero level OU1. If the pulse width of the continuous short pulses is less than the minimum pulse width threshold, the duration of the high level P is extended to the minimum pulse width threshold, the duration of the first zero level OU1 is occupied, and the level state is switched to the third zero level OL1. Figure 5As known from the control logic in, the direct switching of the high level P to the third zero level OL1 is an illegal state transition; the target pulse signal can be obtained by extending the pulse width of the first narrow pulse in the front sequence to the first pulse width, and inserting the second narrow pulse in the back sequence behind the first narrow pulse, and the output level state switching of the single-phase bridge arm of the three-level converter is controlled by the target pulse signal, so that after the duration of the high level P is reached, it switches to the first zero level OU1, realizing the minimum pulse width suppression, avoiding the loss of the pulse signal and the illegal switching of the level state.

[0068] like Figure 7 As shown in the modulation wave and carrier, the zero crossing point of the modulation wave just falls on the intersection of the carrier, and an illegal switching of the modulation wave from the zero state of the positive half cycle to the zero state of the negative half cycle occurs. In this case, the fourth zero level OL2 is directly switched to the first zero level OL1, which will cause the converter to be locked and shut down; the control logic can be used to switch the output level state to the target level state, so that the modulation wave can smoothly transition from the positive half cycle to the negative half cycle.

[0069] Another embodiment of the present invention provides a device for suppressing illegal switching of a switch state of a three-level converter, comprising:

[0070] A signal acquisition module, used for acquiring an initial pulse signal;

[0071] A signal processing module, configured to, if the initial pulse signal includes continuous narrow pulses, extend the pulse width of a first narrow pulse in front to the first pulse width, and insert a second narrow pulse in the back to the back of the first narrow pulse, to obtain a target pulse signal, wherein the pulse width of the continuous narrow pulses is less than a minimum pulse width threshold of a power switch of the three-level converter;

[0072] A signal output module is used to control the output level state switching of the single-phase bridge arm of the three-level converter through the target pulse signal.

[0073] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0074] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, whose structure is as follows: Figure 8 As shown, it includes: a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, the above-mentioned method for suppressing illegal switching of the switch state of the three-level converter is implemented.

[0075] Based on the same inventive concept, an embodiment of the present invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and when the computer executable instructions are executed by a processor, the aforementioned method for suppressing illegal switching of the switch state of a three-level converter is implemented.

[0076] Any modifications, supplements and equivalent substitutions made within the scope of the principles of the present invention shall still fall within the patent scope of the present invention.

[0077] Unless otherwise stated, the "connection" mentioned above refers to a logical relationship of current transmission, and does not necessarily mean a direct electrical connection. At the same time, "first", "second", etc. do not indicate a sequence, but are only used to identify related units, devices, etc.

[0078] The present invention is not limited to the above voltage levels, which are merely voltage levels in the embodiments.

Claims

1. A method for suppressing illegal switching of switch states of a three-level converter, characterized in that: The following steps are involved: Obtaining an initial pulse signal; If the initial pulse signal includes continuous narrow pulses, the pulse width of a first narrow pulse in front of the timing sequence is extended to the first pulse width, and a second narrow pulse in the back of the timing sequence is inserted behind the first narrow pulse to obtain a target pulse signal, wherein the pulse width of the continuous narrow pulses is less than the minimum pulse width threshold of the power switch of the three-level converter; The output level state switching of the single-phase bridge arm of the three-level converter is controlled by the target pulse signal.

2. The method according to claim 1, characterized in that The step of obtaining the initial pulse signal comprises the following steps: Obtain modulation wave information and carrier wave information; An initial pulse signal is obtained according to the modulation wave information and the carrier wave information.

3. The method according to claim 2, characterized in that If the initial pulse signal includes continuous narrow pulses, the pulse width of the first narrow pulse in the front sequence is extended to the first pulse width, and the second narrow pulse in the back sequence is inserted behind the first narrow pulse to obtain the target pulse signal, including the following steps: After the initial pulse signal is acquired, the initial pulse signal is stored to obtain a stored pulse signal; If there are continuous narrow pulses in the initial pulse signal, the pulse width of the first narrow pulse preceding in time sequence is extended to the first pulse width to obtain a first target pulse signal; Retrieving a second narrow pulse in the stored pulse signal, and inserting the second narrow pulse behind the first narrow pulse, and inserting the second pulse segment behind the first narrow pulse, to obtain a second target pulse signal; The method of controlling the output level state switching of the single-phase bridge arm of the three-level converter by the target pulse signal comprises the following steps: The output level state switching of the single-phase bridge arm of the three-level converter is controlled by the second target pulse signal.

4. The method according to claim 1, characterized in that After the step of inserting the second narrow pulse with a later timing sequence behind the first narrow pulse, the method further comprises the following steps: The pulse width of the second narrow pulse is extended to a second pulse width.

5. The method according to claim 2, characterized in that The following steps are also included: Acquire control logic of the three-level converter, and acquire level state switching information when the output level state of the three-level converter switches; The legality of the level state switching is determined according to the control logic and the level state switching information.

6. The method according to claim 5, characterized in that The following steps are also included: If the level state is switched to an illegal zero state, the level state to be output is switched to a target level state according to the control logic.

7. The method according to claim 4, characterized in that The first pulse width and the second pulse width are both minimum pulse width thresholds of a power switch of a three-level converter.

8. A device for suppressing illegal switching of switch states of a three-level converter, characterized in that: include: A signal acquisition module, used for acquiring an initial pulse signal; A signal processing module, configured to, if the initial pulse signal includes continuous narrow pulses, extend the pulse width of a first narrow pulse in front to the first pulse width, and insert a second narrow pulse in the back to the back of the first narrow pulse, to obtain a target pulse signal, wherein the pulse width of the continuous narrow pulses is less than a minimum pulse width threshold of a power switch of the three-level converter; A signal output module is used to control the output level state switching of the single-phase bridge arm of the three-level converter through the target pulse signal.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, the method for suppressing illegal switching of the switch state of a three-level converter according to any one of claims 1 to 7 is implemented.

10. A computer storage medium, characterized in that: The computer storage medium stores computer executable instructions, and when the computer executable instructions are executed, the method for suppressing illegal switching of the switch state of the three-level converter according to any one of claims 1 to 7 is implemented.

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