Burr filtering circuit, method, equipment, medium and program product

Abstract

The invention discloses a burr filtering circuit, method and device, a medium and a program product, and the burr filtering circuit comprises a first time delay circuit which is used for delaying an input signal by a time delay width; the first logic gate circuit is used for filtering high-level burrs of which the width is smaller than or equal to the delay width in the input signal; the second logic gate circuit is used for filtering low-level burrs of which the width is smaller than or equal to the delay width in the input signal; the second delay circuit is used for delaying the input signal by two delay widths; the third logic gate circuit is used for ensuring that the signal with the length greater than two delay widths is not filtered; and the fourth logic gate circuit is used for outputting a target serial signal, and the target serial signal is a signal obtained by filtering high-level burrs and low-level burrs of which the widths are less than or equal to the delay width of the input signal and delaying for one delay width. The burr filtering circuit provided by the embodiment of the invention is simple in circuit structure, small in size, easy to change in filtering width and low in output delay.

Description

Technical Field

[0001] The present invention relates to the field of electronic related technologies, and in particular to a burr filtering circuit, method, device, medium and program product. Background Art

[0002] In the design and application of digital circuits, serial methods are widely used to transmit data. During serial data communication, the transmitter may generate glitches (instantaneous rapid changes or fluctuations in signals or parameters) during the signal transmission process due to environmental interference such as power supply noise, signal interference, and electromagnetic radiation. If the glitches are not properly handled, the receiver may easily receive erroneous data, resulting in communication failure and affecting communication quality.

[0003] The traditional method of filtering out glitches in digital circuits is generally to use several latches to sequentially latch the signal. When all the shift registers have the same value, it means that the signal is stable and the signal value is output at this time. If there is one bit different in all the shift registers, the original output remains unchanged. Using this method, the glitches can be filtered out, but because the length of the filtered glitches is related to the number of shift registers, the actual circuit volume is larger and the signal output delay is higher. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a burr filtering circuit with a simple circuit structure, a small volume, an easy-to-change filtering width, and a low output delay.

[0005] The present invention also provides a burr filtering method, an electronic device, a computer-readable storage medium and a computer program product.

[0006] A glitch filtering circuit according to an embodiment of the first aspect of the present invention includes: A first delay circuit having a first delay output terminal and a first delay input terminal for receiving an input signal, wherein the first delay circuit is used to delay the input signal by a delay width; A first logic gate circuit has a high-level filtering output terminal, a first high-level filtering input terminal for receiving the input signal, and a second high-level filtering input terminal connected to the first delay output terminal, wherein the first logic gate circuit is used to filter out high-level glitches in the input signal whose width is less than or equal to the delay width; A second logic gate circuit has a low-level filtering output terminal, a first low-level filtering input terminal for receiving the input signal, and a second low-level filtering input terminal connected to the first delay output terminal, and the second logic gate circuit is used to filter out low-level glitches in the input signal whose width is less than or equal to the delay width; A second delay circuit having a second delay output terminal and a second delay input terminal connected to the first delay output terminal, the second delay circuit being used to delay the input signal by two of the delay widths; A third logic gate circuit has a signal retention output terminal, a first signal retention input terminal connected to the second delay output terminal, and a second signal retention input terminal connected to the low level filtering output terminal, and the third logic gate circuit is used to ensure that a signal whose length is greater than two of the delay widths is not filtered out; The fourth logic gate circuit has a signal output terminal, a first signal input terminal connected to the high-level filtered output terminal, and a second signal input terminal connected to the signal retained output terminal, the signal output terminal is used to output a target serial signal, the target serial signal is the input signal from which high-level glitches and low-level glitches with a width less than or equal to the delay width have been filtered out, and the signal is delayed by one of the delay widths.

[0007] The burr filtering circuit according to the embodiment of the present invention has at least the following beneficial effects: After the input signal is delayed by a delay width through the first delay circuit, it is input into the first logic gate circuit at the same time as the original input signal to filter out high-level glitches in the input signal whose width is less than or equal to the delay width. After the input signal is delayed by a delay width through the first delay circuit, it is input into the second logic gate circuit at the same time as the original input signal to filter out low-level glitches in the input signal whose width is less than or equal to the delay width. Signals with a length greater than two delay widths are generally considered to be normal signals. After the input signal is delayed by two delay widths through the first delay circuit and the second delay circuit, it is input into the third logic gate circuit at the same time as the output signal of the second logic gate circuit to ensure that signals with a length greater than two delay widths are not filtered out. Finally, the fourth logic gate circuit can output high-level glitches and low-level glitches with a width less than or equal to the delay width that have been filtered out, and a signal with a delay width of one delay can be output. The glitch filtering circuit of the embodiment of the present invention has a simple circuit structure and a small volume. The filter width is easy to change by setting the delay width, and the output delay is low.

[0008] According to some embodiments of the present invention, the first logic gate circuit is an AND gate.

[0009] According to some embodiments of the present invention, the second logic gate circuit adopts an OR gate.

[0010] According to some embodiments of the present invention, the third logic gate circuit is an AND gate.

[0011] According to some embodiments of the present invention, the fourth logic gate circuit is an OR gate.

[0012] According to some embodiments of the present invention, the delay width is set to one tenth of the high level length or the low level length of the input signal.

[0013] According to a second aspect of the present invention, a burr filtering method includes: Obtaining an input signal sent by a transmitter; The input signal is respectively input to the first delay input terminal, the first high level filter input terminal and the first low level filter input terminal of the burr filtering circuit as described in the first aspect embodiment above, so that the burr filtering circuit filters out high level glitches and low level glitches whose width is less than or equal to the delay width in the input signal, and outputs the target serial signal through the signal output terminal after delaying for one of the delay width.

[0014] The burr filtering method according to the embodiment of the present invention has at least the following beneficial effects: After the input signal is delayed by a delay width through the first delay circuit, it is input into the first logic gate circuit at the same time as the original input signal to filter out high-level glitches in the input signal whose width is less than or equal to the delay width. After the input signal is delayed by a delay width through the first delay circuit, it is input into the second logic gate circuit at the same time as the original input signal to filter out low-level glitches in the input signal whose width is less than or equal to the delay width. Signals with a length greater than two delay widths are generally considered to be normal signals. After the input signal is delayed by two delay widths through the first delay circuit and the second delay circuit, it is input into the third logic gate circuit at the same time as the output signal of the second logic gate circuit to ensure that signals with a length greater than two delay widths are not filtered out. Finally, the fourth logic gate circuit can output high-level glitches and low-level glitches with a width less than or equal to the delay width that have been filtered out, and a signal with a delay width of one delay can be output. The glitch filtering method of the embodiment of the present invention has a simple circuit structure and a small volume. The filter width is easy to change by setting the delay width, and the output delay is low.

[0015] According to an embodiment of the third aspect of the present invention, an electronic device comprises one or more processors and a memory, wherein one or more programs are stored in the memory, and when the one or more programs are executed by the one or more processors, the one or more processors implement: the burr filtering method as described in the embodiment of the second aspect above. Since the electronic device adopts all the technical solutions of the burr filtering method of the above embodiment, it at least has all the beneficial effects brought by the technical solutions of the above embodiment.

[0016] According to the computer-readable storage medium of the fourth aspect of the present invention, a computer program is stored, and when the program is executed by a processor, the burr filtering method as described in the second aspect of the present invention is implemented. Since the computer-readable storage medium adopts all the technical solutions of the burr filtering method of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

[0017] A computer program product according to an embodiment of a fifth aspect of the present invention includes a computer program, and when the computer program is executed by a processor, the computer program implements: the burr filtering method as described in the embodiment of the second aspect. Since the computer program product adopts all the technical solutions of the burr filtering method of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

[0018] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a circuit schematic diagram of a burr filtering circuit according to an embodiment of the present invention; Figure 2 is a flow chart of a burr filtering method according to an embodiment of the present invention; Figure 3 is a signal waveform diagram after a burr filtering circuit according to an embodiment of the present invention; Figure 4 is a signal waveform diagram after a burr filtering circuit according to another embodiment of the present invention; Figure 5 FIG. 4 is a signal waveform diagram after a glitch filtering circuit according to another embodiment of the present invention.

[0020] Reference numerals: A first delay circuit 100; A first logic gate circuit 200; A second logic gate circuit 300; A second delay circuit 400; A third logic gate circuit 500; Fourth logic gate circuit 600 . DETAILED DESCRIPTION

[0021] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0022] In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0023] In the description of the present invention, it should be understood that descriptions involving orientation, such as orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0025] The following will be combined Figures 1 to 5 The burr filtering circuit of the embodiment of the present invention is described clearly and completely. Obviously, the embodiment described below is only a part of the embodiment of the present invention, not all the embodiments.

[0026] The glitch filtering circuit according to the first embodiment of the present invention includes a first delay circuit 100 , a first logic gate circuit 200 , a second logic gate circuit 300 , a second delay circuit 400 , a third logic gate circuit 500 and a fourth logic gate circuit 600 .

[0027] The first delay circuit 100 has a first delay output terminal and a first delay input terminal for receiving an input signal, and the first delay circuit 100 is used to delay the input signal by a delay width; The first logic gate circuit 200 has a high-level filtering output terminal, a first high-level filtering input terminal for receiving an input signal, and a second high-level filtering input terminal connected to the first delay output terminal, and the first logic gate circuit 200 is used to filter out high-level glitches in the input signal whose width is less than or equal to the delay width; The second logic gate circuit 300 has a low-level filtering output terminal, a first low-level filtering input terminal for receiving an input signal, and a second low-level filtering input terminal connected to the first delay output terminal, and the second logic gate circuit 300 is used to filter out low-level glitches in the input signal whose width is less than or equal to the delay width; The second delay circuit 400 has a second delay output terminal and a second delay input terminal connected to the first delay output terminal, and the second delay circuit 400 is used to delay the input signal by two delay widths; The third logic gate circuit 500 has a signal retention output terminal, a first signal retention input terminal connected to the second delay output terminal, and a second signal retention input terminal connected to the low level filtering output terminal. The third logic gate circuit 500 is used to ensure that a signal whose length is greater than two delay widths is not filtered out; The fourth logic gate circuit 600 has a signal output terminal, a first signal input terminal connected to the high-level filtered output terminal, and a second signal input terminal connected to the signal retained output terminal. The signal output terminal is used to output a target serial signal. The target serial signal is an input signal whose high-level glitches and low-level glitches with a width less than or equal to the delay width have been filtered out, and the signal is delayed by a delay width.

[0028] In some embodiments of the present invention, the width of the filtered glitch depends on the delay width of the first delay circuit 100 and the second delay circuit 400, and the maximum width of the filtered glitch is the delay width. It should be noted that the glitch filtering circuit of the embodiment of the present invention is generally suitable for low-speed peripheral communication circuits (signal frequency <1M), and the glitch width is much smaller than the input signal width. Signals with a width greater than the two delay widths can be regarded as normal signals and are not filtered.

[0029] In some embodiments of the present invention, reference Figures 3 to 5 The maximum delay width cannot exceed one-half of the high level or low level length of the input signal cycle, otherwise the signal will be filtered out as a glitch. The delay width can be set to one-tenth of the high level length or low level length of the input signal. It should be noted that the specific size of the delay width can be selected according to actual conditions and cannot be regarded as a limitation of the present invention.

[0030] In some embodiments of the present invention, reference Figure 1, the first logic gate circuit 200 uses an AND gate, the second logic gate circuit 300 uses an OR gate, the third logic gate circuit 500 uses an AND gate, and the fourth logic gate circuit 600 uses an OR gate. If the two input signals of the AND gate are 0 and 0 respectively, the output is 0, if the two input signals of the AND gate are 0 and 1 respectively, the output is 0, and if the two input signals of the AND gate are 1 and 1 respectively, the output is 1. Therefore, the first logic gate circuit 200 uses an AND gate to filter out high-level glitches, and the third logic gate circuit 500 ensures that signals with a length greater than two delay widths are not filtered out. If the two input signals of the OR gate are 0 and 0 respectively, the output is 0, if the two input signals of the OR gate are 0 and 1 respectively, the output is 1, and if the two input signals of the OR gate are 1 and 1 respectively, the output is 1. Therefore, the second logic gate circuit 300 uses an OR gate to filter out low-level glitches, and the fourth logic gate circuit 600 can obtain a signal with a high-level glitches and low-level glitches with a width less than or equal to the delay width that have been filtered out and a delay of one delay width.

[0031] It should be noted that both the AND gate and the OR gate can be obtained by combining components such as diodes, resistors, triodes, MOS tubes, etc., and the specific circuit structure is not specifically limited here.

[0032] In one embodiment of the present invention, when the burr width is T, Figure 1 As shown, the input signal is recorded as Din, a delay width is recorded as T, the input signal is recorded as Din_T after passing through the first delay circuit 100, Din and Din_T are recorded as Z1 after passing through the first logic gate circuit 200, Din and Din_T are recorded as Din_OR_T after passing through the second logic gate circuit 300, Din_T is recorded as Din_2T after passing through the second delay circuit 400, Din_2T and Din_OR_T are recorded as Z2 after passing through the third logic gate circuit 500, and Z1 and Z2 are recorded as Z after passing through the fourth logic gate circuit 600.

[0033] In the above embodiment, if Figure 3 As shown, the black part represents a high-level glitch. When the input signal Din enters the glitch filtering circuit of the embodiment of the present invention, it passes through the first delay circuit 100 to obtain Din_T, and Din_T passes through the second delay circuit 400 to obtain Din_2T. After Din_T and Din pass through the first logic gate circuit 200, Z1 is obtained. Figure 3It can be seen that Z1 has filtered out high-level glitches. After Din_T and Din pass through the second logic gate circuit 300, Din_OR_T is obtained. After Din_OR_T and Din_2T pass through the third logic gate circuit 500, Z2 is obtained. At this time, Z2 also filters out high-level glitches and can ensure that signals with a length greater than 2T are not filtered out. Finally, Z1 and Z2 pass through the fourth logic gate circuit 600 to obtain the final Z. Z is delayed by one T relative to Din and high-level glitches are filtered out.

[0034] In the above embodiment, if Figure 4 As shown, the black part represents a low-level glitch. When the input signal Din enters the glitch filtering circuit of the embodiment of the present invention, it passes through the first delay circuit 100 to obtain Din_T, and Din_T passes through the second delay circuit 400 to obtain Din_2T. After Din_T and Din pass through the second logic gate circuit 300, Din_OR_T is obtained. Figure 4 It can be seen that Din_OR_T has filtered out low-level glitches. After Din_T and Din pass through the first logic gate circuit 200, Z1 is obtained. After Din_OR_T and Din_2T pass through the third logic gate circuit 500, Z2 is obtained. Finally, Z1 and Z2 pass through the fourth logic gate circuit 600 to obtain the final Z. At this time, Z is delayed by one T relative to Din, and low-level glitches are filtered out.

[0035] In another embodiment of the present invention, Figure 5 As shown, when the burr width is 1.5T, the final Z is delayed by one T relative to Din, and some high-level burrs and some low-level burrs are filtered out. It can be understood that if the burr width is greater than T and less than 2T, a part of the burrs can be filtered out by the burr filtering circuit of the embodiment of the present invention, and the low-level burrs are filtered out from the burr head by a width of one T, and the high-level burrs are filtered out from the middle of the burr by a length of (2T-burr width). In the case where the burr width is greater than T, the burrs can be finally filtered out by linking multiple levels of burr filtering circuits of the embodiment of the present invention, and the specific principles and processes will not be repeated here.

[0036] According to the glitch filtering circuit of the embodiment of the present invention, after the input signal is delayed by a delay width through the first delay circuit 100, it is simultaneously input into the first logic gate circuit 200 with the original input signal to filter out high-level glitches in the input signal whose width is less than or equal to the delay width. After the input signal is delayed by a delay width through the first delay circuit 100, it is simultaneously input into the second logic gate circuit 300 with the original input signal to filter out low-level glitches in the input signal whose width is less than or equal to the delay width. Signals with a length greater than two delay widths are generally considered to be normal signals. After the input signal is delayed by two delay widths through the first delay circuit 100 and the second delay circuit 400, it is simultaneously input into the third logic gate circuit 500 with the output signal of the second logic gate circuit 300 to ensure that signals with a length greater than two delay widths are not filtered out. Finally, the fourth logic gate circuit 600 can output a signal with a high-level glitches and low-level glitches whose width is less than or equal to the delay width and a delay of one delay width. The burr filtering circuit of the embodiment of the present invention has a simple circuit structure and a small volume. The filter width can be easily changed by setting the delay width, and the output delay is low.

[0037] According to a second aspect of the present invention, a burr filtering method includes: Obtaining an input signal sent by a transmitter; The input signal is respectively input to the first delay input terminal, the first high level filter input terminal and the first low level filter input terminal of the burr filtering circuit as in the first aspect embodiment described above, so that the burr filtering circuit filters out high level glitches and low level glitches whose width is less than or equal to the delay width in the input signal, and outputs the target serial signal through the signal output terminal after delaying for a delay width.

[0038] The burr filtering circuit in the embodiment of the present invention is arranged at the receiving end, and after acquiring the input signal sent by the sending end, the input signal is input into the burr filtering circuit to filter out the burrs.

[0039] Since the burr filtering method of the embodiment of the present invention adopts all the technical solutions of the burr filtering circuit of the above embodiment, it at least has all the beneficial effects brought by the technical solutions of the above embodiment, which will not be described in detail here.

[0040] According to the glitch filtering method of the embodiment of the present invention, after the input signal is delayed by a delay width through the first delay circuit 100, it is simultaneously input into the first logic gate circuit 200 with the original input signal to filter out high-level glitches in the input signal whose width is less than or equal to the delay width. After the input signal is delayed by a delay width through the first delay circuit 100, it is simultaneously input into the second logic gate circuit 300 with the original input signal to filter out low-level glitches in the input signal whose width is less than or equal to the delay width. Signals with a length greater than two delay widths are generally considered to be normal signals. After the input signal is delayed by two delay widths through the first delay circuit 100 and the second delay circuit 400, it is simultaneously input into the third logic gate circuit 500 with the output signal of the second logic gate circuit 300 to ensure that signals with a length greater than two delay widths are not filtered out. Finally, the fourth logic gate circuit 600 can output a signal with a high-level glitches and low-level glitches whose width is less than or equal to the delay width and a delay of one delay width. The burr filtering method of the embodiment of the present invention has a simple circuit structure and a small volume. The filter width can be easily changed by setting the delay width, and the output delay is low.

[0041] An embodiment of the present invention further provides an electronic device, the electronic device comprising: one or more processors; A memory stores one or more programs, and when the one or more programs are executed by one or more processors, the one or more processors implement the burr filtering method provided by any embodiment of the present invention.

[0042] As a non-transient network system, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0043] The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory, and the processor is called to execute the methods of the embodiments of the present invention.

[0044] The processor can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present invention.

[0045] In some embodiments, the electronic device further comprises: Input / output interface, used to realize information input and output; Communication interface, used to realize communication interaction between this device and other devices. Communication can be realized through wired methods (such as USB, network cable, etc.) or wireless methods (such as mobile network, WIFI, Bluetooth, etc.); The bus, which transfers information between the various components of the device (such as the processor, memory, input / output interfaces, and communication interfaces); The processor, memory, input / output interface and communication interface can be connected to each other through a bus within the device.

[0046] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the burr filtering method provided by any embodiment of the present invention.

[0047] An embodiment of the present invention further provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the burr filtering method provided by any embodiment of the present invention.

[0048] The system architecture and application scenarios described in the embodiments of the present invention are intended to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided by the embodiments of the present invention are equally applicable to similar technical problems.

[0049] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0050] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0051] The above describes some embodiments of the present invention with reference to the accompanying drawings, but does not limit the scope of the present invention. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the present invention shall be within the scope of the present invention.

Claims

1. A glitch filtering circuit, characterized in that: include: A first delay circuit having a first delay output terminal and a first delay input terminal for receiving an input signal, wherein the first delay circuit is used to delay the input signal by a delay width; A first logic gate circuit has a high-level filtering output terminal, a first high-level filtering input terminal for receiving the input signal, and a second high-level filtering input terminal connected to the first delay output terminal, wherein the first logic gate circuit is used to filter out high-level glitches in the input signal whose width is less than or equal to the delay width; A second logic gate circuit has a low-level filtering output terminal, a first low-level filtering input terminal for receiving the input signal, and a second low-level filtering input terminal connected to the first delay output terminal, and the second logic gate circuit is used to filter out low-level glitches in the input signal whose width is less than or equal to the delay width; A second delay circuit having a second delay output terminal and a second delay input terminal connected to the first delay output terminal, the second delay circuit being used to delay the input signal by two of the delay widths; A third logic gate circuit has a signal retention output terminal, a first signal retention input terminal connected to the second delay output terminal, and a second signal retention input terminal connected to the low level filtering output terminal, and the third logic gate circuit is used to ensure that a signal whose length is greater than two of the delay widths is not filtered out; The fourth logic gate circuit has a signal output terminal, a first signal input terminal connected to the high-level filtered output terminal, and a second signal input terminal connected to the signal retained output terminal, the signal output terminal is used to output a target serial signal, the target serial signal is the input signal from which high-level glitches and low-level glitches with a width less than or equal to the delay width have been filtered out, and the signal is delayed by one of the delay widths.

2. The glitch filtering circuit according to claim 1, characterized in that: The first logic gate circuit adopts an AND gate.

3. The glitch filtering circuit according to claim 1, characterized in that: The second logic gate circuit is an OR gate.

4. The glitch filtering circuit according to claim 1, characterized in that: The third logic gate circuit adopts an AND gate.

5. The glitch filtering circuit according to claim 1, characterized in that: The fourth logic gate circuit adopts an OR gate.

6. The glitch filtering circuit according to claim 1, characterized in that: The delay width is set to one tenth of the high level length or low level length of the input signal.

7. A burr filtering method, characterized in that: include: Obtaining an input signal sent by a transmitter; The input signal is respectively input to the first delay input terminal, the first high level filter input terminal and the first low level filter input terminal of the glitch filtering circuit as described in any one of claims 1 to 6, so that the glitch filtering circuit filters out high level glitches and low level glitches with a width less than or equal to the delay width in the input signal, and outputs the target serial signal through the signal output terminal after delaying for one of the delay width.

8. An electronic device comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement: the burr filtering method as claimed in claim 7.

9. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the burr filtering method according to claim 7 is implemented.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the burr filtering method according to claim 7 is implemented.

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