Multiplexing circuit, polling scheduler and chip
By hierarchical two-choice one-unit network processing request sources in parallel, the problem of too long timing path of Find Frist One circuit is solved, and system performance and scalability are improved.
Patent Information
- Application Number
- CN202411272329.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2025-01-10
AI Technical Summary
When the existing Find Frist One circuit processes multiple request sources, the timing path is too long, resulting in increased logic series, decreased clock frequency, and limited system performance.
A hierarchical two-choice unit network of multiplexed circuits is adopted to process multiple request sources in parallel with a tree structure, reduce the serial comparison series, and form a binary tree structure, and reduce the number of request sources per layer by half, and reduce the logical series.
It significantly reduces the time to find the first logic "1", improves scheduling efficiency, shortens timing path delays, supports more request sources without increasing delays, and ensures that the system is stable and fair when running at high speed.
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Figure CN119298902A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a multiplexing circuit, a polling scheduler and a chip. Background Art
[0002] Find First One circuit is a logic circuit used to find the first (or highest priority) logic "1" among multiple inputs and output the position of the logic "1". This circuit has many applications in digital systems, including interrupt processing, task scheduling, data selection, etc.
[0003] An example of a currently used Find First One circuit is Figure 1 As shown by Figure 1 It can be seen that the implementation of the Find FirstOne circuit is a serial structure. For an 8-bit binary sequence, each bit of the request source is compared one by one from high to low, until all request sources are traversed and the position of the first logic "1" starting from the low bit is found; the value of each bit in the binary sequence indicates whether the corresponding request source initiates a request, 1 indicates initiating a request, and 0 indicates not initiating a request; Figure 1 There are 8 request sources in total. The priority of the lower request source is higher than that of the higher request source. If bit0 is 1, the result (gnt) output by the Find Frist One circuit is bit0.
[0004] It is understandable that in Figure 1 In this serial structure, when the number of request sources is large, the timing path of the FindFrist One circuit will be very long. Logically speaking, if the number of request sources is N, then a serial N-1 level two-choice module is required to implement it, that is, the number of logic levels is N-1. Summary of the invention
[0005] The purpose of the present application is to propose a polling scheduler, an electronic device and a chip to optimize the timing path of a Find First One circuit and reduce the number of logic levels.
[0006] According to a first aspect of the present application, a multiplexing circuit is provided, comprising M layers of structures connected in sequence, each layer of the structure comprising a plurality of two-select-one units, the two-select-one units being used to select one of the request signals for output according to the signal value and priority of two input request signals; M is greater than or equal to 2;
[0007] The first layer structure includes N / 2 two-choice units, where N is the number of request sources participating in the scheduling, and N is greater than or equal to 4; the input of each two-choice unit of the first layer structure is the request signal of the two request sources corresponding thereto;
[0008] Except for the first layer structure, the number of two-choice units in each layer structure is 1 / 2 of the number of two-choice units in the previous layer structure, and the input of each two-choice unit in each layer structure is the output of the two two-choice units in the corresponding previous layer structure;
[0009] The last layer of structure includes a two-choice unit, and the output of the two-choice unit is used as the output of the multiplexing circuit.
[0010] The above-mentioned multiplexing circuit optimizes the timing path of the Find First One module by processing multiple request sources in parallel in a tree structure through a hierarchical two-choice unit network, thereby reducing the number of serial comparison levels required. In the traditional Find First One module, if the number of request sources is N, then a serial N-1 level two-choice unit is required to implement it. This is because in the traditional serial structure, each request source must be compared with the next request source in turn until the first logic "1" is found. In the above-mentioned multiplexing circuit, the request sources are divided into multiple groups, each group contains two request sources, and the request sources of each group are compared by a two-choice unit. In this way, there will be N / 2 two-choice units in the first layer. The output of each two-choice unit is then used as the input of the next layer, and so on, until there is only one two-choice unit left in the last layer. This structure forms a binary tree, in which each node represents a two-choice unit, and the leaf node of the tree represents the original request source. In this way, the multiplexing circuit converts the serial comparison process into a parallel comparison process. In each layer, half of the request sources are eliminated, so the number of logic levels is greatly reduced. For N request sources, only log2(N) layers of binary selection units are needed to find the first logic "1", because each layer halves the number of request sources. This structure reduces the number of logic levels and shortens the timing path, because multiple comparisons are performed in parallel rather than in series, which helps to increase the clock frequency of the circuit and thus improve the performance of the entire system, especially when there are a large number of request sources.
[0011] According to a second aspect of the present application, a polling scheduler is provided, comprising a recording module, a mask module, a two-choice module, a data output module, and a multiplexing circuit as described in the first aspect;
[0012] The recording module is used to record the last scheduling result;
[0013] The mask module is used to perform mask processing on the original scheduling request according to the last scheduling result to obtain a masked scheduling request; the original scheduling request includes request signals of N request sources;
[0014] The two-select-one module is used to process the input original scheduling request and the mask scheduling request, and when the mask scheduling request is valid, output the mask scheduling request to the multiplexing circuit; when the mask scheduling request is invalid, output the original scheduling request to the multiplexing circuit;
[0015] The multiplexing circuit is used to process the original scheduling request or the mask scheduling request output by the two-choice module to obtain the current scheduling result;
[0016] The data output module is used to select a request source data from multiple request source data for output according to the current scheduling result.
[0017] According to a third aspect of the present application, a polling scheduler is provided, comprising a scheduling result recording module, a mask module, a two-choice module, a data output module, a first multiplexing circuit and a second multiplexing circuit, wherein the first multiplexing circuit and the second multiplexing circuit are both the multiplexing circuits as described in the first aspect;
[0018] The scheduling result recording module is used to record the last scheduling result;
[0019] The mask module is used to perform mask processing on the original scheduling request according to the last scheduling result to obtain a masked scheduling request; the original scheduling request includes request signals of N request sources;
[0020] The first multiplexing circuit is used to process the input original scheduling request and output a first scheduling result to the two-select-one module;
[0021] The second multiplexing circuit is used to process the input mask scheduling request and output a second scheduling result to the two-select-one module;
[0022] The two-selection module is used to select and process the input first scheduling result and second scheduling result, and when the second scheduling result is valid, output the second scheduling result to the data output module; when the second scheduling result is invalid, output the first scheduling result to the data output module;
[0023] The data output module is used to select a request source data from a plurality of request source data for output according to the first scheduling result or the second scheduling result output by the two-selection module.
[0024] When the multiplexing circuit according to the first aspect is applied to the polling scheduler according to the second aspect or the third aspect, since the multiplexing circuit adopts a hierarchical two-choice unit network and can process multiple request sources in parallel, the time required to find the first logic "1" can be significantly reduced, so that the polling scheduler can more quickly determine which request source needs to be served, thereby improving the efficiency of scheduling. In a traditional polling scheduler, as the number of request sources increases, the delay of the timing path will also increase, which may lead to performance bottlenecks, while the tree structure of the multiplexing circuit reduces the number of logic levels, thereby shortening the critical timing path and reducing the delay, so that the polling scheduler can support more request sources without excessively increasing the delay. The recording module and the mask module in the polling scheduler can help avoid repeated service of the same request source, thereby improving the fairness and stability of the system and realizing polling scheduling. The combination of the fast response capability of the multiplexing circuit and the recording module and the mask module can ensure that the system can still maintain stable and fair scheduling when running at high speed. The design of the multiplexing circuit allows the polling scheduler to easily expand to more request sources. When the system needs to support more request sources, it only needs to increase the level of multiplexing circuits without completely redesigning the scheduler. Therefore, the application of multiplexing circuits enables the polling scheduler to remain efficient, stable and scalable when processing a large number of requests, which is crucial to improving the overall performance and reliability of complex systems.
[0025] According to a third aspect of the present application, a chip is provided, comprising the multiplexing circuit according to the first aspect.
[0026] According to a fourth aspect of the present application, a chip is provided, comprising the polling scheduler according to the second aspect.
[0027] According to a fifth aspect of the present application, a chip is provided, comprising the polling scheduler according to the third aspect.
[0028] Other features and advantages of the embodiments of the present application will be described in the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0030] Figure 1 It is a schematic diagram of the structure of the Find First One circuit mentioned in the background technology.
[0031] Figure 2 This is a schematic diagram of the structure of a multiplexing circuit in Example 1 of the present application.
[0032] Figure 3 This is a schematic diagram of the structure of another multiplexing circuit in Example 1 of the present application.
[0033] Figure 4 This is a structural diagram of a polling scheduler in Example 2 of the present application.
[0034] Figure 5 This is a structural diagram of a polling scheduler in Example 3 of the present application. DETAILED DESCRIPTION
[0035] The detailed description of the accompanying drawings is intended as an illustration of the currently preferred embodiment of the present application, and is not intended to represent the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included in the spirit and scope of the present application.
[0036] Embodiment 1 of the present application provides a multiplexing circuit, comprising M layers of structures connected in sequence, each layer of the structure comprising a plurality of two-select-one units, the two-select-one units being used to select one of the request signals for output according to the signal value and priority of two input request signals; M is greater than or equal to 2;
[0037] The first layer structure includes N / 2 two-choice units, where N is the number of request sources participating in the scheduling, and N is greater than or equal to 4; the input of each two-choice unit of the first layer structure is the request signal of the two request sources corresponding thereto;
[0038] Except for the first layer structure, the number of two-choice units in each layer structure is 1 / 2 of the number of two-choice units in the previous layer structure, and the input of each two-choice unit in each layer structure is the output of the two two-choice units in the corresponding previous layer structure;
[0039] The last layer of structure includes a two-choice unit, and the output of the two-choice unit is used as the output of the multiplexing circuit.
[0040] The above-mentioned multiplexing circuit optimizes the timing path of the Find First One module by processing multiple request sources in parallel in a tree structure through a hierarchical network of two-choice units, thereby reducing the number of serial comparison levels required. In the traditional Find First One module, if the number of request sources is N, then a serial N-1 level of two-choice units is required to implement it. This is because in the traditional serial structure, each request source must be compared with the next request source in turn until the first logic "1" is found. In the above-mentioned multiplexing circuit, the request sources are divided into multiple groups, each group contains two request sources, and the request sources of each group are compared by a two-choice unit. In this way, there will be N / 2 two-choice units in the first layer. The output of each two-choice unit is then used as the input of the next layer, and so on, until there is only one two-choice unit left in the last layer. This structure forms a binary tree, in which each node represents a two-choice unit, and the leaf node of the tree represents the original request source. In this way, the multiplexing circuit converts the serial comparison process into a parallel comparison process. In each layer, half of the request sources are eliminated, so the number of logic levels is greatly reduced. For N request sources, only log2(N) layers of binary selection units are needed to find the first logic "1" because each layer halves the number of request sources. This structure reduces the number of logic levels and shortens the timing path because multiple comparisons are performed in parallel rather than serially, which helps to increase the clock frequency of the module and thus improve the performance of the entire system, especially when there are a large number of request sources.
[0041] Based on the multiplexing circuit described in Embodiment 1, in some embodiments, the two-choice-one unit is further used for:
[0042] If the signal values of the two input request signals are both 1, the request signal with a higher priority is selected for output;
[0043] If the signal value of one input request signal is 0 and the signal value of another input request signal is 1, then the request signal with the signal value of 1 is selected for output;
[0044] If the signal values of the two input request signals are both 0, any one of the request signals is selected for output.
[0045] Specifically, if both input signals of the two-choice unit are 1, it means that both request sources have issued requests. In this case, the two-choice unit will select the request source with a higher priority for output according to the preset priority rule. For example, if the priority of request source A is higher than that of request source B, then even if the signals of both request sources are 1, the two-choice unit will output the signal of request source A.
[0046] If one input signal of the two-to-one unit is 0 and the other is 1, this means that one request source has made a request and the other has not. In this case, the two-to-one unit will output the request source with a signal value of 1 because it is the only source making a request.
[0047] If both input signals of the two-choice unit are 0, it means that neither request source has issued a request. In this case, the two-choice unit can select any request source for output because there is no valid request signal. In practical applications, this can be selected by selecting a fixed default request source or according to a certain rule.
[0048] This design enables the two-to-one unit to flexibly select outputs according to different combinations of input signals, thereby ensuring that the highest priority request signal can be accurately identified and delivered in the multiplexing circuit.
[0049] Based on the multiplexing circuit described in embodiment 1, in some embodiments, the request signals of N request sources are obtained according to the scheduling request input into the multiplexing circuit;
[0050] The scheduling request is an N-bit binary sequence, each bit in the binary sequence is used to indicate whether a corresponding request source participates in the scheduling, and the request signals of the N request sources correspond to the N bits one by one;
[0051] The request signal includes a signal value of a bit corresponding to it and position information of the bit in the binary sequence, and the priority of the request signal corresponds to the position information included therein.
[0052] Specifically, the scheduling request is an N-bit binary sequence, and the value of each bit (0 or 1) represents the state of a request source, 0 indicates that the request source does not participate in scheduling, and 1 indicates that the request source participates in scheduling.
[0053] The request signal of each request source includes a signal value and position information. The signal value corresponds to the corresponding bit in the scheduling request. If the request source participates in the scheduling, the signal value is 1, otherwise it is 0. The position information indicates the specific position of the request signal in the binary sequence, that is, its index in the sequence (starting from 0).
[0054] The priority of each request signal corresponds to its position information in the binary sequence, that is, the earlier the position of the request source in the binary sequence (the lower the bit), the higher its priority. For example, if the N-bit binary sequence is 10110101, then the request source 0 (position 0) has the highest priority, followed by the request source 1 (position 1), and so on. Alternatively, the later the position of the request source in the binary sequence (the higher the bit), the higher its priority. For example, if the N-bit binary sequence is 10110101, then the request source 7 (position 7) has the highest priority, followed by the request source 6 (position 6), and so on.
[0055] In this way, the multiplexing circuit is able to determine which request source should be serviced based on the scheduling request and the priority of the request signal. This design allows the priority of the request source to be directly represented in hardware, thereby simplifying the design and operation of the module.
[0056] like Figure 2 FIG. 1 is an exemplary structure of the first embodiment. Figure 2 An example of 8 request sources is shown, and the working principle of the multiplexing circuit can be explained by the following steps:
[0057] Step S11, initialization: there are 8 request sources, and their request signals are 11011010. In the first layer of the multiplexing circuit, there are 4 two-choice units, and each module corresponds to two request sources.
[0058] Step S12, first layer comparison: the two-choice unit compares the priorities of the two request sources it inputs, and outputs the request source with the higher priority; in the first layer, the first two-choice unit compares request source 0 (0) and request source 1 (1), and the output is request source 1 (1); the second two-choice unit compares request source 2 (0) and request source 3 (1), and the output is request source 3 (1); the third two-choice unit compares request source 4 (1) and request source 5 (0), and the output is request source 4 (1); the fourth two-choice unit compares request source 6 (1) and request source 7 (1), and the output is request source 6 (1); therefore, the output result of the first layer is 1111 (corresponding to request sources 6, 4, 3, 1).
[0059] Step S13, second layer comparison: In the second layer, there are two two-choice units, and the input of each two-choice unit is the two outputs of the first layer. In the second layer, the first two-choice unit compares the outputs of the first layer, request source 1(1) and request source 3(1), and the output is request source 1(1). The second two-choice unit compares the outputs of the first layer, request source 4(1) and request source 6(1), and the output is request source 4(1). Therefore, the output result of the second layer is 11 (corresponding to request sources 4 and 1).
[0060] Step S14, third layer comparison: In the third layer, there is only one two-choice unit, and its input is the two outputs of the second layer. In the third layer, the first two-choice unit compares the outputs of the second layer, request source 1 (1) and request source 4 (1), and the output is 1. Therefore, the output result of the third layer is request source 1 (1).
[0061] The output of the third layer is the final output of the multiplexing circuit, indicating that the location of the first logic "1" has been found, that is, request source 1. In this way, the multiplexing circuit finds the first logic "1" in 3 layers of comparison, while the traditional serial structure requires 7 comparisons. This hierarchical tree structure significantly reduces the number of comparisons required, thereby optimizing the timing path and improving the efficiency of the module.
[0062] like Figure 3 Another exemplary structure of the first embodiment is shown. Figure 3 In the example of 16 request sources, the working principle of the multiplexing circuit can be explained by the following steps:
[0063] Step S21, initialization: there are 16 request sources, and their request signals are 1101101011011010. In the first layer of the multiplexing circuit, there are 8 two-choice units, and each module corresponds to two request sources.
[0064] Step S22, first layer comparison: the two-choice unit compares the priorities of the two request sources it inputs, and outputs the request source with the higher priority; in the first layer, the first two-choice unit compares request source 0(0) and request source 1(1), and outputs request source 1(1); the second two-choice unit compares request source 2(0) and request source 3(1), and outputs request source 3(1); the third two-choice unit compares request source 4(1) and request source 5(0), and outputs request source 4(1); the fourth two-choice unit compares request source 6(1) and request source 7(0), and outputs request source 6(1); The 5th binary-selection unit compares request source 8(0) and request source 9(1), and the output is request source 9(1); the 6th binary-selection unit compares request source 10(0) and request source 11(1), and the output is request source 11(1); the 7th binary-selection unit compares request source 12(1) and request source 13(0), and the output is request source 12(1); the 8th binary-selection unit compares request source 14(1) and request source 15(1), and the output is request source 14(1); therefore, the output result of the first layer is 111111111 (corresponding to request sources 14, 12, 11, 9, 6, 4, 3, 1).
[0065] Step S23, second layer comparison: In the second layer, there are 4 two-choice units, and the input of each two-choice unit is the two outputs of the first layer. In the second layer, the first two-choice unit compares the output request source 1(1) and the request source 3(1) of the first layer, and the output is request source 1(1); the second two-choice unit compares the output request source 4(1) and the request source 6(1) of the first layer, and the output is request source 4(1); the third two-choice unit compares the output request source 9(1) and the request source 11(1) of the first layer, and the output is request source 9(1); the fourth two-choice unit compares the output request source 12(1) and the request source 14(1) of the first layer, and the output is request source 12(1); therefore, the output result of the second layer is 1111 (corresponding to request sources 12, 9, 4, 1).
[0066] Step S24, third layer comparison: In the third layer, there are two two-choice units, and the input of each module is the two outputs of the second layer. In the third layer, the first two-choice unit compares the output request source 1 (1) and the request source 4 (1) of the second layer, and the output is request source 1 (1); the second two-choice unit compares the output request source 9 (1) and the request source 12 (1) of the second layer, and the output is request source 9 (1); therefore, the output result of the third layer is 11 (corresponding to request sources 9 and 1).
[0067] Step S25, fourth layer comparison: In the fourth layer, there is only one two-choice unit, and its input is the two outputs of the third layer. In the fourth layer, the first two-choice unit compares the outputs of the third layer, request source 1(1) and request source 9(1), and the output is request source 1(1); therefore, the output result of the fourth layer is request source 1(1).
[0068] The output of the fourth layer is the final output of the multiplexing circuit, indicating that the location of the first logic "1" has been found, that is, request source 1. In this way, the multiplexing circuit finds the first logic "1" in 4 layers of comparison, while the traditional serial structure requires 15 comparisons. This hierarchical tree structure significantly reduces the number of comparisons required, thereby optimizing the timing path and improving the efficiency of the module.
[0069] Embodiment 2 of the present application provides a polling scheduler, such as Figure 4 As shown, it includes a recording module, a mask module, a two-selection module, a data output module and the multiplexing circuit described in the above embodiment;
[0070] The recording module is used to record the last scheduling result; specifically, it can be implemented by a pointer, for example, if the pointer points to bit5 (the pointer value is 5), then the last scheduling is request source 5;
[0071] The mask module is used to perform mask processing on the original scheduling request according to the last scheduling result to obtain a mask scheduling request; the original scheduling request refers to a scheduling request that has not been processed, including request signals of all N request sources; specifically, the mask module selects which request sources' requests should be considered and which should be ignored according to the last scheduling result. If the polling scheduling process is scheduled from low to high, if the pointer points to bit5, the request sources after bit5 are selected for scheduling in this scheduling, and the request sources before bit5 and bit5 are not selected for scheduling;
[0072] The two-choice module is used to process the input original scheduling request and the mask scheduling request. When the mask scheduling request is valid, the mask scheduling request is output to the multiplexing circuit. When the mask scheduling request is invalid, the original scheduling request is output to the multiplexing circuit. Specifically, if the mask scheduling request is valid (i.e., the mask module generates a valid mask), the two-choice module will output the mask scheduling request to the multiplexing circuit, which means that only the requests of the request sources selected in the mask will be processed by the multiplexing circuit. If the mask scheduling request is invalid (i.e., the mask module does not generate a valid mask), the two-choice module will output the original scheduling request to the multiplexing circuit, which means that the requests of all request sources will be processed by the multiplexing circuit. It should be noted that the two-choice module in the second embodiment and the two-choice unit in the first embodiment can be the same circuit element.
[0073] The multiplexing circuit is used to process the original scheduling request or the mask scheduling request output by the two-selection module to obtain the current scheduling result; specifically, the working principle of the multiplexing circuit has been described in detail in the multiplexing circuit of the above embodiment, so it will not be repeated in this embodiment;
[0074] The data output module is used to select a request source data from multiple request source data for output according to the current scheduling result.
[0075] The data output module is used to select a request source data from multiple request source data for output according to the current scheduling result output by the multiplexing circuit; specifically, assuming that there are four request sources, each request source has a data block, namely data block A of request source 0, data block B of request source 1, data block C of request source 2, and data block D of request source 3. At this time, the current scheduling result is request source 1, which means that request source 1 is selected, so the data output module will select data block B of request source 1 for output.
[0076] It should be noted that the original scheduling request is updated according to the state of the request source. The polling scheduling in this embodiment not only considers the resource fairness of each request source, but also considers the time sequence of the request source initiating the request. Resource fairness ensures that each request source has the opportunity to be served within a round of the scheduler, which is achieved through the time slice round-robin scheduling algorithm. Each request source will be assigned a fixed time slice, and the scheduler will schedule them in turn according to the order of the request source. Considering the time sequence of the request source initiating the request means that the request source that initiates the request first will be given priority service. This consideration can be achieved by recording the request time of the request source in the scheduling request. The scheduler will give priority to those request sources with earlier request times when scheduling. Therefore, the design of the polling scheduler in this embodiment can improve the responsiveness and efficiency of the system, because it not only ensures that each request source can get fair service, but also considers the actual needs and urgency of the request source. The time sequence of the request source initiating the request can be used as an important reference for scheduling, especially when processing urgent tasks or high-priority requests. In practical applications, this scheduler that considers the time sequence of requests can better meet the needs of different types of request sources, thereby improving the overall performance and user experience of the system.
[0077] In the second embodiment, since the multiplexing circuit adopts a hierarchical two-choice unit network, it can process multiple request sources in parallel, so it can significantly reduce the time required to find the first logic "1", so that the polling scheduler can more quickly determine which request source needs to be served, thereby improving the efficiency of scheduling. In a traditional polling scheduler, as the number of request sources increases, the delay of the timing path will also increase, which may lead to a performance bottleneck, and the tree structure of the multiplexing circuit reduces the number of logical levels, thereby shortening the critical timing path and reducing the delay, so that the polling scheduler can support more request sources without excessively increasing the delay. The recording module and mask module in the polling scheduler can help avoid repeated service of the same request source, thereby improving the fairness and stability of the system and realizing polling scheduling. The combination of the fast response capability of the multiplexing circuit and the recording module and mask module can ensure that the system can still maintain stable and fair scheduling when running at high speed. The design of the multiplexing circuit allows the polling scheduler to be easily expanded to more request sources. When the system needs to support more request sources, it only needs to increase the level of the multiplexing circuit without completely redesigning the scheduler. Therefore, the application of multiplexing circuits enables the polling scheduler to remain efficient, stable, and scalable when handling a large number of requests, which is crucial to improving the overall performance and reliability of complex systems.
[0078] Based on the second embodiment, in some embodiments, the original scheduling request is an N-bit binary sequence, and the value of each bit in the binary sequence is used to indicate whether a corresponding request source participates in the scheduling, and the request signals of the N request sources correspond to the N bits one by one; the request signal includes a signal value of a bit corresponding thereto and position information of the bit in the binary sequence, and the priority of the request signal corresponds to the position information included therein;
[0079] Specifically, the original scheduling request is an N-bit binary sequence. The value of each bit (0 or 1) indicates the state of a request source. 0 indicates that the request source does not participate in scheduling, and 1 indicates that the request source participates in scheduling. This design allows the state of the request source to be directly encoded in the scheduling request, thereby simplifying the design and operation of the scheduler. The request signal of each request source includes a signal value and position information. The signal value corresponds one-to-one to the corresponding bit in the scheduling request. If the request source participates in scheduling, the signal value is 1, otherwise it is 0. The position information indicates the specific position of the request signal in the binary sequence, that is, its index in the sequence (starting from 0).
[0080] Furthermore, the priority of each request signal corresponds to its position information in the binary sequence, that is, the earlier the position of the request source in the binary sequence (the lower the bit), the higher its priority. For example, if the N-bit binary sequence is 10110101, then the request source 0 (position 0) has the highest priority, followed by the request source 1 (position 1), and so on. Alternatively, the later the position of the request source in the binary sequence (the higher the bit), the higher its priority. For example, if the N-bit binary sequence is 10110101, then the request source 7 (position 7) has the highest priority, followed by the request source 6 (position 6), and so on.
[0081] The mask module is further used to determine the request source scheduled in this round according to the last scheduling result, set the value of the bit corresponding to the request source scheduled in this round in the original scheduling request to 0, and obtain a mask scheduling request;
[0082] Specifically, the mask module determines the request sources that have been scheduled in this round according to the last scheduling result, and sets the values of the bits corresponding to these scheduled request sources in the original scheduling request to 0 to obtain the mask scheduling request. This can avoid repeated scheduling of request sources that have been served in the last scheduling cycle. Specifically, assuming that the original scheduling request is 01101010 (bit0 to bit7) and the last scheduling result is bit3, in this case, the processing steps of the mask module are as follows:
[0083] The last scheduling result is bit3, which means that request source 3 was served in the last scheduling.
[0084] The mask module creates a mask that is used to mask the request source that has been serviced in the last scheduling. 11111111<<(bit3+1). The left shift operation will copy the value of bit3 to the higher bit, and fill the lower bit with 0. Since bit3 is 4 bits (counting from right to left), the left shift of 4 bits will turn it to 0, and it will be filled with all 0. The mask is bitwise ANDed with the original scheduling request. If a bit of the mask is 1, the value of the corresponding bit in the original scheduling request will be retained; if a bit of the mask is 0, the value of the corresponding bit in the original scheduling request will be masked, that is, set to 0. 11111111 is shifted 4 bits to the left to get 111111110000, and then the lower 8 bits are retained as the mask, that is, 11110000. 11110000 is bitwise ANDed with the original scheduling request 01101010 to get the masked scheduling request 01100000. The mask scheduling request 01100000 only contains the request sources that were not serviced in the previous scheduling. The polling scheduler will determine the next request source to be serviced based on this mask scheduling request. In this example, the mask scheduling request is 01100000, which means that the scheduler will select one of the request sources 4 to 7 to service.
[0085] In this way, the mask module can decide which request sources should be served in the next scheduling according to the last scheduling result, thus realizing uniform polling scheduling of request sources. At the same time, it also avoids repeated scheduling of request sources that have been served, improving the efficiency and responsiveness of the polling scheduler.
[0086] Embodiment 3 of the present application provides a polling scheduler, such as Figure 5 As shown, it includes a scheduling result recording module, a mask module, a two-choice module, a data output module, a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit are both the multiplexing circuits described in the above embodiment;
[0087] The scheduling result recording module is used to record the last scheduling result; specifically, it can be implemented by a pointer, for example, the pointer points to bit5 (the pointer value is 5), then the last scheduling is request source 5;
[0088] The mask module is used to perform mask processing on the original scheduling request according to the last scheduling result to obtain a mask scheduling request; the original scheduling request refers to a scheduling request that has not been processed, including request signals of all N request sources; specifically, the mask module selects which request sources' requests should be considered and which should be ignored according to the last scheduling result. If the polling scheduling process is scheduled from low to high, if the pointer points to bit5, the request sources after bit5 are selected for scheduling in this scheduling, and the request sources before bit5 and bit5 are not selected for scheduling;
[0089] The first multiplexing circuit is used to process the input original scheduling request and output a first scheduling result to the two-selection module; specifically, the working principle of the multiplexing circuit has been described in detail in the multiplexing circuit of the above embodiment, so the first multiplexing circuit will not be described in detail in this embodiment;
[0090] The second multiplexing circuit is used to process the input mask scheduling request and output a second scheduling result to the two-selection module; specifically, the working principle of the multiplexing circuit has been described in detail in the multiplexing circuit of the above embodiment, so the first multiplexing circuit will not be described in detail in this embodiment;
[0091] The two-select-one module is used to select and process the input first scheduling result and the second scheduling result. When the second scheduling result is valid, the second scheduling result is output to the data output module. When the second scheduling result is invalid, the first scheduling result is output to the data output module. Specifically, in the polling scheduler, the two-select-one module is used to select between two scheduling results, and the two scheduling results come from two different multiplexing circuits. If the second scheduling result is valid (that is, it is non-zero, indicating that a request source is selected), the two-select-one module will output the second scheduling result to the data output module, that is, the data output module will select the data of a request source for output according to the second scheduling result. If the second scheduling result is invalid (that is, it is zero, indicating that no request source is selected), the two-select-one module will output the first scheduling result to the data output module, that is, the data output module will select the data of a request source for output according to the first scheduling result. In this way, the two-select-one module can determine which scheduling result should be passed to the data output module according to the status of the two scheduling results, which enables the scheduler to select different scheduling strategies according to different situations, thereby achieving more flexible and efficient scheduling. It should be noted that the two-choice module in the third embodiment and the two-choice unit in the first embodiment may be the same circuit element.
[0092] The data output module is used to select a request source data from multiple request source data for output according to the first scheduling result or the second scheduling result output by the two-select-one module; specifically, assuming there are four request sources, each request source has a data block, namely data block A of request source 0, data block B of request source 1, data block C of request source 2, and data block D of request source 3. At this time, the first scheduling result or the second scheduling result output by the two-select-one module is request source 1, which means that request source 1 is selected, so the data output module will select data block B of request source 1 for output.
[0093] In the third embodiment, since the multiplexing circuit adopts a hierarchical two-choice unit network, it can process multiple request sources in parallel, so it can significantly reduce the time required to find the first logic "1", so that the polling scheduler can more quickly determine which request source needs to be served, thereby improving the efficiency of scheduling. In a traditional polling scheduler, as the number of request sources increases, the delay of the timing path will also increase, which may lead to a performance bottleneck, while the tree structure of the multiplexing circuit reduces the number of logical levels, thereby shortening the critical timing path and reducing the delay, so that the polling scheduler can support more request sources without excessively increasing the delay. The recording module and mask module in the polling scheduler can help avoid repeated service of the same request source, thereby improving the fairness and stability of the system and realizing polling scheduling. The combination of the fast response capability of the multiplexing circuit and the recording module and mask module can ensure that the system can still maintain stable and fair scheduling when running at high speed. The design of the multiplexing circuit allows the polling scheduler to be easily expanded to more request sources. When the system needs to support more request sources, it only needs to increase the level of the multiplexing circuit without completely redesigning the scheduler. Therefore, the application of multiplexing circuits enables the polling scheduler to remain efficient, stable, and scalable when handling a large number of requests, which is crucial to improving the overall performance and reliability of complex systems.
[0094] Based on the third embodiment, in some embodiments, the original scheduling request is an N-bit binary sequence, and the value of each bit in the binary sequence is used to indicate whether a corresponding request source participates in the scheduling, and the request signals of the N request sources correspond to the N bits one by one; the request signal includes a signal value of a bit corresponding thereto and position information of the bit in the binary sequence, and the priority of the request signal corresponds to the position information included therein;
[0095] Specifically, the original scheduling request is an N-bit binary sequence. The value of each bit (0 or 1) indicates the state of a request source. 0 indicates that the request source does not participate in scheduling, and 1 indicates that the request source participates in scheduling. This design allows the state of the request source to be directly encoded in the scheduling request, thereby simplifying the design and operation of the scheduler. The request signal of each request source includes a signal value and position information. The signal value corresponds one-to-one to the corresponding bit in the scheduling request. If the request source participates in scheduling, the signal value is 1, otherwise it is 0. The position information indicates the specific position of the request signal in the binary sequence, that is, its index in the sequence (starting from 0).
[0096] Furthermore, the priority of each request signal corresponds to its position information in the binary sequence, that is, the earlier the position of the request source in the binary sequence (the lower the bit), the higher its priority. For example, if the N-bit binary sequence is 10110101, then the request source 0 (position 0) has the highest priority, followed by the request source 1 (position 1), and so on. Alternatively, the later the position of the request source in the binary sequence (the higher the bit), the higher its priority. For example, if the N-bit binary sequence is 10110101, then the request source 7 (position 7) has the highest priority, followed by the request source 6 (position 6), and so on.
[0097] The mask module is further used to determine the request source scheduled in this round according to the last scheduling result, set the value of the bit corresponding to the request source scheduled in this round in the original scheduling request to 0, and obtain a mask scheduling request;
[0098] Specifically, the mask module determines the request sources that have been scheduled in this round according to the last scheduling result, and sets the values of the bits corresponding to these scheduled request sources in the original scheduling request to 0 to obtain the mask scheduling request. This can avoid repeated scheduling of request sources that have been served in the last scheduling cycle. Specifically, assuming that the original scheduling request is 01101010 (bit0 to bit7) and the last scheduling result is bit1, in this case, the processing steps of the mask module are as follows:
[0099] The last scheduling result is bit 1, which means that request source 1 was served in the last scheduling.
[0100] The mask module creates a mask that is used to mask the request source that has been serviced in the last scheduling. 11111111<<(bit1+1). The left shift operation will copy the value of bit1 to the higher bit, and fill the lower bit with 0. Since bit1 is the second bit (counting from right to left), the left shift of 2 bits will turn it to 0, and it is filled with all 0. The mask is bitwise ANDed with the original scheduling request. If a bit of the mask is 1, the value of the corresponding bit in the original scheduling request will be retained; if a bit of the mask is 0, the value of the corresponding bit in the original scheduling request will be masked, that is, set to 0. 11111111 is shifted 2 bits to the left to get 1111111100, and then the lower 8 bits are retained as the mask, that is, 11111100. 11111100 is bitwise ANDed with the original scheduling request 01101010 to get the masked scheduling request 01101000. The mask scheduling request 01101000 only contains the request sources that were not serviced in the previous scheduling. The polling scheduler will determine the next request source to be serviced based on this mask scheduling request. In this example, the mask scheduling request is 01101000, which means that the scheduler will select one of the request sources 2 to 7 to service.
[0101] In this way, the mask module can decide which request sources should be served in the next scheduling according to the last scheduling result, thus realizing uniform polling scheduling of request sources. At the same time, it also avoids repeated scheduling of request sources that have been served, improving the efficiency and responsiveness of the polling scheduler.
[0102] Embodiment 4 of the present application provides a chip, including the multiplexing circuit described in the above embodiment. The above multiplexing circuit is integrated on the chip. This design can be used in various systems that need to efficiently process multiple request sources, such as interrupt processing, task scheduling, data selection, etc.
[0103] Embodiment 5 of the present application provides a chip, including the polling scheduler described in Embodiment 2. This design enables the chip to implement an efficient and flexible scheduling mechanism, which is suitable for systems that need to process multiple request sources.
[0104] Embodiment 6 of the present application provides a chip, including the polling scheduler described in Embodiment 3. This design enables the chip to implement an efficient and flexible scheduling mechanism, which is suitable for systems that need to process multiple request sources.
[0105] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many updates and modifications will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A multiplexing circuit, characterized in that: It includes M layers of structures connected in sequence, each layer of the structure includes a plurality of two-select-one units, and the two-select-one units are used to select one of the request signals for output according to the signal values and priorities of the two input request signals; M is greater than or equal to 2; The first layer structure includes N / 2 two-choice units, where N is the number of request sources participating in the scheduling, and N is greater than or equal to 4; the input of each two-choice unit of the first layer structure is the request signal of the two request sources corresponding thereto; Except for the first layer structure, the number of two-choice units in each layer structure is 1 / 2 of the number of two-choice units in the previous layer structure, and the input of each two-choice unit in each layer structure is the output of the two two-choice units in the corresponding previous layer structure; The last layer of structure includes a two-choice unit, and the output of the two-choice unit is used as the output of the multiplexing circuit.
2. The multiplexing circuit according to claim 1, characterized in that: The two-choice unit is further used for: If the signal values of the two input request signals are both 1, the request signal with a higher priority is selected for output; If the signal value of one input request signal is 0 and the signal value of another input request signal is 1, then the request signal with the signal value of 1 is selected for output; If the signal values of the two input request signals are both 0, any one of the request signals is selected for output.
3. The multiplexing circuit according to claim 1, characterized in that: The request signals of N request sources are obtained according to the scheduling request input to the multiplexing circuit; The scheduling request is an N-bit binary sequence, each bit in the binary sequence is used to indicate whether a corresponding request source participates in the scheduling, and the request signals of the N request sources correspond to the N bits one by one; The request signal includes a signal value of a bit corresponding to it and position information of the bit in the binary sequence, and the priority of the request signal corresponds to the position information included therein.
4. A polling scheduler, characterized in that: It comprises a recording module, a mask module, a two-choice module, a data output module and a multiplexing circuit as claimed in any one of claims 1 to 3; The recording module is used to record the last scheduling result; The masking module is used to perform masking processing on the original scheduling request according to the last scheduling result to obtain a masked scheduling request; The original scheduling request includes request signals from N request sources; The two-select-one module is used to process the input original scheduling request and the mask scheduling request, and when the mask scheduling request is valid, output the mask scheduling request to the multiplexing circuit; when the mask scheduling request is invalid, output the original scheduling request to the multiplexing circuit; The multiplexing circuit is used to process the original scheduling request or the mask scheduling request output by the two-choice module to obtain the current scheduling result; The data output module is used to select a request source data from multiple request source data for output according to the current scheduling result.
5. The polling scheduler according to claim 4, characterized in that: The original scheduling request is an N-bit binary sequence, each bit in the binary sequence is used to indicate whether a corresponding request source participates in the scheduling, and the request signals of the N request sources correspond to the N bits one by one; the request signal includes a signal value of a bit corresponding thereto and position information of the bit in the binary sequence, and the priority of the request signal corresponds to the position information included therein; The mask module is further used to determine the request source scheduled in this round according to the last scheduling result, set the value of the bit corresponding to the request source scheduled in this round in the original scheduling request to 0, and obtain a mask scheduling request.
6. A polling scheduler, characterized in that: The system comprises a scheduling result recording module, a mask module, a two-choice module, a data output module, a first multiplexing circuit and a second multiplexing circuit, wherein the first multiplexing circuit and the second multiplexing circuit are multiplexing circuits according to any one of claims 1 to 3; The scheduling result recording module is used to record the last scheduling result; The masking module is used to perform masking processing on the original scheduling request according to the last scheduling result to obtain a masked scheduling request; The original scheduling request includes request signals from N request sources; The first multiplexing circuit is used to process the input original scheduling request and output a first scheduling result to the two-select-one module; The second multiplexing circuit is used to process the input mask scheduling request and output a second scheduling result to the two-select-one module; The two-selection module is used to select and process the input first scheduling result and second scheduling result, and when the second scheduling result is valid, output the second scheduling result to the data output module; when the second scheduling result is invalid, output the first scheduling result to the data output module; The data output module is used to select a request source data from a plurality of request source data for output according to the first scheduling result or the second scheduling result output by the two-selection module.
7. The polling scheduler according to claim 6, characterized in that: The original scheduling request is an N-bit binary sequence, each bit in the binary sequence is used to indicate whether a corresponding request source participates in the scheduling, and the request signals of the N request sources correspond to the N bits one by one; the request signal includes a signal value of a bit corresponding thereto and position information of the bit in the binary sequence, and the priority of the request signal corresponds to the position information included therein; The mask module is further used to determine the request source scheduled in this round according to the last scheduling result, set the value of the bit corresponding to the request source scheduled in this round in the original scheduling request to 0, and obtain a mask scheduling request.
8. A chip, characterized in that: A multiplexing circuit comprising any one of claims 1 to 3.
9. A chip, characterized in that: The invention comprises the polling scheduler according to any one of claims 4 to 5.
10. A chip, characterized in that: The invention comprises the polling scheduler according to any one of claims 6 to 7.