RapidIO message receiving flow control method, device, medium and system

Abstract

The invention discloses a RapidIO message receiving flow control method, device, medium and system, and belongs to the field of aviation integrated communication, and the method comprises the steps: a sending node is connected with a RapidIO exchange chip through a RapidIO bus; the ZYNQ receiving node is connected with the RapidIO exchange chip through a RapidIO bus; the PL unit and the PS unit of the ZYNQ chip are connected through an AXI bus; and the PL unit receives a data packet from the RapidIO exchange chip through the RapidIO bus, stores data and packet length through the packet-level FIFO, and feeds back the half-full state of the data FIFO to the sending node in a message response packet manner, thereby realizing dynamic adjustment of the sending rate. The invention provides a solution which is simple in software implementation and can improve the fault tolerance when the flow at the message receiving end and the message transmitting end is asymmetric.

Description

Technical Field

[0001] The present invention relates to the field of aviation integrated communications, and more specifically, to a RapidIO message receiving flow control method, device, medium and system. Background Art

[0002] In recent years, RapidIO bus, as a bus interconnection standard in the embedded field, has been increasingly used for high-speed interconnection between multiple heterogeneous chips in aviation integrated systems due to its high bandwidth, low latency, and high reliability.

[0003] The RapidIO message transaction type carries a response packet, which ensures the reliability of its transmission. RapidIO message transactions support up to 16 RapidIO data packets at a time, with a maximum length of 256 bytes for a single RapidIO data packet and a maximum length of 4096 bytes for a single message transmission, meeting the needs of short data packet transmission application scenarios in existing aviation integrated systems.

[0004] For the receiving end of the ZYNQ chip (processor PS unit + programmable logic PL unit), due to the limited transmission length of RapidIO messages, the PL unit receives the RapidIO message packet, stores the data in the local cache RAM or FIFO, gives the total length of the currently received message packet, and then processes it through an interrupt notification to the PS unit or the PS unit timing query method. The PS unit takes out the data of the corresponding length from the local cache RAM or FIFO according to the total length of the currently received message packet, and parses and processes it. Therefore, when the PL unit receives the message packet, the calculated total length of the currently received message packet is very important for the PS unit to process.

[0005] The ZYNQ chip integrates the processor PS unit and the programmable logic PL unit, which is highly programmable and flexible, and will serve as the main control device of the hardware board. The PS unit will serve as the main control unit of the hardware board, responsible for processing various data transmission and reception, health management, periodic bit reporting and other functions.

[0006] When the thread of the PS unit processing received messages is preempted by other high-priority threads for a long time, the RapidIO message packets received from the PL unit cannot be processed in time. Once the RapidIO message packets stored in the local cache RAM or FIFO of the PL unit overflow, the PS unit cannot find the packet header when processing, resulting in continuous errors and cyclic deadlock.

[0007] For a large-scale integrated aviation system, reliability is of vital importance and the above-mentioned cyclic deadlock situation cannot be tolerated. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a RapidIO message receiving flow control method, device, medium and system. Without increasing the system hardware cost, the problem that the PS unit at the receiving end cannot process the message packet in time causes the PL unit receiving data buffer to overflow, thereby causing the PS unit processing to enter a cyclic deadlock process is solved. The method can effectively improve the fault tolerance and reliability of the system.

[0009] The object of the present invention is achieved through the following solutions:

[0010] A RapidIO message receiving flow control system, comprising:

[0011] Transmitting node, RapidIO switching chip, ZYNQ receiving node PL unit and ZYNQ receiving node PS unit; the transmitting node is interconnected with the RapidIO switching chip through the RapidIO bus; the ZYNQ receiving node is interconnected with the RapidIO switching chip through the RapidIO bus; the ZYNQ chip PL unit and the PS unit are connected using the AXI bus.

[0012] A RapidIO message receiving flow control method, based on the RapidIO message receiving flow control system as described above, comprises the following steps:

[0013] Step S1, the ZYNQ receiving node PL unit receives data from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving and processing module, parses the RapidIO packet header, extracts the RapidIO message packet, and records the value of the Data_FIFO half-full signal at the current moment. When the Data_FIFO half-full signal is invalid, the RapidIO message data is written into the Data_FIFO, and the calculated data length is written into the length Len_FIFO;

[0014] Step S2, the RapidIO message response sending module, after receiving the RapidIO message, records the message packet sequence number and the source ID information of the sending node; and writes the value of the data Data_FIFO half-full signal at the current message packet reception time output by the RapidIO message receiving and processing module into the bit0 of the response packet header, writes the value of the discarded flag of the data packet into the bit1 of the response packet header, and sets the error flag of bit35 of the response packet header; the sending node receives the message response packet from the ZYNQ receiving node, and realizes dynamic adjustment of the sending rate by reading the values ​​of the reserved bits bit0 and bit35 of the response packet header.

[0015] Furthermore, the recording of the value of the data_FIFO half-full signal at the current moment specifically includes: registering the state of the data_FIFO half-full signal fifo_data_prog_full at the moment of receiving the first data packet of the current RapidIO message.

[0016] Further, the when the data Data_FIFO half-full signal is invalid specifically means: when the flag fifo_prog_full_flag after the data Data_FIFO half-full signal is registered is invalid.

[0017] Furthermore, after writing the RapidIO message data into the data_FIFO and writing the calculated data length into the length Len_FIFO, the method further includes the step of: when the flag fifo_prog_full_flag after the data_FIFO half-full signal is registered is valid, setting the data packet discarded flag msg_drp_before_flag to be valid.

[0018] Further, the step of writing the value of the data Data_FIFO half-full signal at the current message packet reception moment output by the RapidIO message reception processing module into the bit0 position of the response packet header specifically includes: writing the value of the flag fifo_prog_full_flag after the data Data_FIFO half-full signal output by the RapidIO message reception processing module is stored into the bit0 position of the response packet header.

[0019] Furthermore, the bit35 error flag of the response packet header is set at the same time, specifically: the bit35 error flag of the response packet header is set according to the value of fifo_prog_full_flag at the same time.

[0020] A RapidIO message receiving flow control method, based on the RapidIO message receiving flow control system as described above, comprises the following steps:

[0021] The RapidIO message receiving data processing flow enters the initial state after the power-on reset is completed; monitors whether the received RapidIO data packet is the first packet of the message, otherwise continues to monitor, and if so, enters the data FIFO half-full signal valid judgment flow; in the data FIFO half-full signal valid judgment flow, if yes, enters the data packet discard flag setting state;

[0022] After the data packet discard flag state is set, the process of judging whether the current message packet is the last packet is entered; in the process of judging whether the current message packet is the last packet, if yes, the process of judging whether the data packet discard flag is valid is entered; in the process of judging whether the data packet discard flag is valid, if yes, the process of setting the data packet discard flag state is entered; after the data packet discard flag state is set, the process of clearing the data packet discard flag is entered; after the execution of clearing the data packet discard flag state is completed, the process of returning to the initial state is returned;

[0023] In the process of judging whether the data FIFO half-full signal is valid, otherwise, it turns to the process of judging whether the current message packet is the last packet;

[0024] In the process of judging whether the packet discard flag is valid, if not, the state of writing the message packet length in the length FIFO is entered, and then the state of clearing the packet discard flag is entered; after the state of clearing the packet discard flag is completed, the state is returned to the initial state.

[0025] A RapidIO message receiving flow control method, based on the RapidIO message receiving flow control system as described above, comprises the following steps:

[0026] The RapidIO message response sending process enters the initial state after the power-on reset is completed; monitors whether the received RapidIO data packet is a message packet, otherwise continues to monitor, and if so enters the state of recording the packet sequence number and source ID of the RapidIO message packet, and then enters the state of setting the bit0, bit1 and bit35 of the response packet; after the state of setting the bit0, bit1 and bit35 of the response packet is completed, enters the state of setting the message response packet header; after the state of setting the message response packet header is completed, enters the state of whether the message response packet is sent, otherwise continues to judge, and if yes, returns to the initial state.

[0027] A RapidIO message receiving flow control device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method described in any one of Embodiments 2 to 9 is executed.

[0028] A computer-readable storage medium stores a computer program, and when the computer program is loaded by a processor, the method described in any one of Embodiments 2 to 9 is executed.

[0029] The beneficial effects of the present invention include:

[0030] The present invention can improve the fault tolerance when the flow rates at both ends of message sending and receiving are asymmetric, thereby improving the reliability of the system.

[0031] The present invention realizes the reception of continuous RapidIO message packets by adopting a packet-level FIFO mode. Using a data FIFO half-full signal feedback mechanism, on the one hand, when the PS unit is too late to take away the local FIFO data of the PL unit, the new RapidIO message packet from the sending node is actively discarded to ensure that the PS unit processing will not cause a cyclic deadlock; on the other hand, using a receiving node message response mode, the receiving node FIFO overflow information is actively notified to the sending node, so that the communicating parties establish a flow control mechanism, and the sending node can dynamically adjust the rate of RapidIO message sending. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0033] Figure 1 A schematic diagram of a RapidIO message receiving flow control method of the present invention;

[0034] Figure 2 for Figure 1 Implement the schematic diagram;

[0035] Figure 3 for Figure 2 RapidIO message response packet header information diagram;

[0036] Figure 4 for Figure 2 RapidIO message receiving data processing flow chart;

[0037] Figure 5 for Figure 2 RapidIO message response sending process flow chart. DETAILED DESCRIPTION

[0038] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0039] The specific implementation process of the present invention is as follows:

[0040] like Figure 1As shown, the present invention provides a RapidIO message receiving flow control method, comprising: a sending node + a RapidIO switching chip + a ZYNQ receiving node PL unit + a ZYNQ receiving node PS unit. The sending node is interconnected with the RapidIO switching chip through a RapidIO bus; the ZYNQ receiving node is interconnected with the RapidIO switching chip through a RapidIO bus. The ZYNQ chip PL unit and the PS unit are connected using an AXI bus.

[0041] like Figure 2 As shown, the ZYNQ receiving node PL unit receives the data packet from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving and processing module, parses the RapidIO packet header, extracts the RapidIO message packet, and registers the data Data_FIFO half-full signal fifo_data_prog_full state at the moment of receiving the first packet of the current RapidIO message. When the flag fifo_prog_full_flag after the data Data_FIFO half-full signal is registered is invalid, the RapidIO message data msg_data_in is written into the data Data_FIFO, and the calculated data length msg_len_in is written into the length Len_FIFO. When the flag fifo_prog_full_flag after the data Data_FIFO half-full signal is registered is valid, the flag msg_drp_before_flag indicating that the data packet has been discarded is set to be valid. The RapidIO message response sending module, after receiving the RapidIO message, on the one hand, records the source ID of the message sender; on the other hand, writes the value of the flag fifo_prog_full_flag after the data Data_FIFO half-full signal output from the RapidIO message receiving and processing module is stored into the bit0 of the response packet header; writes the data packet discarded flag msg_drp_before_flag into the bit1 of the response packet header; and sets the error flag bit35 of the response packet header according to the value of fifo_prog_full_flag.

[0042] Figure 3In the RapidIO message response packet, bit63 to bit56 are Target_tid, which is the message packet sequence number and is consistent with the value of bit63 to bit56 in the received message packet header; bit55 to bit52 are Ftype values, which are set to 0xd in the message response; bit51 to bit48 are Ttype values, which are set to 0x1 in the message response; bit47 is the RSV reserved bit, which is set to 1'b0; bit46 to bit45 are Prio values, which are set to 2'b01; bit44 is the Crf value, which is set to 1'b0; bit43 to bit36 are RSV reserved bits, which are set to 0x00; bit35 is the error value, which has a default value of 1'b0. It is set here according to the fifo_prog_full_flag value. When fifo_prog_full_flag is 0, it is set is 1'b0, and is set to 1'b1 when fifo_prog_full_flag is 1; bit34~bit32 are RSV reserved bits, set to bit 3'b000; bit31~bit0 are RSV reserved bits, with the default value 0x00000000, the value of bit1 here is consistent with the value of msg_drp_before_flag, when msg_drp_before_flag is 0, bit1 is set to 1'b0, and when msg_drp_before_flag is 1, bit1 is set to 1'b1; the value of bit0 here is consistent with the value of fifo_prog_full_flag, when fifo_prog_full_flag is 0, bit0 is set to 1'b0, and when fifo_prog_full_flag is 1, bit0 is set to 1'b1.

[0043] like Figure 4 As shown, the RapidIO message receiving data processing flow enters the initial state after the power-on reset is completed. Monitor whether the received RapidIO data packet is the first packet of the message. If so, enter the data FIFO half-full signal whether the judgment flow is valid. In the data FIFO half-full signal whether the judgment flow is valid, if yes, enter the data packet discard flag setting state.

[0044] Figure 4 After setting the packet discard flag state, the process of determining whether the current message packet is the last packet is transferred to. In the process of determining whether the current message packet is the last packet, if yes, the process of determining whether the packet discard flag is valid is transferred to. In the process of determining whether the packet discard flag is valid, if yes, the process of setting the packet discard flag state is transferred to. After setting the packet discard flag state is completed, the process of clearing the packet discard flag is transferred to. After the execution of clearing the packet discard flag state is completed, the process returns to the initial state.

[0045] Figure 4 In the process of determining whether the data FIFO half-full signal is valid, otherwise, the process of determining whether the current message packet is the last packet is entered.

[0046] Figure 4 In the process of judging whether the packet discard flag is valid, if not, the state of writing the message packet length in the length FIFO is entered, and then the state of clearing the packet discard flag is entered. After the execution of the clearing packet discard flag state is completed, the initial state is returned.

[0047] like Figure 5 As shown in the figure, the RapidIO message response sending process enters the initial state after the power-on reset is completed. Monitor whether the received RapidIO data packet is a message packet. If it is, enter the state of recording the packet sequence number and source ID of the RapidIO message packet, and then enter the state of setting the bit0, bit1 and bit35 of the response packet. After the state of setting the bit0, bit1 and bit35 of the response packet is completed, enter the state of setting the message response header. After the state of setting the message response header is completed, enter the state of whether the message response packet is sent. If it is, return to the initial state.

[0048] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0049] Example 1

[0050] A RapidIO message receiving flow control system, comprising:

[0051] Transmitting node, RapidIO switching chip, ZYNQ receiving node PL unit and ZYNQ receiving node PS unit; the transmitting node is interconnected with the RapidIO switching chip through the RapidIO bus; the ZYNQ receiving node is interconnected with the RapidIO switching chip through the RapidIO bus; the ZYNQ chip PL unit and the PS unit are connected using the AXI bus.

[0052] Example 2

[0053] A RapidIO message receiving flow control method, based on the RapidIO message receiving flow control system described in Example 1, comprises the following steps:

[0054] Step S1, the ZYNQ receiving node PL unit receives data from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving and processing module, parses the RapidIO packet header, extracts the RapidIO message packet, and records the value of the Data_FIFO half-full signal at the current moment. When the Data_FIFO half-full signal is invalid, the RapidIO message data is written into the Data_FIFO, and the calculated data length is written into the length Len_FIFO;

[0055] Step S2, the RapidIO message response sending module, after receiving the RapidIO message, records the message packet sequence number and the source ID information of the sending node; and writes the value of the data Data_FIFO half-full signal at the current message packet reception time output by the RapidIO message receiving and processing module into the bit0 of the response packet header, writes the value of the discarded flag of the data packet into the bit1 of the response packet header, and sets the error flag of bit35 of the response packet header; the sending node receives the message response packet from the ZYNQ receiving node, and realizes dynamic adjustment of the sending rate by reading the values ​​of the reserved bits bit0 and bit35 of the response packet header.

[0056] Example 3

[0057] On the basis of the second embodiment, the recording of the value of the Data_FIFO half-full signal at the current moment specifically includes: registering the state of the Data_FIFO half-full signal fifo_data_prog_full at the moment of receiving the first data packet of the current RapidIO message.

[0058] Example 4

[0059] On the basis of Embodiment 3, the when the data_FIFO half-full signal is invalid is specifically: when the flag fifo_prog_full_flag after the data_FIFO half-full signal is registered is invalid.

[0060] Example 5

[0061] Based on Example 4, after writing the RapidIO message data into the data_FIFO and writing the calculated data length into the length Len_FIFO, the method further includes the step of: when the flag fifo_prog_full_flag after the data_FIFO half-full signal is registered is valid, setting the data packet discarded flag msg_drp_before_flag to be valid.

[0062] Example 6

[0063] On the basis of Example 4, the step of writing the value of the data Data_FIFO half-full signal at the current message packet reception moment output by the RapidIO message reception processing module into the bit0 position of the response packet header is specifically: writing the value of the flag fifo_prog_full_flag after the data Data_FIFO half-full signal output by the RapidIO message reception processing module is stored into the bit0 position of the response packet header.

[0064] Example 7

[0065] On the basis of Example 4, the bit 35 error flag of the response packet header is set at the same time, specifically: the bit 35 error flag of the response packet header is set according to the value of fifo_prog_full_flag at the same time.

[0066] Example 8

[0067] A RapidIO message receiving flow control method, based on the RapidIO message receiving flow control system described in Example 1, comprises the following steps:

[0068] The RapidIO message receiving data processing flow enters the initial state after the power-on reset is completed; monitors whether the received RapidIO data packet is the first packet of the message, otherwise continues to monitor, and if so, enters the data FIFO half-full signal valid judgment flow; in the data FIFO half-full signal valid judgment flow, if yes, enters the data packet discard flag setting state;

[0069] After the data packet discard flag state is set, the process of judging whether the current message packet is the last packet is entered; in the process of judging whether the current message packet is the last packet, if yes, the process of judging whether the data packet discard flag is valid is entered; in the process of judging whether the data packet discard flag is valid, if yes, the process of setting the data packet discard flag state is entered; after the data packet discard flag state is set, the process of clearing the data packet discard flag is entered; after the execution of clearing the data packet discard flag state is completed, the process of returning to the initial state is returned;

[0070] In the process of judging whether the data FIFO half-full signal is valid, otherwise, it turns to the process of judging whether the current message packet is the last packet;

[0071] In the process of judging whether the packet discard flag is valid, if not, the state of writing the message packet length in the length FIFO is entered, and then the state of clearing the packet discard flag is entered; after the state of clearing the packet discard flag is completed, the state is returned to the initial state.

[0072] Example 9

[0073] A RapidIO message receiving flow control method, based on the RapidIO message receiving flow control system described in Example 1, comprises the following steps:

[0074] The RapidIO message response sending process enters the initial state after the power-on reset is completed; monitors whether the received RapidIO data packet is a message packet, otherwise continues to monitor, and if so enters the state of recording the packet sequence number and source ID of the RapidIO message packet, and then enters the state of setting the bit0, bit1 and bit35 of the response packet; after the state of setting the bit0, bit1 and bit35 of the response packet is completed, enters the state of setting the message response packet header; after the state of setting the message response packet header is completed, enters the state of whether the message response packet is sent, otherwise continues to judge, and if yes, returns to the initial state.

[0075] Example 10

[0076] A RapidIO message receiving flow control device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method described in any one of Embodiments 2 to 9 is executed.

[0077] Embodiment 11

[0078] A computer-readable storage medium stores a computer program, wherein the computer program is loaded by a processor and executes the method described in any one of Embodiments 2 to 9.

[0079] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0080] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0081] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A RapidIO message receiving flow control system, characterized in that: include: Transmitting node, RapidIO switch chip, ZYNQ receiving node PL unit and ZYNQ receiving node PS unit; The sending node is interconnected with the RapidIO switching chip through the RapidIO bus; the ZYNQ receiving node is interconnected with the RapidIO switching chip through the RapidIO bus; the ZYNQ chip PL unit and PS unit are connected using the AXI bus.

2. A RapidIO message receiving flow control method, characterized in that: The RapidIO message receiving flow control system according to claim 1 comprises the following steps: Step S1, the ZYNQ receiving node PL unit receives data from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving and processing module, parses the RapidIO packet header, extracts the RapidIO message packet, and records the value of the Data_FIFO half-full signal at the current moment. When the Data_FIFO half-full signal is invalid, the RapidIO message data is written into the Data_FIFO, and the calculated data length is written into the length Len_FIFO; Step S2, the RapidIO message response sending module, after receiving the RapidIO message, records the message packet sequence number and the source ID information of the sending node; and writes the value of the data Data_FIFO half-full signal at the current message packet reception time output by the RapidIO message receiving and processing module into the bit0 of the response packet header, writes the value of the discarded flag of the data packet into the bit1 of the response packet header, and sets the error flag of bit35 of the response packet header; the sending node receives the message response packet from the ZYNQ receiving node, and realizes dynamic adjustment of the sending rate by reading the values ​​of the reserved bits bit0 and bit35 of the response packet header.

3. The RapidIO message receiving flow control method according to claim 2, characterized in that: The recording of the value of the data_FIFO half-full signal at the current moment specifically includes: registering the state of the data_FIFO half-full signal fifo_data_prog_full at the moment of receiving the first data packet of the current RapidIO message.

4. The RapidIO message receiving flow control method according to claim 3, characterized in that: The when the data Data_FIFO half-full signal is invalid specifically means: when the flag fifo_prog_full_flag after the data Data_FIFO half-full signal is stored is invalid.

5. The RapidIO message receiving flow control method according to claim 4, characterized in that: After writing the RapidIO message data into the data_FIFO and writing the calculated data length into the length Len_FIFO, the method further includes the step of: when the flag fifo_prog_full_flag after the data_FIFO half-full signal is stored is valid, setting the data packet discarded flag msg_drp_before_flag to be valid.

6. The RapidIO message receiving flow control method according to claim 4, characterized in that: The step of writing the value of the data Data_FIFO half-full signal at the current message packet reception moment output by the RapidIO message reception processing module into the bit0 position of the response packet header specifically includes: writing the value of the flag fifo_prog_full_flag after the data Data_FIFO half-full signal output by the RapidIO message reception processing module is stored into the bit0 position of the response packet header.

7. The RapidIO message receiving flow control method according to claim 6, characterized in that: The bit35 error flag of the response packet header is set at the same time, specifically: the bit35 error flag of the response packet header is set according to the value of fifo_prog_full_flag at the same time.

8. A RapidIO message receiving flow control method, characterized in that: The RapidIO message receiving flow control system according to claim 1 comprises the following steps: The RapidIO message receiving data processing flow enters the initial state after the power-on reset is completed; monitors whether the received RapidIO data packet is the first packet of the message, otherwise continues to monitor, and if so, enters the data FIFO half-full signal valid judgment flow; in the data FIFO half-full signal valid judgment flow, if yes, enters the data packet discard flag setting state; After the data packet discard flag status is set, the process of determining whether the current message packet is the last packet is entered; if the current message packet is the last packet, the process of determining whether the data packet discard flag is valid is entered; In the process of judging whether the packet discard flag is valid, if it is, the state of setting the packet discard flag appears is entered; after the state of setting the packet discard flag appears is completed, the state of clearing the packet discard flag is entered; after the state of clearing the packet discard flag is completed, the initial state is returned; In the process of judging whether the data FIFO half-full signal is valid, otherwise, it turns to the process of judging whether the current message packet is the last packet; In the process of judging whether the packet discard flag is valid, if not, the state of writing the message packet length in the length FIFO is entered, and then the state of clearing the packet discard flag is entered; after the state of clearing the packet discard flag is completed, the state is returned to the initial state.

9. A RapidIO message receiving flow control method, characterized in that: The RapidIO message receiving flow control system according to claim 1 comprises the following steps: The RapidIO message response sending process enters the initial state after the power-on reset is completed; monitors whether the received RapidIO data packet is a message packet, otherwise continues to monitor, and if so enters the state of recording the packet sequence number and source ID of the RapidIO message packet, and then enters the state of setting the bit0, bit1 and bit35 of the response packet; after the state of setting the bit0, bit1 and bit35 of the response packet is completed, enters the state of setting the message response packet header; after the state of setting the message response packet header is completed, enters the state of whether the message response packet is sent, otherwise continues to judge, and if yes, returns to the initial state.

10. A RapidIO message receiving flow control device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 2 to 9 is executed.

11. A computer-readable storage medium, characterized in that: A computer program is stored in the readable storage medium, and the computer program is loaded by a processor to execute the method according to any one of claims 2 to 9.

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