CPLD-based high-speed switch control method, apparatus and device, and storage medium

Abstract

The invention discloses a CPLD-based high-speed switch control method, device and equipment and a storage medium, and relates to the technical field of switches, and the CPLD-based high-speed switch control method comprises the following steps: when a high-speed switch control scene is a state detection scene, collecting a level state signal of each module; respectively storing the level state signal of each module to a corresponding storage register according to the function type corresponding to the level state signal of each module; and when the occurrence of a target event is monitored, sending an event generation signal to a target chip, so that the target chip reads a corresponding storage register according to the event generation signal, and completing state detection. All signals are mounted on the CPLD, so that a lower-level device can be controlled or monitored only by reading and writing an internal register of the CPLD through an I2C interface during operation, and the operation of a switch system state monitoring process is simplified.

Description

Technical Field

[0001] The present application relates to the technical field of switches, and in particular to a CPLD-based high-speed switch control method, device, equipment and storage medium. Background Art

[0002] The common switch signal control of high-speed switches is implemented by multiple programmable devices. The SOC chip is controlled through the I2C interface. It is necessary to poll or edit multiple devices with different addresses to monitor the status of each device of the switch or control the PHY, optical module, temperature detection chip and other devices mounted under the programmable device. The operation is relatively cumbersome. The control of the LED light of the optical module also requires multiple shift register chips to be spliced ​​end to end to realize the function of a multi-bit shift register. The wiring is relatively cumbersome and takes up a lot of space. Summary of the invention

[0003] The main purpose of the present application is to provide a CPLD-based high-speed switch control method, device, equipment and storage medium, aiming to solve the technical problem of cumbersome operation in the existing switch system status monitoring process.

[0004] To achieve the above purpose, the present application proposes a CPLD-based high-speed switch control method, the CPLD-based high-speed switch control method comprising:

[0005] When the high-speed switch control scenario is a status detection scenario, the level status signal of each module is collected;

[0006] According to the function type corresponding to the level state signal of each module, the level state signal of each module is stored in the corresponding storage register;

[0007] When the target event is detected to occur, an event occurrence signal is sent to the target chip, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the state detection.

[0008] In one embodiment, when the target event is detected, sending the event occurrence signal to the target chip includes:

[0009] When a target event is detected, a level state signal of a module corresponding to the target event is adjusted to obtain an adjustment state signal;

[0010] An event occurrence signal is generated according to the adjustment state signal, and the event occurrence signal is sent to a target chip.

[0011] In one embodiment, the CPLD-based high-speed switch control method further includes:

[0012] When the high-speed switch control scenario is a channel chip selection scenario, the channels of each module are numbered to obtain multiple target channel numbers;

[0013] When there is a need to access the target module, receiving the current module number sent by the target chip;

[0014] Channel chip selection is completed according to the current module number and multiple target channel numbers.

[0015] In one embodiment, completing channel chip selection according to the current module number and multiple target channel numbers includes:

[0016] Store the current module number to the chip select register and determine the corresponding current channel number;

[0017] Determine a corresponding module channel number according to the current channel number and a plurality of target channel numbers;

[0018] The interface of the module channel number is connected to the interface of the target chip to complete the channel chip selection.

[0019] In one embodiment, the CPLD-based high-speed switch control method further includes:

[0020] When the high-speed switch control scenario is a lighting control scenario, receiving a serial data signal sent by a target chip;

[0021] Performing signal conversion on the serial data signal through a shift register according to a clock signal to obtain a parallel data signal;

[0022] Lighting control is performed according to the parallel data signal.

[0023] In one embodiment, the performing lighting control according to the parallel data signal includes:

[0024] Distributing the parallel data signals to corresponding output pins and determining output information;

[0025] When the output information is consistent with the preset information, the light is controlled to flash.

[0026] In one embodiment, the CPLD-based high-speed switch control method further includes:

[0027] When the high-speed switch control scenario is an interrupt reporting scenario, the module interrupt signal is shifted into a corresponding interrupt parallel signal;

[0028] When a target interrupt event is detected in the interrupt parallel signal, the level state of the pin is adjusted and the level state of the pin is sent to the target chip, so that the target chip reads the corresponding interrupt register according to the level state of the pin and reports the interrupt.

[0029] In addition, to achieve the above purpose, the present application also proposes a CPLD-based high-speed switch control device, the CPLD-based high-speed switch control device comprising:

[0030] The acquisition module is used to collect the level status signals of each module when the high-speed switch control scenario is a status detection scenario;

[0031] A storage module, used for storing the level status signal of each module to a corresponding storage register according to the function type corresponding to the level status signal of each module;

[0032] The control module is used to send an event occurrence signal to the target chip when the target event is detected, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection.

[0033] In addition, to achieve the above-mentioned purpose, the present application also proposes a CPLD-based high-speed switch control device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the CPLD-based high-speed switch control method as described above.

[0034] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the CPLD-based high-speed switch control method as described above are implemented.

[0035] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the CPLD-based high-speed switch control method as described above are implemented.

[0036] This application collects the level status signals of each module when the high-speed switch control scenario is a status detection scenario; stores the level status signals of each module to the corresponding storage registers according to the function types corresponding to the level status signals of each module; and sends an event occurrence signal to the target chip when the target event occurs, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection. By mounting all signals to the programmable device CPLD, the control or monitoring of the lower-level devices can be realized by only reading and writing the internal registers of the CPLD through the I2C interface during operation, which simplifies the operation of the switch system status monitoring process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0039] Figure 1 A flowchart of a first embodiment of a high-speed switch control method based on CPLD according to the present application;

[0040] Figure 2 A schematic diagram of the control and monitoring flow of each module of a switch provided in Embodiment 1 of the high-speed switch control method based on CPLD of the present application;

[0041] Figure 3 A flow chart of the second embodiment of the high-speed switch control method based on CPLD provided in the present application;

[0042] Figure 4 This is an I2C topology diagram provided for the second embodiment of the high-speed switch control method based on CPLD of the present application;

[0043] Figure 5 A flowchart diagram of the third embodiment of the high-speed switch control method based on CPLD of the present application is provided;

[0044] Figure 6 A schematic diagram of the LED serial transfer and control process provided in Embodiment 3 of the high-speed switch control method based on CPLD of the present application;

[0045] Figure 7 A flowchart diagram of a fourth embodiment of a high-speed switch control method based on CPLD of the present application is provided;

[0046] Figure 8 A schematic diagram of an interrupt reporting process provided in Embodiment 4 of the high-speed switch control method based on CPLD of the present application;

[0047] Fig. 9 This is a schematic diagram of the module structure of a high-speed switch control device based on CPLD according to an embodiment of the present application;

[0048] Fig.10 The device structure diagram of the hardware operating environment involved in the CPLD-based high-speed switch control method in the embodiment of the present application.

[0049] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0051] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0052] The main solution of the embodiment of the present application is: when the high-speed switch control scenario is a status detection scenario, the level status signal of each module is collected; the level status signal of each module is stored in the corresponding storage register according to the function type corresponding to the level status signal of each module; when the target event is detected, an event occurrence signal is sent to the target chip, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection.

[0053] The common switch signal control of high-speed switches is implemented by multiple programmable devices. The SOC chip is controlled through the I2C interface. It is necessary to poll or edit multiple devices with different addresses to monitor the status of each device of the switch or control the PHY, optical module, temperature detection chip and other devices mounted under the programmable device. The operation is relatively cumbersome. The control of the LED light of the optical module also requires multiple shift register chips to be spliced ​​end to end to realize the function of a multi-bit shift register. The wiring is relatively cumbersome and takes up a lot of space.

[0054] This application proposes that when the high-speed switch control scenario is a status detection scenario, the level status signal of each module is collected; the level status signal of each module is stored in the corresponding storage register according to the function type corresponding to the level status signal of each module; when the target event is detected, the event occurrence signal is sent to the target chip, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection. By mounting all signals to the programmable device CPLD, it is only necessary to read and write the internal register of the CPLD through the I2C interface to realize the control or monitoring of the lower-level devices during operation, which simplifies the operation of the switch system status monitoring process.

[0055] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or a CPLD-based high-speed switch control device that can realize the above functions. The following takes a CPLD-based high-speed switch control device as an example of the execution subject, for example, a programmable logic device (Complex Programmable Logic Device, CPLD), to illustrate this embodiment and the following embodiments.

[0056] Based on this, the embodiment of the present application provides a high-speed switch control method based on CPLD, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the CPLD-based high-speed switch control method of the present application.

[0057] In this embodiment, the CPLD-based high-speed switch control method includes steps S10 to S30:

[0058] Step S10, when the high-speed switch control scenario is a status detection scenario, collecting the level status signal of each module;

[0059] It should be noted that the switch system status monitoring process is cumbersome, and the SOC chip needs to poll each module. The signals of these modules may be monitored by multiple GPIO expansion chips or directly by the SOC chip providing multiple GPIOs. In this embodiment, all signals are reported to the CPLD and then stored in the register of the CPLD. The SOC chip can read the internal register of the CPLD through the I2C interface.

[0060] It can be understood that the status detection scenario refers to the scenario in which the switch SOC chip controls and detects each module through the I2C interface. Each module includes POE, PHY, optical module and other modules, and the level status signal includes a low level status signal and a high level status signal.

[0061] In the specific implementation, when the high-speed switch control scenario is that the switch SOC chip controls and detects each module scenario through the I2C interface, the CPLD collects the level status signals of modules such as POE, PHY, and optical modules. Among them, the high level in the power supply working status signal indicates that the power supply is working normally, and the low level indicates that the power supply is working abnormally.

[0062] Step S20, storing the level status signal of each module into the corresponding storage register according to the function type corresponding to the level status signal of each module;

[0063] It can be understood that the function type refers to the module type, and the storage register includes registers such as POE registers, PHY registers, and optical module registers.

[0064] In the specific implementation, the CPLD collects the level status signals of modules such as POE, PHY, and optical modules, and then analyzes the level status signals to determine the corresponding module types, and then classifies and stores the level status signals in various registers. For example, when the collected level status signal is of the power supply type, the collected level status signal is stored in the power supply register.

[0065] Step S30, when the target event is detected to occur, an event occurrence signal is sent to the target chip, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection.

[0066] It can be understood that the target event refers to events such as power failure and light emission of the optical module, the target chip refers to the SOC chip, and the event occurrence signal refers to the signal reporting the occurrence of a related event to the SOC chip.

[0067] In the specific implementation, when the CPLD detects that the power supply is not in place or the optical module is emitting light, the CPLD will pull down the corresponding GPIO level and report to the SOC chip that a related event has occurred. The SOC chip then reads the status register of the CPLD target event through the I2C interface to obtain the status of the switch-related modules.

[0068] In a feasible implementation, step S30 may include steps A31 to A32:

[0069] Step A31, when the target event is detected, adjusting the level state signal of the module corresponding to the target event to obtain an adjustment state signal;

[0070] It can be understood that the adjustment state signal refers to the level state signal after adjustment.

[0071] In a specific implementation, when it is detected that the power supply is not in place, the optical module is emitting light, etc., the CPLD pulls down the corresponding GPIO level, and then obtains the adjusted level status signal.

[0072] Step A32, generating an event occurrence signal according to the adjustment status signal, and sending the event occurrence signal to the target chip.

[0073] It can be understood that a signal for reporting the occurrence of a relevant event to the SOC chip is generated according to the adjusted level status signal, and the signal for reporting the occurrence of a relevant event to the SOC chip is sent to the SOC chip.

[0074] It should be noted that if Figure 2As shown, in this embodiment, the signals of the switch POE, PHY, optical module and other modules are concentrated on the CPLD, reducing the use of system resources. In this design, the status signals of each module monitored by the CPLD are all level signals: such as the in-position signal of each module - high level indicates that it is not in position, and low level indicates that it is in position; the power supply working status signal - high level indicates that the power supply is working normally, and low level indicates that the power supply is working abnormally, etc. These signals are directly read by the CPLD in real time through GPIO and their level states are stored in various registers according to functional classification. The CPLD provides a GPIO for each type of status signal to report the occurrence of related events to the SOC. For example, when the power supply is not in place, the optical module emits light, etc., the CPLD pulls down the corresponding GPIO level and reports the occurrence of related events to the SOC chip. Then the SOC chip reads the status register of the CPLD target event through the I2C interface to obtain the status of the switch-related modules, replacing the traditional SOC periodically polling all status signals to read the status of each device.

[0075] This embodiment collects the level status signals of each module when the high-speed switch control scenario is a status detection scenario; stores the level status signals of each module to the corresponding storage registers according to the function types corresponding to the level status signals of each module; and sends an event occurrence signal to the target chip when the target event occurs, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection. By mounting all signals to the programmable device CPLD, the control or monitoring of the lower-level devices can be realized by only reading and writing the internal registers of the CPLD through the I2C interface during operation, which simplifies the operation of the switch system status monitoring process.

[0076] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 3 The CPLD-based high-speed switch control method further includes steps S21 to S23:

[0077] Step S21, when the high-speed switch control scenario is a channel chip selection scenario, number the channels of each module to obtain multiple target channel numbers;

[0078] It can be understood that the channel chip selection scenario refers to the chip selection scenario of the I2C channel, and the target channel number refers to the number of the I2C channel corresponding to the module.

[0079] In a specific implementation, when the high-speed switch control scenario is a chip selection scenario of an I2C channel, the CPLD simulates programmable device logic, opens a chip selection register internally and assigns a number to each I2C channel, thereby obtaining the numbers of the I2C channels corresponding to multiple modules.

[0080] Step S22, when there is a target module access requirement, receiving the current module number sent by the target chip;

[0081] It can be understood that the target module access requirement refers to the requirement of the SOC chip to access a certain I2C device, and the current module number refers to the number of the module that the SOC chip needs to access.

[0082] In a specific implementation, when the need of the SOC chip to access a certain I2C device is detected, the number of the module that the SOC chip needs to access, which is sent by the SOC chip, is received.

[0083] Step S23, completing channel chip selection according to the current module number and multiple target channel numbers.

[0084] It can be understood that the numbers of the modules that the SOC chip needs to access are matched with the numbers of the I2C channels corresponding to the multiple modules, thereby completing the channel chip selection.

[0085] In a feasible implementation, step S23 may include steps A231 to A233:

[0086] Step A231, store the current module number to the chip select register, and determine the corresponding current channel number;

[0087] It is understandable that the SOC chip can write the number of the target I2C channel into the chip select register of the CPLD through the I2C interface to obtain the current channel number.

[0088] Step A232, determining a corresponding module channel number according to the current channel number and a plurality of target channel numbers;

[0089] It can be understood that the numbers of the modules that the SOC chip needs to access are matched with the numbers of the I2C channels corresponding to the multiple modules to obtain the numbers of the corresponding I2C channels, that is, to obtain the corresponding module channel numbers.

[0090] Step A233, connecting the interface of the module channel number with the interface of the target chip to complete the channel chip selection.

[0091] In the specific implementation, the CPLD will connect the I2C of the SOC with the two I / O ports of the target I2C channel to realize the chip selection of the I2C channel.

[0092] It should be noted that if Figure 4As shown, in this embodiment, the switch SOC chip controls and detects each module through the I2C interface. Since the device addresses of the optical module and the POE chip are mostly repeated addresses, in order to prevent the address conflicts of each device, each time the optical module, POE chip, power supply and other devices are operated, a certain device needs to be selected separately. This design uses CPLD software simulation to realize chip selection, replace programmable devices, and expand the I2C interface of the SOC chip. CPLD simulates the logic of programmable devices, opens the chip select register internally and assigns a number to each I2C channel. When the SOC chip needs to access a certain I2C device, the SOC chip can write the number of the target I2C channel into the chip select register of the CPLD through the I2C interface. The CPLD will internally connect the SOC's I2C with the two I / O ports of the target I2C channel to realize the chip selection of the I2C channel.

[0093] This embodiment obtains multiple target channel numbers by numbering the channels of each module when the high-speed switch control scenario is a channel chip selection scenario; when there is a target module access requirement, the current module number sent by the target chip is received; and the channel chip selection is completed according to the current module number and the multiple target channel numbers. By simulating chip selection through software, programmable devices are replaced, and the I2C interface of the SOC chip is expanded. The SOC chip can write the chip select register of the CPLD through the I2C interface to chip select the I2C channel.

[0094] Based on the first and second embodiments of the present application, in the third embodiment of the present application, the same or similar contents as those of the first and second embodiments can be referred to the above description, and will not be described in detail later. Figure 5 The CPLD-based high-speed switch control method further includes steps S31 to S33:

[0095] Step S31, when the high-speed switch control scene is a lighting control scene, receiving a serial data signal sent by a target chip;

[0096] It can be understood that the light control scene refers to the scene of controlling the flashing of the LED light, and the serial data signal refers to the serial data stream output by the SOC chip according to the port status.

[0097] In a specific implementation, when the high-speed switch control scenario is a scenario of controlling the LED light to flash, the SOC chip receiving the data sent by the SOC chip outputs a serial data stream according to the port state.

[0098] Step S32, converting the serial data signal through a shift register according to the clock signal to obtain a parallel data signal;

[0099] It can be understood that the clock signal refers to a periodic electronic pulse signal that controls the data transmission and processing in the digital circuit, and the parallel data signal refers to a signal form in which multiple data bits are transmitted simultaneously through multiple independent data lines at the same time in a digital electronic system.

[0100] In a specific implementation, according to the periodic electronic pulse signal, the serial data stream output by the SOC chip according to the port state is converted into a corresponding parallel data signal through the CPLD shift register.

[0101] Step S33, performing lighting control according to the parallel data signal.

[0102] It can be understood that each parallel signal is connected to a corresponding LED pin, and the corresponding LED light flashes by outputting '0' and '1'.

[0103] In a feasible implementation, step S33 may include steps A331 to A332:

[0104] Step A331, allocating the parallel data signal to the corresponding output pin and determining the output information;

[0105] It can be understood that the output pin refers to the LED pin (GPIO), and the output information refers to the output '0' or '1' information.

[0106] In a specific implementation, each parallel data signal is distributed to a corresponding LED pin, and output '0' or '1' information is obtained.

[0107] Step A332, when the output information is consistent with the preset information, control the light to flash.

[0108] In a specific implementation, the preset information refers to preset information for controlling the flashing. For example, the preset information for controlling the flashing is '1'. When the output information is '1', the light is controlled to flash.

[0109] It should be noted that if Figure 6 As shown, in this embodiment, the SOC chip has a group of GPIOs dedicated to lighting, which are clock signals and data signals. The SOC chip outputs a serial data stream according to the port status, and then converts the serial signal into a parallel signal according to the clock signal through a shift register. Each parallel signal is connected to the corresponding LED pin, and the corresponding LED light flashes by outputting '0' and '1'. This design uses the internal software of CPLD to realize the function of multi-bit shift registers, replacing the original solution of using multiple shift register chips to splice end to end to realize multi-bit shift registers.

[0110] This embodiment receives the serial data signal sent by the target chip when the high-speed switch control scenario is the lighting control scenario; converts the serial data signal through the shift register according to the clock signal to obtain a parallel data signal; and performs lighting control according to the parallel data signal. The shift register function is realized by using the internal logic of the CPLD to replace the solution of splicing multiple shift register chips end to end, so as to realize the light module LED control.

[0111] Based on the first, second and third embodiments of the present application, in the fourth embodiment of the present application, the same or similar contents as those in the first, second and third embodiments can be referred to the above description, and will not be described in detail later. Figure 7 The CPLD-based high-speed switch control method further includes steps S41 to S42:

[0112] Step S41, when the high-speed switch control scenario is an interrupt reporting scenario, shifting the module interrupt signal into a corresponding interrupt parallel signal;

[0113] It can be understood that the interrupt reporting scenario refers to the interrupt reporting process control scenario, the module interrupt signal refers to the interrupt signal of each module in the switch, and the interrupt parallel signal refers to the module interrupt signal after the parallel signal is converted.

[0114] In a specific implementation, the interrupt signals of each module in the switch are uniformly reported to the CPLD, and the CPLD shifts the input interrupt signals into parallel signals, that is, obtains interrupt parallel signals.

[0115] Step S42, when detecting that a target interrupt event occurs in the interrupt parallel signal, adjusting the level state of the pin and sending the level state of the pin to the target chip, so that the target chip reads the corresponding interrupt register according to the level state of the pin and reports the interrupt.

[0116] It can be understood that the target interrupt event refers to an event in which two adjacent bits of the parallel signal change from '1' to '0'.

[0117] In the specific implementation, when an event is detected that two adjacent bits of the parallel signal change from '1' to '0', the level of the GPIO reported to the SOC chip is pulled down to notify the SOC chip that an interrupt is triggered, and then the SOC chip reads the interrupt register in the CPLD to obtain the interrupt information of each device.

[0118] It should be noted that if Figure 8As shown, in this embodiment, the interrupts of each module of the switch are uniformly reported to the CPLD, and the CPLD shifts the input interrupt signal into a parallel signal, detects the event that two adjacent bits of the parallel signal change from '1' to '0', and stores the event in the register and notifies the SOC chip of the interrupt trigger by lowering the level of the GPIO reported to the SOC chip. After receiving the CPLD report signal, the SOC chip reads the CPLD interrupt register through the I2C interface to obtain the interrupt information of each device. After the SOC chip completes the reading, the CPLD clears the interrupt storage register to prepare for the next interrupt.

[0119] This embodiment shifts the module interrupt signal into the corresponding interrupt parallel signal when the high-speed switch control scenario is an interrupt reporting scenario; when the interrupt parallel signal is detected to have a target interrupt event, the level state of the pin is adjusted and sent to the target chip, so that the target chip reads the corresponding interrupt register according to the level state of the pin and reports the interrupt. By saving the interrupt in the register and waiting for the SOC chip to process it, the SOC chip clears the register after reading the register content to prepare for the next interrupt, and the SOC chip does not need to periodically poll all devices.

[0120] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the CPLD-based high-speed switch control method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0121] This application also provides a high-speed switch control device based on CPLD, please refer to Fig. 9 , the CPLD-based high-speed switch control device comprises:

[0122] The acquisition module 10 is used to collect the level status signal of each module when the high-speed switch control scenario is a status detection scenario;

[0123] The storage module 20 is used to store the level status signal of each module to the corresponding storage register according to the function type corresponding to the level status signal of each module;

[0124] The control module 30 is used to send an event occurrence signal to the target chip when the target event is detected, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection.

[0125] Optionally, the control module 30 is further used for:

[0126] When a target event is detected, a level state signal of a module corresponding to the target event is adjusted to obtain an adjustment state signal;

[0127] An event occurrence signal is generated according to the adjustment state signal, and the event occurrence signal is sent to a target chip.

[0128] Optionally, the control module 30 is further used for:

[0129] When the high-speed switch control scenario is a channel chip selection scenario, the channels of each module are numbered to obtain multiple target channel numbers;

[0130] When there is a need to access the target module, receiving the current module number sent by the target chip;

[0131] Channel chip selection is completed according to the current module number and multiple target channel numbers.

[0132] Optionally, the control module 30 is further used for:

[0133] Store the current module number to the chip select register and determine the corresponding current channel number;

[0134] Determine a corresponding module channel number according to the current channel number and a plurality of target channel numbers;

[0135] The interface of the module channel number is connected to the interface of the target chip to complete the channel chip selection.

[0136] Optionally, the control module 30 is further used for:

[0137] When the high-speed switch control scenario is a lighting control scenario, receiving a serial data signal sent by a target chip;

[0138] Performing signal conversion on the serial data signal through a shift register according to a clock signal to obtain a parallel data signal;

[0139] Lighting control is performed according to the parallel data signal.

[0140] Optionally, the control module 30 is further used for:

[0141] Distributing the parallel data signals to corresponding output pins and determining output information;

[0142] When the output information is consistent with the preset information, the light is controlled to flash.

[0143] Optionally, the control module 30 is further used for:

[0144] When the high-speed switch control scenario is an interrupt reporting scenario, the module interrupt signal is shifted into a corresponding interrupt parallel signal;

[0145] When a target interrupt event is detected in the interrupt parallel signal, the level state of the pin is adjusted and the level state of the pin is sent to the target chip, so that the target chip reads the corresponding interrupt register according to the level state of the pin and reports the interrupt.

[0146] The CPLD-based high-speed switch control device provided by the present application adopts the CPLD-based high-speed switch control method in the above embodiment, which can solve the technical problem of cumbersome operation of the existing switch system status monitoring process. Compared with the prior art, the beneficial effects of the CPLD-based high-speed switch control device provided by the present application are the same as the beneficial effects of the CPLD-based high-speed switch control method provided by the above embodiment, and other technical features in the CPLD-based high-speed switch control device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0147] The present application provides a CPLD-based high-speed switch control device, the CPLD-based high-speed switch control device comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the CPLD-based high-speed switch control method in the above-mentioned embodiment 1.

[0148] Reference below Fig.10 , which shows a schematic diagram of the structure of a CPLD-based high-speed switch control device suitable for implementing the embodiment of the present application. The CPLD-based high-speed switch control device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.10 The CPLD-based high-speed switch control device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0149] like Fig.10As shown, the CPLD-based high-speed switch control device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. Various programs and data required for the operation of the CPLD-based high-speed switch control device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 may allow the CPLD-based high-speed switch control device to communicate wirelessly or wired with other devices to exchange data. Although the CPLD-based high-speed switch control device with various systems is shown in the figure, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have alternatively.

[0150] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0151] The CPLD-based high-speed switch control device provided by the present application adopts the CPLD-based high-speed switch control method in the above embodiment, which can solve the technical problem of cumbersome operation of the existing switch system status monitoring process. Compared with the prior art, the beneficial effects of the CPLD-based high-speed switch control device provided by the present application are the same as the beneficial effects of the CPLD-based high-speed switch control method provided in the above embodiment, and other technical features in the CPLD-based high-speed switch control device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0152] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0153] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0154] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the CPLD-based high-speed switch control method in the above-mentioned embodiment.

[0155] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0156] The computer-readable storage medium may be included in the CPLD-based high-speed switch control device; or may exist independently without being assembled into the CPLD-based high-speed switch control device.

[0157] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a CPLD-based high-speed switch control device, the CPLD-based high-speed switch control device: when the high-speed switch control scenario is a status detection scenario, collects the level status signal of each module; stores the level status signal of each module to a corresponding storage register according to the function type corresponding to the level status signal of each module; and when a target event is detected, sends an event occurrence signal to a target chip, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection.

[0158] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0159] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0160] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0161] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned CPLD-based high-speed switch control method, and can solve the technical problem of cumbersome operation of the existing switch system status monitoring process. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the CPLD-based high-speed switch control method provided by the above-mentioned embodiment, and will not be repeated here.

[0162] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned CPLD-based high-speed switch control method when executed by a processor.

[0163] The computer program product provided by the present application can solve the technical problem of cumbersome operation of the existing switch system status monitoring process. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the CPLD-based high-speed switch control method provided in the above embodiment, which will not be repeated here.

[0164] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A high-speed switch control method based on CPLD, characterized in that: The CPLD-based high-speed switch control method comprises: When the high-speed switch control scenario is a status detection scenario, the level status signal of each module is collected; According to the function type corresponding to the level state signal of each module, the level state signal of each module is stored in the corresponding storage register; When the target event is detected to occur, an event occurrence signal is sent to the target chip, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the state detection.

2. The method according to claim 1, characterized in that When the target event is detected, sending an event occurrence signal to the target chip includes: When a target event is detected, a level state signal of a module corresponding to the target event is adjusted to obtain an adjustment state signal; An event occurrence signal is generated according to the adjustment state signal, and the event occurrence signal is sent to a target chip.

3. The method according to claim 1, characterized in that The CPLD-based high-speed switch control method also includes: When the high-speed switch control scenario is a channel chip selection scenario, the channels of each module are numbered to obtain multiple target channel numbers; When there is a need to access the target module, receiving the current module number sent by the target chip; Channel chip selection is completed according to the current module number and multiple target channel numbers.

4. The method according to claim 3, characterized in that The completing channel chip selection according to the current module number and multiple target channel numbers includes: Store the current module number to the chip select register and determine the corresponding current channel number; Determine a corresponding module channel number according to the current channel number and a plurality of target channel numbers; The interface of the module channel number is connected to the interface of the target chip to complete the channel chip selection.

5. The method according to claim 1, characterized in that The CPLD-based high-speed switch control method also includes: When the high-speed switch control scenario is a lighting control scenario, receiving a serial data signal sent by a target chip; Performing signal conversion on the serial data signal through a shift register according to a clock signal to obtain a parallel data signal; Lighting control is performed according to the parallel data signal.

6. The method according to claim 5, characterized in that The performing lighting control according to the parallel data signal comprises: Distributing the parallel data signals to corresponding output pins and determining output information; When the output information is consistent with the preset information, the light is controlled to flash.

7. The method according to claim 1, characterized in that The CPLD-based high-speed switch control method also includes: When the high-speed switch control scenario is an interrupt reporting scenario, the module interrupt signal is shifted into a corresponding interrupt parallel signal; When a target interrupt event is detected in the interrupt parallel signal, the level state of the pin is adjusted and the level state of the pin is sent to the target chip, so that the target chip reads the corresponding interrupt register according to the level state of the pin and reports the interrupt.

8. A high-speed switch control device based on CPLD, characterized in that: The device comprises: The acquisition module is used to collect the level status signals of each module when the high-speed switch control scenario is a status detection scenario; A storage module, used for storing the level status signal of each module to a corresponding storage register according to the function type corresponding to the level status signal of each module; The control module is used to send an event occurrence signal to the target chip when the target event is detected, so that the target chip reads the corresponding storage register according to the event occurrence signal to complete the status detection.

9. A high-speed switch control device based on CPLD, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the CPLD-based high-speed switch control method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the CPLD-based high-speed switch control method according to any one of claims 1 to 7 are implemented.

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