Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and a storage system, and the semiconductor device comprises a first semiconductor structure which comprises a stacking structure stacked along a second direction, the stacking structure comprises a plurality of gate layers which are spaced along the second direction, and the plurality of gate layers respectively form a plurality of step surfaces in a step region; the plurality of gate contact parts are located in the step region, penetrate through the plurality of step surfaces and are respectively connected with the plurality of gate layers, and each gate contact part comprises a first contact end and a second contact end which are located on the two opposite sides of the stacking structure in the second direction; the second semiconductor structure is located on one side of the first semiconductor structure in the second direction, is arranged close to the first contact end and comprises a first peripheral circuit, and the first peripheral circuit is connected with the first contact end of the gate contact part; the third semiconductor structure is located on the side, away from the second semiconductor structure, of the first semiconductor structure in the second direction and comprises a second peripheral circuit, and the second peripheral circuit is connected with the second contact end of the gate contact part.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] In recent years, the development of memory has been particularly rapid. The main feature of memory is that it can retain stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasure and rewriting, etc. Therefore, it has been widely used in many fields such as microcomputers and automatic control.

[0003] As memory wiring becomes more and more complex, how to simplify memory wiring becomes an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a storage system to simplify the wiring of the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0006] A first semiconductor structure, wherein the first semiconductor structure comprises a storage area and a step area adjacent to each other along a first direction, and the first semiconductor structure comprises:

[0007] a stacked structure stacked along a second direction, the stacked structure comprising a plurality of gate layers spaced apart along the second direction, the plurality of gate layers respectively forming a plurality of step surfaces in the step region, the second direction intersecting the first direction; and

[0008] A plurality of gate contacts, located in the step region, penetrating through the plurality of step surfaces and respectively connected to the plurality of gate layers, the gate contacts comprising a first contact end and a second contact end located at opposite sides of the stack structure in the second direction;

[0009] a second semiconductor structure located at one side of the first semiconductor structure in the second direction and disposed close to the first contact end, and comprising a first peripheral circuit connected to the first contact end of the gate contact portion; and

[0010] The third semiconductor structure is located on a side of the first semiconductor structure away from the second semiconductor structure in the second direction and includes a second peripheral circuit connected to the second contact end of the gate contact portion.

[0011] In a second aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0012] Providing a first semiconductor layer, wherein the first semiconductor layer has a first region and a second region adjacent to each other along a first direction;

[0013] Forming a stacking structure stacked along a second direction on the first semiconductor layer, the stacking structure comprising a plurality of gate layers spaced apart along the second direction, the plurality of gate layers respectively forming a plurality of step surfaces in the first region, and the second direction intersecting with the first direction;

[0014] forming a plurality of gate contacts in the first region, the plurality of gate contacts penetrating the plurality of step surfaces and respectively connected to the plurality of gate layers, the gate contacts comprising a first contact end and a second contact end located at opposite sides of the stack structure in the second direction, the second contact end of the gate contact extending into the first semiconductor layer;

[0015] forming a first peripheral circuit on the second semiconductor layer, disposing the first peripheral circuit between the second semiconductor layer and the stacked structure in the second direction, and connecting the first peripheral circuit and the first contact end of the gate contact portion; and

[0016] A second peripheral circuit is formed on the third semiconductor layer, and is disposed on a side of the stack structure away from the second semiconductor layer in the second direction, and is connected to the second contact end of the gate contact portion.

[0017] In a third aspect, the present application provides a storage system, the storage system comprising:

[0018] A memory, comprising the semiconductor device of any of the above embodiments; and

[0019] The controller is connected to the memory and is used to control the memory.

[0020] In some embodiments of the present application, multiple gate contacts are located in the step region, the multiple gate contacts penetrate multiple step surfaces and are respectively connected to multiple gate layers, the gate contacts include a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction, the first peripheral circuit of the second semiconductor structure is connected to the first contact end of the gate contact, and the second peripheral circuit of the third semiconductor structure is connected to the second contact end of the gate contact. Through this design, bidirectional lead-out of the gate contact is achieved, the wiring concentration of the wires connecting the gate contact with the first peripheral circuit and the second peripheral circuit is reduced, and the wiring in the semiconductor device is simplified.

[0021] Moreover, on the basis of the bidirectional lead-out of the gate contact, the first peripheral circuit is connected to the first contact end of the gate contact, and the second peripheral circuit is connected to the second contact end of the gate contact. With this design, the first peripheral circuit and the second peripheral circuit are respectively connected to the opposite sides of the first semiconductor structure, which is conducive to expanding the process window of the first peripheral circuit and the second peripheral circuit, thereby reducing the process manufacturing difficulty of the first peripheral circuit and the second peripheral circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0023] Figures 2 to 11 A schematic diagram of the structure of a semiconductor device for manufacturing some embodiments of the present application;

[0024] Figures 12 to 16 A schematic diagram of the structure of a semiconductor device for manufacturing other embodiments of the present application;

[0025] Fig.17 A block diagram of a storage system according to some embodiments of the present application;

[0026] Fig.18 A block diagram of a storage system according to some other embodiments of the present application;

[0027] Fig.19 A block diagram of an electronic device according to some embodiments of the present application.

[0028] The accompanying drawings are marked as follows:

[0029] 100, semiconductor device; 200, memory; 300, controller; 400, storage system; 500, electronic device; 600, host;

[0030] 1, first semiconductor structure; 1', first initial semiconductor structure; 1a, storage area; 1b, step area; 1c, peripheral area;

[0031] 01, first semiconductor layer; 01a, first region; 01b, second region; 01c, third region; 01d1, first semiconductor layer opening; 01d2, second semiconductor layer opening;

[0032] 11, stacking structure; 111, gate layer; 111a, step surface; 11a, stacking layer; 112, sacrificial layer; 113, gate dielectric layer; 1111, first gate layer; 1112, second gate layer; 1113, third gate layer; 1114, fourth gate layer;

[0033] 12, gate contact portion; 121, penetration portion; 122, contact portion; 123, gate contact insulating portion; 12a, first contact end; 12b, second contact end;

[0034] 13, isolation layer;

[0035] 141, a first wire; 142, a second wire; 143, a third wire; 144, a fourth wire; 145, a fifth wire;

[0036] 152, a third bonding layer; 1521, a third bonding contact;

[0037] 16, channel structure; 16a, first channel connection end; 16b, second channel connection end; 162, functional layer; 161, channel layer;

[0038] 17, common source;

[0039] 181, first through-array connection contact; 1811, first conductive connection portion; 1812, first insulating portion;

[0040] 182, second through-array connection contact; 1821, second conductive connection portion; 1822, second insulating portion;

[0041] 19, dielectric layer;

[0042] 2, second semiconductor structure; 02, second semiconductor layer; 21, first peripheral circuit; 211, first string driving circuit; 212, first page buffer circuit; 22, fourth bonding layer; 221, fourth bonding contact;

[0043] 3', third initial semiconductor structure; 3, third semiconductor structure; 03, third semiconductor layer; 31, second peripheral circuit; 311, second series driving circuit; 312, second page buffer circuit; 32, second bonding layer; 321, second bonding contact; 33, connection contact; 331, first connection contact; 332, second connection contact;

[0044] 4, pad portion; 41, first pad portion; 42, second pad portion;

[0045] x, first direction; z, second direction. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0047] Please refer to Figure 1 As shown, it is a schematic flow chart of a method for manufacturing a semiconductor device in some embodiments of the present application. The method for manufacturing a semiconductor device comprises the following steps:

[0048] S101: providing a first semiconductor layer, wherein the first semiconductor layer has a first region and a second region adjacent to each other along a first direction;

[0049] S102: forming a stacked structure stacked along a second direction on the first semiconductor layer, the stacked structure comprising a plurality of gate layers spaced apart along the second direction, the plurality of gate layers respectively forming a plurality of step surfaces in the first region, and the second direction intersecting the first direction;

[0050] S103: forming a plurality of gate contacts in the first region, the plurality of gate contacts penetrating the plurality of step surfaces and respectively connected to the plurality of gate layers, the gate contacts comprising a first contact end and a second contact end located at opposite sides of the stack structure in the second direction, the second contact end of the gate contact extending into the first semiconductor layer;

[0051] S104: forming a first peripheral circuit on the second semiconductor layer, disposing the first peripheral circuit between the second semiconductor layer and the stacked structure in the second direction, and connecting the first peripheral circuit to a first contact end of the gate contact portion; and

[0052] S105: forming a second peripheral circuit on the third semiconductor layer, disposing the second peripheral circuit on a side of the stack structure away from the second semiconductor layer in the second direction, and connecting the second peripheral circuit to a second contact end of the gate contact portion.

[0053] In some embodiments of the present application, multiple gate contacts are formed that penetrate multiple step surfaces and are respectively connected to multiple gate layers, and the gate contacts include a first contact end and a second contact end located on opposite sides of the stack structure in the second direction. Through this method, the gate contact can be connected to the peripheral circuit through the first contact end and the second contact end, that is, the gate contact can be led out in both directions, which provides conditions for multiple chips including peripheral circuits to be arranged on opposite sides of the stack structure, while reducing the concentration of wiring connecting the gate contact and the peripheral circuit, which is conducive to simplifying the wiring design of the semiconductor device.

[0054] In addition, on the basis that the gate contact can be led out in both directions, the first peripheral circuit is connected to the first contact end of the gate contact, and the second peripheral circuit is connected to the second contact end of the gate contact. Through this method, the first peripheral circuit and the second peripheral circuit are respectively connected to the opposite sides of the stacking structure, which is conducive to expanding the process window of the first peripheral circuit and the second peripheral circuit, thereby reducing the process manufacturing difficulty of the first peripheral circuit and the second peripheral circuit.

[0055] Please refer to Figures 2 to 11 , which is a schematic diagram of the structure of the semiconductor device of some embodiments of the present application. Figure 1 , Figures 2 to 11 The manufacturing methods of semiconductor devices according to some embodiments of the present application are described in detail.

[0056] First, refer to Figure 2 As shown, step S101 is performed: providing a first semiconductor layer 01 , wherein the first semiconductor layer 01 has a first region 01 a and a second region 01 b adjacent to each other along a first direction x.

[0057] In some embodiments, the first semiconductor layer 01 has a first region 01a, a second region 01b, and a third region 01c. The first region 01a is adjacent to the second region 01b along a first direction x. The third region 01c is adjacent to the second region 01b along a first direction x. In the first region 01a, a gate contact 12 hereinafter is connected to the gate layer 111. The second region 01b is used to form a memory array. The third region 01c is located outside the first region 01a and the second region 01b.

[0058] Exemplarily, the first semiconductor layer 01 includes two first regions 01a and two second regions 01b, but is not limited thereto. In the first direction x, the two first regions 01a are adjacently arranged, and the two second regions 01b are located on opposite sides of the two first regions 01a. The third region 01c is arranged around the two second regions 01b.

[0059] Next, refer to Figure 3 As shown, step S102 is performed to form a stacking structure 11 stacked along the second direction z on the first semiconductor layer 01, the stacking structure 11 includes a plurality of gate layers 111 spaced apart along the second direction z, the plurality of gate layers 111 respectively form a plurality of step surfaces 111a in the first region 01a, and the second direction z intersects with the first direction x.

[0060] Exemplarily, the second direction z is perpendicular to the first direction x, but is not limited thereto.

[0061] In some embodiments, reference Figure 2 As shown, a stacking structure 11 stacked along a second direction z is formed on the first semiconductor layer 01, including: a stacking layer 11a stacked along the second direction z is formed on the first semiconductor layer 01, and the stacking layer 11a includes a plurality of sacrificial layers 112 and a plurality of gate dielectric layers 113 alternately arranged along the second direction z.

[0062] Exemplarily, the material of the plurality of sacrificial layers 112 includes, but is not limited to, silicon nitride. The material of the plurality of gate dielectric layers 113 includes, but is not limited to, silicon oxide.

[0063] In some embodiments, forming the stacked structure 11 stacked along the second direction z on the first semiconductor layer 01 further includes: replacing the plurality of sacrificial layers 112 with a plurality of gate layers 111 to obtain the stacked structure 11 .

[0064] It should be noted that by Figure 2 After the multiple sacrificial layers 112 of the semiconductor structure are replaced by multiple gate layers 111, the Figure 3 A first initial semiconductor structure 1 ′ is shown.

[0065] In some embodiments, the plurality of gate layers 111 respectively form a plurality of step surfaces 111 a in the first region 01 a .

[0066] Exemplarily, the plurality of gate layers 111 include a first gate layer 1111, a second gate layer 1112, a third gate layer 1113, and a fourth gate layer 1114. The first gate layer 1111 and the second gate layer 1112 are respectively located in the two first regions 01a and are arranged in the same layer. The third gate layer 1113 and the fourth gate layer 1114 are respectively located in the two first regions 01a and are arranged in the same layer.

[0067] It should be noted that the two elements arranged in the same layer are coplanar or substantially coplanar in the first direction x.

[0068] Exemplarily, the material of the gate layer 111 includes, but is not limited to, metals, and the metals include, but are not limited to, tungsten, cobalt, copper, nickel, and combinations thereof.

[0069] Next, please refer to Figure 3 As shown, step S103 is performed: a plurality of gate contacts 12 are formed in the first region 01a, the plurality of gate contacts 12 penetrate the plurality of step surfaces 111a, and are respectively connected to the plurality of gate layers 111, the gate contact 12 includes a first contact end 12a and a second contact end 12b located on opposite sides of the stack structure 11 in the second direction z, and the second contact end 12b of the gate contact 12 extends into the first semiconductor layer 01.

[0070] In some embodiments, reference Figure 2 As shown, the forming of the plurality of gate contacts 12 in the first region 01 a includes: forming the plurality of gate contacts 12 penetrating the stacked layer 11 a in the first region 01 a and extending into the first semiconductor layer 01 .

[0071] It should be noted that after the multiple sacrificial layers 112 are replaced by multiple gate layers 111 , the multiple gate contacts 12 penetrate the stacked structure 11 and are respectively connected to the multiple gate layers 111 .

[0072] In some embodiments, the gate contact portion 12 includes a penetration portion 121 and a contact portion 122, both of which extend along the second direction z, and the penetration portion 121 is connected to the contact portion 122. The penetration portion 121 penetrates the stacked structure 11 and extends into the first semiconductor layer 01, and one end of the penetration portion 121 away from the contact portion 122 is a second contact end 12b. One end of the contact portion 122 away from the penetration portion 121 is a first contact end 12a, and the contact portion 122 is also in contact with the step surface 111a of the gate layer 111, so that the gate contact portion 12 is connected to the gate layer 111.

[0073] In some embodiments, the dimension of the through portion 121 along the first direction x is smaller than the dimension of the contact portion 122 along the first direction x, so that the contact portion 122 contacts the step surface 111 a of the gate layer 111 to achieve connection between the gate contact portion 12 and the gate layer 111 .

[0074] In some embodiments, the gate contact portion 12 further includes a gate contact insulating portion 123 , which covers the through portion 121 and the sidewalls of the contact portion 122 extending along the second direction z, and also covers the bottom wall of the through portion 121 in the first semiconductor layer 01 .

[0075] Exemplarily, the material of the through portion 121 and the contact portion 122 includes metal, including but not limited to tungsten, cobalt, copper, nickel and combinations thereof. The material of the gate contact insulating portion 123 includes but not limited to silicon nitride, silicon oxide, silicon oxynitride and combinations thereof.

[0076] In some embodiments, reference Figure 2 As shown, before replacing the multiple sacrificial layers 112 with multiple gate layers 111, the above method also includes: forming a plurality of channel structures 16 penetrating the stacked layer 11a along the second direction z in the second region 01b, the plurality of channel structures 16 including a first channel connection end 16a and a second channel connection end 16b located on opposite sides of the stacked layer 11a in the second direction z, and the second channel connection end 16b of the channel structure 16 extends into the first semiconductor layer 01.

[0077] In some embodiments, the channel structure 16 includes a functional layer 162 and a channel layer 161 arranged from outside to inside. The functional layer 162 includes a blocking layer, a charge trapping layer, and a tunneling layer arranged in sequence from outside to inside. The channel layer 161 extends along the second direction z, and its opposite ends in the second direction z include a first channel connection end 16a and a second channel connection end 16b.

[0078] For example, the blocking layer, the charge trapping layer and the tunneling layer may be of a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The material of the channel layer 161 includes, but is not limited to, polysilicon.

[0079] It should be noted that after the multiple sacrificial layers 112 are replaced by multiple gate layers 111 , the channel structure 16 penetrates the stack structure 11 along the second direction z, and the first channel connection end 16a and the second channel connection end 16b of the channel structure 16 are located on opposite sides of the stack structure 11 .

[0080] In some embodiments of the present application, the channel structure 16 and the gate contact 12 both penetrate the stacked structure 11, which facilitates the use of one mask to prepare the channel hole filling the channel structure 16 and the gate contact hole filling the gate contact 12, thereby reducing the number of masks required to manufacture semiconductor devices and reducing the cost required to manufacture semiconductor devices.

[0081] In some embodiments, reference Figure 2 As shown, before replacing the multiple sacrificial layers 112 with multiple gate layers 111, the method further includes: forming a dielectric layer 19 in the third region 01c and the first region 01a, the dielectric layer 19 covers the stacked layer 11a of the first region 01a and fills the third region 01c.

[0082] Exemplarily, the material of the dielectric layer 19 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof. Specifically, the material of the dielectric layer 19 includes silicon oxide.

[0083] In some embodiments, reference Figure 2 As shown, the method further includes: forming a first through array connection pad 181 on the first semiconductor layer 01 in the third region 01 c , wherein the first through array connection pad 181 extends into the first semiconductor layer 01 along the second direction z.

[0084] In some embodiments of the present application, at least one of the first peripheral circuit and the second peripheral circuit is connected to an external circuit through the first through-array connection contact 181 .

[0085] In some embodiments, the first through-array connection contact 181 penetrates the dielectric layer 19 in the third region 01 c and extends into the first semiconductor layer 01 .

[0086] In some embodiments, the first through-array connection contact 181 includes a first conductive connection portion 1811 and a first insulating portion 1812, the first conductive connection portion 1811 extends along the second direction z, the first insulating portion 1812 covers the side wall of the first conductive connection portion 1811 extending along the second direction z, and the first insulating portion 1812 also covers the bottom wall of the first conductive connection portion 1811 located in the first semiconductor layer 01.

[0087] In some embodiments, reference Figure 2As shown, the method further includes: forming a second through-array connection contact 182 extending along a second direction z on the first semiconductor layer 01 , wherein the second through-array connection contact 182 extends into the first semiconductor layer 01 .

[0088] In some embodiments of the present application, the second through-array connection contact 182 is connected between the first peripheral circuit and the second peripheral circuit. In other words, the second through-array connection contact 182 is used to connect the first peripheral circuit and the second peripheral circuit.

[0089] In some embodiments, forming the second through-array connecting contact 182 extending along the second direction z on the first semiconductor layer 01 includes: forming the second through-array connecting contact 182 in one of the third region 01c and the first region 01a.

[0090] For example, refer to Figure 2 As shown, a second through array connection contact 182 is formed in the third region 01c. The second through array connection contact 182 penetrates the dielectric layer 19 and extends into the first semiconductor layer 01. The second through array connection contact 182 is spaced apart from the first through array connection contact 181.

[0091] In some embodiments, the second through-array connection contact 182 includes a second conductive connection portion 1821 and a second insulating portion 1822 , wherein the second insulating portion 1822 covers the side walls of the second conductive connection portion 1821 extending along the second direction z, and the second insulating portion 1822 also covers the bottom wall of the second conductive connection portion 1821 located in the first semiconductor layer 01 .

[0092] Exemplarily, the materials of the second conductive connection part 1821 and the first conductive connection part 1811 both include metals, including but not limited to tungsten, cobalt, copper, nickel and combinations thereof. The materials of the first insulating part 1812 and the second insulating part 1822 include but are not limited to silicon nitride, silicon oxide, silicon oxynitride and combinations thereof.

[0093] In some embodiments, reference Figure 2 As shown, the method further includes: forming a third wire 143 on a side of the gate contact portion 12 away from the first semiconductor layer 01, the third wire 143 is connected to the first contact ends 12a of at least two gate contacts 12, and the at least two gate contacts 12 connected to the third wire 143 are respectively connected to at least two gate layers 111 located in the two first regions 01a and arranged in the same layer. With this design, when a signal is applied to one third wire 143, at least two gate layers 111 located in the same layer can be driven simultaneously.

[0094] Exemplarily, the first contact ends 12 a of the two gate contacts 12 respectively connected to the first gate layer 1111 and the second gate layer 1112 are both connected to the third wire 143 .

[0095] In some embodiments, reference Figure 2 As shown, the method further includes: forming a third bonding contact 1521 , wherein the third bonding contact 1521 is located on a side of the third wire 143 away from the first semiconductor layer 01 in the second direction z.

[0096] In some embodiments, a third bonding layer 152 is formed on a side of the third conductive line 143 away from the first semiconductor layer 01 , and the third bonding layer 152 includes a plurality of third bonding contacts 1521 .

[0097] In some embodiments, a plurality of third bonding contacts 1521 are respectively connected to the third wire 143, the first channel connection end 16a of the channel structure 16, the first through array connection contact 181, and the second through array connection contact 182. Since the third bonding contact 1521 is connected to the third wire 143, the third bonding contact 1521 is connected to the first contact end 12a of the gate contact 12.

[0098] Through the above steps S101, S102, S103 and other steps, we can obtain Figure 3 A first initial semiconductor structure 1 ′ is shown.

[0099] Next, refer to Figures 4 to 5 As shown, step S104 is performed to form a first peripheral circuit 21 on the second semiconductor layer 02 , and the first peripheral circuit 21 is disposed between the second semiconductor layer 02 and the stacked structure 11 in the second direction z, and the first peripheral circuit 21 is connected to the first contact end 12a of the gate contact portion 12 .

[0100] In some embodiments, reference Figure 4 As shown, the first peripheral circuit 21 includes a first string driving circuit 211, which is used to connect to the first contact end 12a of the gate contact 12 to drive the gate layer 111 connected to the gate contact 12. The first string driving circuit 211 includes at least one high-voltage transistor.

[0101] In some embodiments, the first peripheral circuit 21 further includes a first page buffer circuit 212, which is used to connect to the first channel connection terminal 16a of the channel structure 16 to drive the channel structure 16. The first page buffer circuit 212 includes at least one of a high voltage transistor and a low voltage transistor.

[0102] Exemplarily, the first page buffer circuit 212 includes a high voltage transistor and a low voltage transistor.

[0103] In some embodiments, reference Figure 4 As shown, the method further includes: forming a fourth bonding contact 221 on a side of the first peripheral circuit 21 away from the second semiconductor layer 02 , and the fourth bonding contact 221 is connected to the first peripheral circuit 21 .

[0104] Exemplarily, the plurality of fourth bonding contacts 221 are respectively connected to the first page buffer circuit 212 and the first string driving circuit 211 .

[0105] In some embodiments, forming the fourth bonding contact 221 on the side of the first peripheral circuit 21 away from the second semiconductor layer 02 includes: forming a fourth bonding layer 22 on the side of the first peripheral circuit 21 away from the second semiconductor layer 02 , the fourth bonding layer 22 including the fourth bonding contact 221 .

[0106] In some embodiments of the present application, by forming a first peripheral circuit 21 and a fourth bonding layer 22 on the second semiconductor layer 02, a Figure 4 The second semiconductor structure 2 is shown.

[0107] In some embodiments, reference Figure 5 As shown, disposing the first peripheral circuit 21 between the second semiconductor layer 02 and the stacked structure 11 in the second direction z includes: Figure 3 The first initial semiconductor structure 1' is flipped and placed Figure 4 On the second semiconductor structure 2 shown, the first semiconductor layer 01 of the first initial semiconductor structure 1 ′ is located at a side of the stacked structure 11 away from the second semiconductor structure 2 .

[0108] In some embodiments, after placing the first initial semiconductor structure 1 ′ on the second semiconductor structure 2 , the method further includes: bonding the third bonding contact 1521 and the fourth bonding contact 221 .

[0109] In some embodiments of the present application, by bonding the third bonding contact 1521 and the fourth bonding contact 221, the first peripheral circuit 21 is connected to the third wire 143, the first channel connection end 16a of the channel structure 16, the first through-array connection contact 181 and the second through-array connection contact 182.

[0110] The first page buffer circuit 212 is connected to the second through-array connection contact 182 and the first channel connection terminal 16a of the channel structure 16. The first string driving circuit 211 is connected to the first contact terminals 12a of at least two gate contacts 12 through the third wire 143.

[0111] In some embodiments, the first contact terminal 12a connecting the first peripheral circuit 21 and the gate contact portion 12 includes: among two adjacent gate contacts 12, the first contact terminal 12a of one gate contact portion 12 is connected to the first peripheral circuit 21, and the other gate contact portion 12 is connected to the second peripheral circuit described below through the second contact terminal 12b. In this way, the two adjacent gate contacts 12 are respectively led out from different contact terminals, reducing the concentration and difficulty of the wiring connecting the first contact terminal 12a of the gate contact portion 12 and the first peripheral circuit 21.

[0112] Exemplarily, in a first region 01a, two gate contacts 12 respectively connected to the first gate layer 1111 and the third gate layer 1113 are adjacent in the first direction x, the first contact end 12a of the gate contact 12 connected to the first gate layer 1111 is connected to the first peripheral circuit 21, while the first contact end 12a of the gate contact 12 connected to the third gate layer 1113 is not connected to the first peripheral circuit 21.

[0113] In some embodiments, the first contact end 12a connecting the first peripheral circuit 21 and the gate contact 12 further includes: the first contact ends 12a of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed on the same layer are connected to the first peripheral circuit 21. In this way, one third wire 143 can connect the first contact ends 12a of at least two gate contacts 12 to drive the at least two gate layers 111 disposed on the same layer, and the number of wires connected to the first contact ends 12a of the gate contacts 12 is reduced.

[0114] Exemplarily, in the first direction x, the first gate layer 1111 and the second gate layer 1112 are arranged in the same layer, so that the first contact ends 12a of the two gate contacts 12 connected to the first gate layer 1111 and the second gate layer 1112 are connected to the first peripheral circuit 21 through the third wire 143.

[0115] Please refer to Figure 6 As shown, after connecting the first initial semiconductor structure 1 ′ and the second semiconductor structure 2 , the method further includes: removing the first semiconductor layer 01 in the first region 01 a to form a first semiconductor layer opening 01 d 1 and expose the second contact ends 12 b of the plurality of gate contacts 12 .

[0116] In some embodiments, the first semiconductor layer 01 in the first region 01a is removed while the first semiconductor layer 01 in the third region 01c is removed to form a first semiconductor layer opening 01d1 and expose the second conductive connection portion 1821 of the second through-array connection pad 182 and the first conductive connection portion 1811 of the first through-array connection pad 181.

[0117] Exemplarily, an etching process is used to remove the first semiconductor layer 01 of the first region 01a and the third region 01c, and then an etching process is used to remove the gate contact insulating portion 123 covering the second contact end 12b of the gate contact portion 12, and an etching process is used to remove the first insulating portion 1812 covering the bottom wall of the first conductive connection portion 1811 and the second insulating portion 1822 covering the bottom wall of the second conductive connection portion 1821.

[0118] Please refer to Figure 7 As shown, the method further includes: forming an isolation layer 13 in the first semiconductor layer opening 01 d 1 , and the second contact ends 12 b of the plurality of gate contacts 12 all extend into the isolation layer 13 .

[0119] In some embodiments, the isolation layer 13 also covers the second through-array connection pads 182 and the first through-array connection pads 181 .

[0120] Exemplarily, the material of the isolation layer 13 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

[0121] In some embodiments, please refer to Figure 8 As shown, after forming the isolation layer 13 , the method further includes: removing the first semiconductor layer 01 in the second region 01 b to form a second semiconductor layer opening 01 d 2 and expose the second channel connection ends 16 b of the plurality of channel structures 16 .

[0122] Exemplarily, an etching process is used to remove the first semiconductor layer 01 in the second region 01 b , and an etching process is used to remove the functional layer 162 outside the second channel connection end 16 b .

[0123] In some embodiments, please refer to Fig. 9 As shown, a common source 17 is formed in the second semiconductor layer opening 01 d 2 , and the second channel connection ends 16 b of the plurality of channel structures 16 extend into the common source 17 and contact the common source 17 .

[0124] In some embodiments, the material of the common source 17 includes, but is not limited to, metal or polysilicon. Exemplarily, the material of the common source 17 includes polysilicon.

[0125] In other embodiments, after removing the first semiconductor layer 01 from the first region 01a, the second region 01b and the third region 01c, an isolation layer 13 is formed at the position where the first semiconductor layer 01 is removed, an isolation layer opening is formed on the isolation layer 13, and a common source 17 is formed in the isolation layer opening. The common source 17 is connected to the second channel connection ends 16b of the multiple channel structures 16.

[0126] In some embodiments, please refer to Fig. 9As shown, after forming the common source 17 , the method further includes: forming a first wire 141 on a side of the isolation layer 13 away from the stack structure 11 in the second direction z, and connecting the first wire 141 to the second contact end 12 b of the gate contact 12 .

[0127] In some embodiments, the second contact ends 12 b of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed in the same layer are connected to the first wire 141 to reduce the number of wirings connected to the second contact ends 12 b of the gate contacts 12 .

[0128] Exemplarily, the second contact ends 12 b of the two gate contacts 12 connected to the third gate layer 1113 and the fourth gate layer 1114 disposed in the same layer are connected to the first wire 141 .

[0129] In some embodiments, the method further includes: forming a second conductive line 142 on a side of the common source 17 away from the stack structure 11 in the second direction z, wherein the second conductive line 142 is connected to the common source 17 .

[0130] Exemplarily, the second conductive line 142 is connected to at least two common sources 17 to reduce the number of wirings connected to the common source 17 .

[0131] In some embodiments, the above method also includes: forming a fourth conductive wire 144 and a fifth conductive wire 145 on the side of the isolation layer 13 away from the stacking structure 11 in the second direction z, and connecting the fourth conductive wire 144 to the first conductive connection portion 1811 of the first through-array connecting contact 181, and connecting the fifth conductive wire 145 to the second conductive connection portion 1821 of the second through-array connecting contact 182.

[0132] In some embodiments, the first wire 141 , the second wire 142 , the fourth wire 144 and the fifth wire 145 are obtained by patterning a conductive layer, and therefore, the first wire 141 , the second wire 142 , the fourth wire 144 and the fifth wire 145 are located in the same layer.

[0133] In some other embodiments, the first conductive line 141 , the second conductive line 142 , the fourth conductive line 144 , and the fifth conductive line 145 may also be located in different layers.

[0134] In some embodiments, please refer to Fig. 9 As shown, the method further includes: forming a first bonding contact 1511 on a side of the first conductive line 141 away from the stack structure 11 in the second direction z, wherein the first bonding contact 1511 is connected to the first conductive line 141 .

[0135] In some embodiments, a first bonding layer 151 is formed on a side of the first wire 141 away from the stacking structure 11 in the second direction z, and the first bonding layer 151 includes a plurality of first bonding contacts 1511, and the plurality of first bonding contacts 1511 are respectively connected to the first wire 141, the second wire 142, the fourth wire 144 and the fifth wire 145.

[0136] In some embodiments of the present application, since the multiple first bonding contacts 1511 are respectively connected to the first wire 141, the second wire 142, the fourth wire 144 and the fifth wire 145, the multiple first bonding contacts 1511 are respectively connected to the first through-array connecting contact 181, the second through-array connecting contact 182, the second channel connecting end 16b of the channel structure 16 and the second contact end 12b of the gate contact 12.

[0137] In some embodiments of the present application, through the above steps, Fig. 9 The first semiconductor structure 1 shown includes a storage area 1a, a step area 1b and a peripheral area 1c. The stacked structure 11 is located in the storage area 1a and the step area 1b, and the step surface 111a of the gate layer 111 is located in the step area 1b. The first through-array connection contact 181 and the second through-array connection contact 182 are located in the peripheral area 1c.

[0138] It should be noted that the storage area 1a corresponds to the second area 01b, the step area 1b corresponds to the first area 01a, and the peripheral area 1c corresponds to the third area 01c.

[0139] Finally, refer to Fig.10 and Fig.11 As shown, the above step S105 is performed to form a second peripheral circuit 31 on the third semiconductor layer 03, and the second peripheral circuit 31 is arranged on the side of the stack structure 11 away from the second semiconductor layer 02 in the second direction x, and the second peripheral circuit 31 is connected to the second contact end 12b of the gate contact portion 12.

[0140] In some embodiments, reference Fig.10 As shown, the second peripheral circuit 31 includes a second string driving circuit 311, and the second string driving circuit 311 is used to connect to the second contact terminal 12b of the gate contact portion 12 to drive the gate layer 111. The second string driving circuit 311 includes at least one high-voltage transistor.

[0141] In some embodiments, the second peripheral circuit 31 further includes a second page buffer circuit 312, which is used to connect to the second channel connection terminal 16b of the channel structure 16 to drive the channel structure 16. The second page buffer circuit 312 includes at least one of a high voltage transistor and a low voltage transistor.

[0142] In the related art, multiple wires are connected to the same end of the gate contact portion, and there is a problem that multiple wires are densely arranged, and there is a problem that the arrangement of multiple wires is difficult. In some embodiments of the present application, since the first string drive circuit 211 is connected to the first contact end 12a of the gate contact portion 12, and the second string drive circuit 311 is connected to the second contact end 12b of the gate contact portion 12, the bidirectional lead-out of the gate contact portion 12 is achieved, and the density of the wires connecting the gate contact portion 12 and the peripheral circuit is reduced, which is conducive to improving the wiring design of the semiconductor device and improving the performance of the semiconductor device.

[0143] In some embodiments of the present application, since the first page buffer circuit 212 is used to connect to the first channel connection terminal 16a of the channel structure 16, and the second page buffer circuit 312 is used to connect to the second channel connection terminal 16b of the channel structure 16, bidirectional lead-out of the channel structure 16 is also achieved, which reduces the density of the wires connecting the channel structure 16 and the peripheral circuits, which is beneficial to improving the wiring design of the semiconductor device and improving the performance of the semiconductor device.

[0144] In some embodiments, reference Fig.10 As shown, the method further includes: forming a connection contact 33 on the third semiconductor layer 03 , the connection contact 33 extending into the third semiconductor layer 03 along the second direction z, and the connection contact 33 and the second peripheral circuit 31 are spaced apart.

[0145] In some embodiments, the connection pad 33 includes a first connection pad 331 and a second connection pad 332. The first connection pad 331 is connected to the second peripheral circuit 31. The second connection pad 332 is used to connect to the first through-array connection pad 181.

[0146] In some embodiments, the material of the first connection pad 331 and the second connection pad 332 includes metal, and the metal includes but is not limited to tungsten, cobalt, copper, nickel, and combinations thereof.

[0147] In some embodiments, reference Fig.10 As shown, the method further includes: forming a second bonding contact 321 connected to the second peripheral circuit 31 on a side of the second peripheral circuit 31 away from the third semiconductor layer 03 in the second direction z.

[0148] In some embodiments, a second bonding layer 32 is formed on a side of the second peripheral circuit 31 away from the third semiconductor layer 03 in the second direction z, and the second bonding layer 32 includes a plurality of second bonding contacts 321, which are respectively connected to the first connection contacts 331, the second connection contacts 332 and the second peripheral circuit 31.

[0149] In some embodiments of the present application, the above method is used to prepare Fig.10A third initial semiconductor structure 3 ′ is shown.

[0150] In some embodiments, reference Fig.11 As shown, in the second direction x, the second peripheral circuit 31 is arranged on the side of the stacked structure 11 away from the second semiconductor layer 02, including: turning over the third initial semiconductor structure 3' and then placing it on Fig. 9 The first semiconductor structure 1 is shown to be located away from a side of the second semiconductor structure 2 , and the third semiconductor layer 03 is located on a side of the first semiconductor structure 1 away from the second semiconductor structure 2 .

[0151] In some embodiments, after placing the third initial semiconductor structure 3 ′ on the first semiconductor structure 1 , the method includes: bonding the second bonding contact 321 to the first bonding contact 1511 to connect the second peripheral circuit 31 and the second contact end 12 b of the gate contact 12 .

[0152] In some embodiments, connecting the second peripheral circuit 31 and the second contact terminal 12 b of the gate contact portion 12 includes: connecting the second contact terminal 12 b of another gate contact portion 12 of two adjacent gate contacts 12 to the second peripheral circuit 31 .

[0153] Exemplarily, when the first contact terminal 12a of the gate contact portion 12 connected to the first gate layer 1111 is connected to the first peripheral circuit 21 via the third wire 143, etc., the second contact terminal 12b of the gate contact portion 12 connected to the third gate layer 1113 is connected to the second peripheral circuit 31 via the first wire 141.

[0154] In some embodiments, connecting the second peripheral circuit 31 and the second contact terminal 12 b of the gate contact portion 12 further includes: connecting the second contact terminals 12 b of at least two gate contacts 12 respectively connected to at least two gate layers 111 arranged in the same layer to the second peripheral circuit 31 .

[0155] Exemplarily, the second contact ends 12 b of the two gate contacts 12 of the third gate layer 1113 and the fourth gate layer 1114 disposed on the same layer are connected to the second peripheral circuit 31 through the first wire 141 .

[0156] In some embodiments of the present application, since the second bonding contact 321 is bonded to the first bonding contact 1511, the second peripheral circuit 31 is connected to the first peripheral circuit 21 through the second through-array connection contact 182 and the fifth wire 145, etc., and the second connection contact 332 is connected to the first peripheral circuit 21 through the first through-array connection contact 181 and the fourth wire 144, etc. Moreover, the second page buffer circuit 312 is connected to the second channel connection terminal 16b of the channel structure 16 through the second wire 142 and the common source 17, etc., and the second string driving circuit 311 is connected to the second contact terminal 12b of the gate contact portion 12 through the first wire 141, etc.

[0157] In some embodiments, after connecting the third initial semiconductor structure 3 ′ and the first semiconductor structure 1 , the method further includes: forming a pad portion 4 on a side of the third semiconductor layer 03 away from the second peripheral circuit 31 , so that the first through array connection contact 181 connects the pad portion 4 and the first peripheral circuit 21 .

[0158] In some embodiments, before forming the pad portion 4 on the side of the third semiconductor layer 03 away from the second peripheral circuit 31 , the surface of the third semiconductor layer 03 away from the second peripheral circuit 31 is thinned to expose the connection pad 33 .

[0159] In some embodiments, forming the pad portion 4 on a side of the third semiconductor layer 03 away from the second peripheral circuit 31 includes: forming the pad portion 4 on a side of the thinned third semiconductor layer 03 away from the second peripheral circuit 31 , the pad portion 4 being connected to the connection contact 33 .

[0160] In some embodiments, the pad portion 4 includes a first pad portion 41 and a second pad portion 42. The first pad portion 41 is connected to the first connection contact 331, so that the first pad portion 41 is connected to the second peripheral circuit 31, which facilitates signal transmission between the second peripheral circuit 31 and the external circuit through the first pad portion 41. The second pad portion 42 is connected to the second connection contact 332, so that the second pad portion 42 is connected to the first peripheral circuit 21 through the second connection contact 332 and the first through-array connection contact 181, which facilitates signal transmission between the first peripheral circuit 21 and the external circuit through the second pad portion 42.

[0161] In some other embodiments, the method further includes: forming a pad portion 4 on a side of the second semiconductor layer 02 away from the first peripheral circuit 21 , and connecting the pad portion 4 and the second peripheral circuit 31 via the first through array connection contact 181 .

[0162] In some embodiments of the present application, the third initial semiconductor structure 3' is processed by the above method to obtain Fig.11 A third semiconductor structure 3 is shown.

[0163] In some embodiments of the present application, in the first initial semiconductor structure 1', the gate contact 12 passes through the stacked structure 11, the gate contact 12 has a first contact end 12a and a second contact end 12b opposite to each other, and the gate contact 12 can be led out in both directions. On the basis that the gate contact 12 can be led out in both directions, the first initial semiconductor structure 1' is connected to the second semiconductor structure 2, and the second semiconductor structure 2 is connected to the first contact ends 12a of some gate contacts 12. Next, the first initial semiconductor structure 1' is processed to obtain the first semiconductor structure 1, the third initial semiconductor structure 3' is connected to the side of the first semiconductor structure 1 away from the second semiconductor structure 2, and the third initial semiconductor structure 3' is connected to the second contact ends 12b of other gate contacts 12, and the third initial semiconductor structure 3' is processed to obtain Fig.11 A semiconductor device 100 is shown.

[0164] In other embodiments, referring to Fig.12 As shown, after the step S101 and before the step S102 , the method further includes: pre-burying a common source layer 17 a in the first semiconductor layer 01 .

[0165] In some other embodiments, the material of the common source layer 17a is different from the material of the first semiconductor layer 01. The material of the common source layer 17a includes but is not limited to metal or polysilicon. Specifically, the material of the common source layer 17a includes polysilicon.

[0166] In other embodiments, referring to Fig.12 As shown, in the above step S103, forming a plurality of gate contacts 12 in the first region 01a includes: forming a plurality of gate contacts 12 extending into the common source layer 17a, wherein the second contact ends 12b of the plurality of gate contacts 12 extend into the common source layer 17a.

[0167] In other embodiments, referring to Fig.12 and Fig.13 As shown, before replacing the multiple sacrificial layers 112 with multiple gate layers 111, the above method also includes: forming a plurality of channel structures 16 in the second region 01b that penetrate the stacked layer 11a along the second direction z, the multiple channel structures 16 include a first channel connection end 16a and a second channel connection end 16b located on opposite sides of the stacked layer 11a in the second direction z, and the second channel connection end 16b of the channel structure 16 extends into the common source layer 17a and contacts the common source layer 17a.

[0168] It should be noted that Fig.12 The semiconductor structure shown is Figure 2 The semiconductor structures shown are basically similar, except that Fig.12The first semiconductor layer 01 is pre-buried with a common source layer 17a, and the common source layer 17a is located in the first region 01a, the second region 01b and the third region 01c. Fig.12 After the sacrificial layer 112 of the semiconductor structure is replaced by the gate layer 111, the Fig.13 A first initial semiconductor structure 1 ′ is shown.

[0169] In other embodiments, referring to Fig.14 As shown, connect Fig.13 The first initial semiconductor structure 1' is shown Figure 4 The second semiconductor structure 2 is shown.

[0170] In other embodiments, referring to Fig.15 As shown, connect Fig.13 The first initial semiconductor structure 1' is shown Figure 4 After forming the second semiconductor structure 2 , the method further comprises: thinning the surface of the first semiconductor layer 01 away from the stacked structure 11 to expose the common source layer 17 a .

[0171] In other embodiments, referring to Fig.16 As shown, the method further includes: removing the common source layer 17a of the first region 01a to form a common source layer opening and expose the second contact ends 12b of the plurality of gate contacts 12; and

[0172] An isolation layer 13 is formed in the common source layer opening, and the second contact ends 12 b of the plurality of gate contacts 12 all extend into the isolation layer 13 .

[0173] In other embodiments, referring to Fig.16 As shown, the method further includes: removing the common source layer 17a of the first region 01a while removing the common source layer 17a of the third region 01c, exposing the first conductive connection portion 1811 of the first through-array connection contact 181 and exposing the second conductive connection portion 1821 of the second through-array connection contact 182.

[0174] In other embodiments, referring to Fig.16 As shown, the method further includes: while removing the common source layer 17a of the first region, retaining the common source layer 17a of the second region 01b to form a common source 17, the second channel connection end 16b of the channel structure 16 extends into the common source 17 and contacts the common source 17.

[0175] In other embodiments of the present application, a common source layer 17a is pre-buried in the first semiconductor layer 01, a portion of the common source layer 17a is removed to form a common source 17, and the second channel connection end 16b of the channel structure 16 is extended into the common source 17 and in contact with the common source 17, so as to improve the problem of damage to the channel structure 16 caused by etching away the functional layer outside the second channel connection end 16b and then forming the common source 17.

[0176] The following combination Fig.11 A semiconductor device 100 according to some embodiments of the present application is described.

[0177] The semiconductor device 100 includes a first semiconductor structure 1, a second semiconductor structure 2, and a third semiconductor structure 3. In a second direction z, the second semiconductor structure 2 is located on one side of the first semiconductor structure 1 in the second direction z, the third semiconductor structure 3 is located on a side of the first semiconductor structure 1 away from the second semiconductor structure 2, and the first semiconductor structure 1 is connected to the third semiconductor structure 3 and the second semiconductor structure 2, respectively.

[0178] The first semiconductor structure 1 includes a storage region 1a and a step region 1b adjacent to each other along a first direction x. The first semiconductor structure 1 also includes a peripheral region 1c spaced apart from the step region 1b in the first direction x, and the peripheral region 1c is disposed around the storage region 1a.

[0179] The first semiconductor structure 1 includes a stacked structure 11 stacked along a second direction z, and the stacked structure 11 includes a plurality of gate layers 111 and a plurality of gate dielectric layers 113 alternately arranged along the second direction z. The plurality of gate layers 111 are arranged at intervals in the second direction z, and a plurality of step surfaces 111a are formed in the step region 1b, respectively. The second direction z intersects with the first direction x.

[0180] Exemplarily, the second direction z is perpendicular to the first direction x, but is not limited thereto.

[0181] The first semiconductor structure 1 further includes a plurality of gate contacts 12 located in the step region 1b, the plurality of gate contacts 12 penetrate the plurality of step surfaces 111a and are respectively connected to the plurality of gate layers 111. The gate contact 12 includes a first contact end 12a and a second contact end 12b located at opposite sides of the stack structure 11 in the second direction z. In other words, the gate contact 12 penetrates the stack structure 11 in the step region 1b.

[0182] In the related art, the gate contact portion is only in contact with the step surface, and it is difficult to realize bidirectional extraction of the gate contact portion. In some embodiments of the present application, the gate contact portion 12 penetrates the stacking structure 11 of the step area 1b, and the peripheral circuit can be connected to the first contact end 12a and the second contact end 12b of the gate contact portion 12, that is, the gate contact portion 12 can be extracted in both directions.

[0183] In some embodiments, the gate contact portion 12 includes a penetration portion 121 and a contact portion 122, both of which extend along the second direction z, and the penetration portion 121 is connected to the contact portion 122. The penetration portion 121 penetrates the stacked structure 11 of the step area 1b, and one end of the penetration portion 121 away from the contact portion 122 is a second contact end 12b. One end of the contact portion 122 away from the penetration portion 121 is a first contact end 12a, and one end of the contact portion 122 close to the penetration portion 121 is also in contact with the step surface 111a of the gate layer 111, so that the gate contact portion 12 is connected to the gate layer 111.

[0184] In some embodiments, the dimension of the through portion 121 along the first direction x is smaller than the dimension of the contact portion 122 along the first direction x, so that the contact portion 122 contacts the step surface 111 a of the gate layer 111 to achieve connection between the gate contact portion 12 and the gate layer 111 .

[0185] In some embodiments, the gate contact portion 12 further includes a gate contact insulating portion 123, and the gate contact insulating portion 123 covers the through portion 121 and the sidewall of the contact portion 122 extending along the second direction z. With this design, on the one hand, an insulating layer is provided between the through portion 121 and the gate layer 111 through which it penetrates, and on the other hand, one end of the contact portion 122 connected to the through portion 121 can contact the corresponding gate layer 111, thereby achieving connection between the gate contact portion 12 and the corresponding gate layer 111.

[0186] The second semiconductor structure 2 is arranged near the first contact end 12a and includes a first peripheral circuit 21, which is connected to the first contact end 12a of the gate contact portion 12. The third semiconductor structure 3 includes a second peripheral circuit 31, which is connected to the second contact end 12b of the gate contact portion 12. Through this design, the bidirectional lead-out of the gate contact portion 12 is achieved, and the wiring concentration of the wires connecting the gate contact portion 12 with the first peripheral circuit 21 and the second peripheral circuit 31 is reduced, thereby simplifying the wiring in the semiconductor device 100. Moreover, while the first peripheral circuit 21 and the second peripheral circuit 31 are respectively connected to the opposite sides of the first semiconductor structure 1, it is beneficial to expand the process window of the first peripheral circuit 21 and the second peripheral circuit 31, thereby reducing the difficulty of the process manufacturing of the first peripheral circuit 21 and the second peripheral circuit 31.

[0187] In some embodiments, among two adjacent gate contacts 12, the first contact end 12a of one gate contact 12 is connected to the first peripheral circuit 21, and the second contact end 12b of the other gate contact 12 is connected to the second peripheral circuit 31. With this design, the two adjacent gate contacts 12 are respectively led out from different contact ends, the concentration of the wiring connecting the first contact end 12a of the gate contact 12 and the first peripheral circuit 21 is low, and the concentration of the wiring connecting the second contact end 12b of the gate contact 12 and the second peripheral circuit 31 is also low, which further simplifies the wiring of the semiconductor device 100.

[0188] In some embodiments, the first contact ends 12a of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed on the same layer are connected to the first peripheral circuit 21, and / or the second contact ends 12b of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed on the same layer are connected to the second peripheral circuit 31. This design is conducive to reducing the number of wires connecting the first contact ends 12a of the gate contacts 12 and the first peripheral circuit 21, and reducing the number of wires connecting the second contact ends 12b of the gate contacts 12 and the second peripheral circuit 31, further simplifying the wiring of the semiconductor device 100.

[0189] Specifically, the first contact ends 12a of at least two gate contact portions 12 respectively connected to at least two gate layers 111 arranged on the same layer are connected to the first peripheral circuit 21, and the second contact ends 12b of at least two gate contact portions 12 respectively connected to at least two gate layers 111 arranged on the same layer are connected to the second peripheral circuit 31.

[0190] In some embodiments, the first semiconductor structure 1 further includes an isolation layer 13, and the isolation layer 13 is located in the step region 1b and the peripheral region 1c. The isolation layer 13 is located between the stacked structure 11 and the third semiconductor structure 3. The second contact ends 12b of the plurality of gate contacts 12 all extend into the isolation layer 13, so that the plurality of gate contacts 12 are insulated from each other.

[0191] In some embodiments, the first semiconductor structure 1 further includes a first conductive line 141 . The first conductive line 141 is located on a side of the isolation layer 13 away from the stacked structure 11 and is connected to the second contact end 12 b of the gate contact 12 .

[0192] In some embodiments, one first conductive line 141 is connected to the second contact ends 12 b of at least two gate contacts 12 , so as to reduce the number of required first conductive lines 141 and further simplify the wiring of the semiconductor device 100 .

[0193] In some embodiments, the first semiconductor structure 1 further includes a third conductive line 143 . The third conductive line 143 is located on a side of the stacked structure 11 close to the second semiconductor structure 2 and is connected to the first contact end 12 a of the gate contact 12 .

[0194] In some embodiments, one third wire 143 is connected to the first contact ends 12 a of at least two gate contacts 12 , so as to reduce the number of required third wires 143 and further simplify the wiring of the semiconductor device 100 .

[0195] In some embodiments of the present application, the first contact end 12 a and the second contact end 12 b of the plurality of gate contacts 12 are respectively connected to the third wire 143 and the first wire 141 to achieve bidirectional extraction of the plurality of gate contacts 12 .

[0196] The first semiconductor structure 1 further includes a plurality of channel structures 16 located in the storage area 1a. The plurality of channel structures 16 penetrate the stacked structure 11 along the second direction z, and the channel structure 16 includes a first channel connection end 16a and a second channel connection end 16b located on opposite sides of the stacked structure 11 in the second direction z. The first channel connection end 16a is disposed near the second semiconductor structure 2 and connected to the first peripheral circuit 21, and the second channel connection end 16b is disposed near the third semiconductor structure 3 and connected to the second peripheral circuit 31.

[0197] In some embodiments of the present application, a plurality of channel structures 16 penetrate the stack structure 11 along the second direction z, and the channel structure 16 includes a first channel connection end 16a and a second channel connection end 16b located on opposite sides of the stack structure 11 in the second direction z. With this design, the channel structure 16 can also be led out from the first channel connection end 16a and the second channel connection end 16b, respectively, to connect to a peripheral circuit, further simplifying the wiring of the semiconductor device 100.

[0198] In some embodiments, the channel structure 16 includes a functional layer 162 and a channel layer 161 arranged from outside to inside. The functional layer 162 includes a blocking layer, a charge trapping layer, and a tunneling layer arranged in sequence from outside to inside. The channel layer 161 extends along the second direction z, and its opposite ends in the second direction z include a first channel connection end 16a and a second channel connection end 16b.

[0199] In some embodiments, the first semiconductor structure 1 also includes a common source 17, which is located in the storage area 1a. In the second direction z, the common source 17 is located on the side of the stacking structure 11 away from the second semiconductor structure 2, and the second channel connection ends 16b of the multiple channel structures 16 extend into the common source 17 and contact the common source 17.

[0200] In some embodiments, the first semiconductor structure 1 further includes a second wire 142 . The second wire 142 is located at a side of the common source 17 away from the stack structure 11 and is connected to the common source 17 and the second peripheral circuit 31 .

[0201] In some embodiments, one second conductive line 142 connects at least two common sources 17 , so as to reduce the number of required second conductive lines 142 and further simplify the wiring of the semiconductor device 100 .

[0202] In some embodiments, the third semiconductor structure 3 also includes a first connecting contact 331 and a first pad portion 41 that are interconnected. The first connecting contact 331 extends into the third semiconductor layer 03 along the second direction z and is connected to the second peripheral circuit 31. In the second direction z, the first pad portion 41 is located on a side of the third semiconductor layer 03 away from the second peripheral circuit 31, thereby facilitating signal transmission between the second peripheral circuit 31 and the external circuit through the first pad portion 41.

[0203] In other embodiments, the second semiconductor structure 2 may also include a first connecting contact 331 and a first pad portion 41 that are connected to each other. The first connecting contact 331 extends into the second semiconductor layer 02 along the second direction z and is connected to the first peripheral circuit 21. In the second direction z, the first pad portion 41 is located on a side of the second semiconductor layer 02 away from the first peripheral circuit 21, thereby facilitating signal transmission between the first peripheral circuit 21 and the external circuit through the first pad portion 41.

[0204] In some embodiments, the first semiconductor structure 1 further includes a first through-array connection contact 181 located in the peripheral region 1c and extending along the second direction z, and the first through-array connection contact 181 extends into the isolation layer 13. The third semiconductor structure 3 further includes a second connection contact 332 and a second pad portion 42 connected to each other. The second connection contact 332 extends into the third semiconductor layer 03 along the second direction z, and is spaced apart from the second peripheral circuit 31. In the second direction z, the second pad portion 42 is located on a side of the third semiconductor layer 03 away from the second peripheral circuit 31, and the first pad portion 41 is adjacently disposed. The first through-array connection contact 181 is connected to the second connection contact 332 and the first peripheral circuit 21, so that the first through-array connection contact 181 connects the second pad portion 42 and the first peripheral circuit 21, so as to facilitate the transmission of signals between the first peripheral circuit 21 and the external circuit through the second pad portion 42.

[0205] In other embodiments, the second semiconductor structure 2 may also include a second connecting contact 332 and a second pad portion 42 connected to each other. The second connecting contact 332 extends into the second semiconductor layer 02 along the second direction z, and is spaced apart from the first peripheral circuit 21. The second pad portion 42 is located on a side of the second semiconductor layer 02 away from the first peripheral circuit 21 in the second direction z, and is disposed adjacent to the first pad portion 41. The first through-array connecting contact 181 is connected to the second connecting contact 332 and the second peripheral circuit 31, so that the first through-array connecting contact 181 connects the second pad portion 42 and the second peripheral circuit 31, which facilitates the transmission of signals between the second peripheral circuit 31 and the external circuit through the second pad portion 42.

[0206] In some embodiments, the first semiconductor structure 1 further includes a fourth wire 144 connected between the first through-array connection pad 181 and the second connection pad 332 , and located on a side of the isolation layer 13 away from the stack structure 11 in the second direction z.

[0207] In some embodiments, the first semiconductor structure 1 further includes a second through array connection contact 182 , which extends into the isolation layer 13 along the second direction z and connects the first peripheral circuit 21 and the second peripheral circuit 31 .

[0208] In some embodiments, the second through array connection pads 182 are located in at least one of the peripheral region 1c and the step region 1b. Specifically, the second through array connection pads 182 are located in the peripheral region 1c, and the first through array connection pads 181 are arranged at intervals.

[0209] In some embodiments, the first semiconductor structure 1 further includes a fifth conductive line 145 located on a side of the isolation layer 13 away from the stacked structure 11 in the second direction z, and the fifth conductive line 145 is connected between the second through-array connection contact 182 and the second peripheral circuit 31 .

[0210] In some embodiments, the first semiconductor structure 1 further includes a first bonding layer 151, the first bonding layer 151 is located between the first wire 141 and the third semiconductor structure 3, the first bonding layer 151 includes a plurality of first bonding contacts 1511, and the plurality of first bonding contacts 1511 are respectively connected to the first wire 141, the second wire 142, the fifth wire 145, and the fourth wire 144. The third semiconductor structure 3 further includes a second bonding layer 32, the second bonding layer 32 is located on a side of the second peripheral circuit 31 away from the third semiconductor layer 03, the second bonding layer 32 includes a plurality of second bonding contacts 321, and the plurality of second bonding contacts 321 are respectively connected to the second peripheral circuit 31 and the second connection contact 332. The plurality of second bonding contacts 321 are bonded to the plurality of first bonding contacts 1511 to form a first bonding surface.

[0211] Since the second bonding contacts 321 are bonded to the first bonding contacts 1511 , the fourth wire 144 is connected to the second connection contact 332 , the second connection contact 332 is connected to the first through-array connection contact 181 , and the second peripheral circuit 31 is connected to the first wire 141 , the second wire 142 and the fifth wire 145 .

[0212] In some embodiments, the first semiconductor structure 1 further includes a third bonding layer 152, which is located between the stacked structure 11 and the second semiconductor structure 2 in the second direction z. The third bonding layer 152 includes a plurality of third bonding contacts 1521, which are respectively connected to the third wire 143, the first channel connection end 16a of the channel structure 16, the first through-array connection contact 181, and the second through-array connection contact 182. The second semiconductor structure 2 further includes a fourth bonding layer 22, which is located on a side of the first peripheral circuit 21 away from the second semiconductor layer 02, and includes a plurality of fourth bonding contacts 221, which are connected to the first peripheral circuit 21. The plurality of fourth bonding contacts 221 are respectively bonded to the plurality of third bonding contacts 1521 to form a second bonding surface.

[0213] Since the fourth bonding contacts 221 are respectively bonded to the third bonding contacts 1521 , the third wire 143 , the first channel connection terminal 16 a of the channel structure 16 , the first through array connection contact 181 and the second through array connection contact 182 are all connected to the first peripheral circuit 21 .

[0214] Please refer to Fig.17 and Fig.18 The present application further provides a storage system 400, which includes a memory 200 and a controller 300. The memory 200 includes any of the semiconductor devices 100 of the above embodiments. The controller 300 is connected to the memory 200 and is used to control the memory 200.

[0215] Among them, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0216] In some embodiments, reference Fig.17As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 may be integrated into a three-dimensional memory card.

[0217] Among them, the three-dimensional memory card includes any one of PC card (PCMCIA, Personal Computer Three-Dimensional Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, three-dimensional memory, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0218] In other embodiments, referring to Fig.18 As shown, the storage system 400 includes a plurality of memories 200 and a controller 300. The storage system 400 is integrated into a solid state drive (SSD).

[0219] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0220] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, laptops, and enterprise storage arrays.

[0221] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes for data read from or written to the memory 200.

[0222] Of course, the controller 300 may also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0223] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0224] Please refer to Fig.19 Some embodiments of the present application further provide an electronic device 500. The electronic device 500 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0225] The electronic device 500 may include the above-mentioned storage system 400 and a host 600 , and the host 600 includes at least one of a central processing unit (CPU) and a cache.

[0226] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A first semiconductor structure, wherein the first semiconductor structure comprises a storage area and a step area adjacent to each other along a first direction, and the first semiconductor structure comprises: a stacked structure stacked along a second direction, the stacked structure comprising a plurality of gate layers spaced apart along the second direction, the plurality of gate layers respectively forming a plurality of step surfaces in the step region, the second direction intersecting the first direction; and A plurality of gate contacts, located in the step region, penetrating through the plurality of step surfaces and respectively connected to the plurality of gate layers, the gate contacts comprising a first contact end and a second contact end located at opposite sides of the stack structure in the second direction; a second semiconductor structure located at one side of the first semiconductor structure in the second direction and disposed close to the first contact end, and comprising a first peripheral circuit connected to the first contact end of the gate contact portion; and The third semiconductor structure is located on a side of the first semiconductor structure away from the second semiconductor structure in the second direction and includes a second peripheral circuit connected to the second contact end of the gate contact portion.

2. The semiconductor device according to claim 1, wherein: Among two adjacent gate contact portions, the first contact end of one gate contact portion is connected to a first peripheral circuit, and the second contact end of the other gate contact portion is connected to the second peripheral circuit.

3. The semiconductor device according to claim 1, wherein: The first contact ends of at least two gate contact portions respectively connected to at least two gate layers arranged in the same layer are connected to the first peripheral circuit; and / or, The second contact ends of at least two of the gate contact portions respectively connected to at least two of the gate layers arranged in the same layer are connected to the second peripheral circuit.

4. The semiconductor device according to claim 1, wherein: The first semiconductor structure further comprises: An isolation layer is located between the stacked structure and the third semiconductor structure, and the second contact ends of the plurality of gate contacts all extend into the isolation layer.

5. The semiconductor device according to claim 4, characterized in that The first semiconductor structure further comprises: The first conductive line is located at a side of the isolation layer away from the stack structure and is connected to the second contact end of the gate contact portion.

6. The semiconductor device according to claim 5, characterized in that The first semiconductor structure further comprises: a first bonding contact, located between the first wire and the third semiconductor structure, and connected to the first wire; The third semiconductor structure further includes a second bonding contact connected to the second peripheral circuit, wherein the second bonding contact is bonded to the first bonding contact.

7. The semiconductor device according to claim 1, wherein: The first semiconductor structure further comprises: A plurality of channel structures are located in the storage area and penetrate the stack structure along the second direction, wherein the channel structure includes a first channel connection end and a second channel connection end located on opposite sides of the stack structure in the second direction, wherein the first channel connection end is arranged close to the second semiconductor structure and connected to the first peripheral circuit, and the second channel connection end is arranged close to the third semiconductor structure and connected to the second peripheral circuit.

8. The semiconductor device according to claim 7, characterized in that The first semiconductor structure further comprises: A common source is located in the storage area and on a side of the stack structure away from the second semiconductor structure in the second direction. The second channel connection ends of the plurality of channel structures extend into and contact the common source.

9. The semiconductor device according to claim 8, characterized in that The first semiconductor structure further comprises: The second conductive line is located at a side of the common source away from the stack structure and is connected to the common source and the second peripheral circuit.

10. The semiconductor device according to claim 1, wherein: The first semiconductor structure further includes a peripheral region spaced apart from the step region in the first direction and a first through-array connection contact located in the peripheral region and extending along the second direction; The third semiconductor structure further includes a pad portion, and the first through-array connection contact connects the pad portion and the first peripheral circuit; or, The second semiconductor structure further includes a pad portion, and the first through-array connection contact connects the pad portion and the second peripheral circuit.

11. The semiconductor device according to claim 1, wherein: The first semiconductor structure further comprises: The second through-array connection pad extends along the second direction and connects the first peripheral circuit and the second peripheral circuit.

12. The semiconductor device according to claim 1, wherein: The first semiconductor structure further comprises: a third bonding contact, located between the stacked structure and the second semiconductor structure in the second direction and connected to the first contact end; The second semiconductor structure further includes a fourth bonding contact connected to the first peripheral circuit, wherein the fourth bonding contact is bonded to the third bonding contact.

13. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a first semiconductor layer, wherein the first semiconductor layer has a first region and a second region adjacent to each other along a first direction; Forming a stacking structure stacked along a second direction on the first semiconductor layer, the stacking structure comprising a plurality of gate layers spaced apart along the second direction, the plurality of gate layers respectively forming a plurality of step surfaces in the first region, and the second direction intersecting with the first direction; forming a plurality of gate contacts in the first region, the plurality of gate contacts penetrating the plurality of step surfaces and respectively connected to the plurality of gate layers, the gate contacts comprising a first contact end and a second contact end located at opposite sides of the stack structure in the second direction, the second contact end of the gate contact extending into the first semiconductor layer; forming a first peripheral circuit on the second semiconductor layer, disposing the first peripheral circuit between the second semiconductor layer and the stacked structure in the second direction, and connecting the first peripheral circuit and the first contact end of the gate contact portion; and A second peripheral circuit is formed on the third semiconductor layer, and is disposed on a side of the stack structure away from the second semiconductor layer in the second direction, and is connected to the second contact end of the gate contact portion.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The first contact terminal connecting the first peripheral circuit and the gate contact portion includes: Connecting the first contact end of one of the two adjacent gate contact portions to a first peripheral circuit; The second contact terminal connecting the second peripheral circuit and the gate contact portion includes: Of the two adjacent gate contact portions, the second contact end of the other gate contact portion is connected to the second peripheral circuit.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The first contact terminal connecting the first peripheral circuit and the gate contact portion includes: connecting the first contact ends of at least two gate contacts respectively connected to at least two gate layers arranged in the same layer to the first peripheral circuit; and / or, The second contact terminal connecting the second peripheral circuit and the gate contact portion includes: The second contact ends of at least two of the gate contacts respectively connected to at least two of the gate layers arranged in the same layer are connected to the second peripheral circuit.

16. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The method further comprises: removing the first semiconductor layer in the first region to form a first semiconductor layer opening and expose the second contact ends of the plurality of gate contacts; and An isolation layer is formed in the first semiconductor layer opening, and the second contact ends of the plurality of gate contacts all extend into the isolation layer.

17. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The method further comprises: pre-burying a common source layer in the first semiconductor layer; The forming of a plurality of gate contacts in the first region includes: forming a plurality of gate contacts extending into the common source layer, wherein the second contact ends of the plurality of gate contacts extend into the common source layer.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that: The method further comprises: Thinning a surface of the first semiconductor layer away from the stacked structure to expose the common source layer; removing the common source layer in the first region to form a common source layer opening and expose the second contact ends of the plurality of gate contacts; and An isolation layer is formed in the common source layer opening, and the second contact ends of the plurality of gate contacts all extend into the isolation layer.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that: The stacking structure formed on the first semiconductor layer and stacked along the second direction comprises: forming a stacked layer stacked along a second direction on the first semiconductor layer, the stacked layer comprising a plurality of sacrificial layers and a plurality of gate dielectric layers alternately arranged along the second direction; and Replacing a plurality of sacrificial layers with a plurality of gate layers to obtain the stacked structure; Before replacing the plurality of sacrificial layers with the plurality of gate layers, the method further comprises: forming a plurality of the channel structures penetrating the stacked layer along the second direction in the second region, wherein the plurality of the channel structures include a first channel connection end and a second channel connection end located at opposite sides of the stacked layer in the second direction, and the second channel connection end of the channel structure extends into the common source layer; The method further includes: while removing the common source layer in the first region, retaining the common source layer in the second region, the remaining common source layer constitutes a common source, and the second channel connection end of the channel structure extends into and contacts the common source.

20. The method for manufacturing a semiconductor device according to claim 16 or 18, characterized in that: The method further comprises: A first conductive line is formed on a side of the isolation layer away from the stack structure in the second direction, and the first conductive line is connected to the second contact end of the gate contact portion.

21. The method for manufacturing a semiconductor device according to claim 20, characterized in that: The method further comprises: forming a first bonding contact on a side of the first wire away from the stacking structure in the second direction, the first bonding contact being connected to the first wire; forming a second bonding contact connected to the second peripheral circuit on a side of the second peripheral circuit away from the third semiconductor layer in the second direction; and A second bonding contact is bonded to the first bonding contact.

22. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The stacking structure formed on the first semiconductor layer and stacked along the second direction comprises: forming a stacked layer stacked along a second direction on the first semiconductor layer, the stacked layer comprising a plurality of sacrificial layers and a plurality of gate dielectric layers alternately arranged along the second direction; and Replacing a plurality of sacrificial layers with a plurality of gate layers to obtain the stacked structure; Before replacing the plurality of sacrificial layers with the plurality of gate layers, the method further comprises: forming a plurality of the channel structures penetrating the stacked layer along the second direction in the second region, the plurality of the channel structures comprising a first channel connection end and a second channel connection end located at opposite sides of the stacked layer in the second direction, the second channel connection end of the channel structure extending into the first semiconductor layer; The method further includes: connecting the first channel connection end of the channel structure to the first peripheral circuit; and The second channel connection terminal of the channel structure is connected to the second peripheral circuit.

23. The method for manufacturing a semiconductor device according to claim 22, characterized in that: The method further comprises: Removing the first semiconductor layer in the second region to form a second semiconductor layer opening and expose the second channel connection ends of the plurality of channel structures; A common source is formed in the second semiconductor layer opening, and the second channel connection ends of the plurality of channel structures extend into the common source and contact the common source.

24. The method for manufacturing a semiconductor device according to claim 19 or 23, characterized in that: The method further comprises: A second conductive line is formed on a side of the common source away from the stack structure in the second direction, and the second conductive line is connected to the common source.

25. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The first semiconductor layer further includes a third region located outside the second region and the first region; and the method further includes: forming a first through array connection contact on the first semiconductor layer in the third region, wherein the first through array connection contact extends into the first semiconductor layer along the second direction; forming a pad portion on a side of the third semiconductor layer away from the second peripheral circuit, so that the first through array connection contact connects the pad portion and the first peripheral circuit; or, A pad portion is formed on a side of the second semiconductor layer away from the first peripheral circuit, so that the first through-array connection contact connects the pad portion and the second peripheral circuit.

26. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The method further comprises: forming a second through-array connection contact extending along the second direction on the first semiconductor layer; and The second through-array connection contact connects the first peripheral circuit and the second peripheral circuit.

27. The method for manufacturing a semiconductor device according to claim 13, characterized in that: The method further comprises: forming a third bonding contact, wherein the third bonding contact is located on a side of the stack structure away from the first semiconductor layer in the second direction, and the third bonding contact is connected to the first contact end of the gate contact portion; forming a fourth bonding contact on a side of the first peripheral circuit away from the second semiconductor layer, the fourth bonding contact being connected to the first peripheral circuit; and The third bonding contact and the fourth bonding contact are bonded.

28. A storage system, characterized in that: The storage system comprises: A memory, comprising the semiconductor device according to any one of claims 1 to 12; and The controller is connected to the memory and is used to control the memory.

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