Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The insulating film IF1 is retracted such that a position of an upper surface of the insulating film IF1 is lower than a position of an upper surface of the field plate electrode FP. An embedded insulating film EF1 is formed so as to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is retracted such that the position of the upper surface of the embedded insulating film EF1 is lower than the position of the upper surface of the field plate electrode FP. A gate insulating film GI is formed inside the trench TR, and an insulating film IF2 is formed so as to cover the field plate electrode FP. A gate electrode is formed on the field plate electrode FP via an insulating film IF2.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-112582 filed on Jul. 7, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a gate electrode and a field plate electrode inside a trench and a method for manufacturing the same. Background Art

[0004] In a semiconductor device including a semiconductor element such as a power MOSFET (metal oxide semiconductor field effect transistor), a trench gate structure in which a gate electrode is embedded in a trench is applied. One type of trench gate structure is a split gate structure in which a field plate electrode is formed at the lower portion of the trench and a gate electrode is formed at the upper portion of the trench. A source potential is supplied from a source electrode to the field plate electrode. By expanding the depletion layer in the drift region using the field plate electrode, the concentration of the drift region can be increased, and the resistance of the drift region can be reduced.

[0005] For example, Patent Document 1 discloses a split gate MOSFET. In Patent Document 1, a polysilicon film is formed inside a trench and on a semiconductor substrate, and an anisotropic etching process is performed on the polysilicon film to remove the polysilicon film outside the trench, thereby forming a field plate electrode inside the trench. Thereafter, an insulating film covering the field plate electrode is formed by a thermal oxidation method, and a gate electrode is formed on the insulating film.

[0006] One publicly available technique is listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2011-199109 Summary of the invention

[0008] When forming the field plate electrode, the upper corner of the field plate electrode tends to be processed into a protruding shape. Therefore, the electric field tends to be concentrated on the protruding portion, and leakage current tends to be generated between the gate electrode and the field plate electrode. In addition, even when an insulating film covering the field plate electrode is formed, the thickness of the insulating film may be locally reduced depending on the exposure state of the field plate electrode.

[0009] The main object of the present disclosure is to improve the reliability of a semiconductor device by ensuring a breakdown voltage between a gate electrode and a field plate electrode. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] The following is a brief description of typical embodiments among the embodiments disclosed in the present disclosure.

[0011] A method for manufacturing a semiconductor device according to an embodiment includes: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after (a), forming a groove in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate; (c) after (b), forming a first insulating film inside the groove and on the upper surface of the semiconductor substrate; (d) after (c), forming a field plate electrode on the first insulating film inside the groove; (e) after (d), removing the first insulating film located on the upper surface of the semiconductor substrate and making the first insulating film inside the groove retreat toward the bottom of the groove, so that in a cross-sectional view, the position of the upper surface of the first insulating film located inside the groove is lower than the position of the upper surface of the field plate electrode; (f) After (e), an embedded insulating film is formed on the upper surface of the semiconductor substrate and inside the trench so as to cover the field plate electrode and the first insulating film; (g) after (f), the embedded insulating film located on the upper surface of the semiconductor substrate is removed, and the embedded insulating film inside the trench is retreated toward the bottom of the trench so that in a cross-sectional view, the position of the upper surface of the embedded insulating film inside the trench is lower than the position of the upper surface of the field plate electrode; (h) after (g), a gate insulating film is formed inside the trench on the upper surface of the embedded insulating film by performing a dry oxidation treatment, and a second insulating film is formed to cover the field plate electrode exposed from the embedded insulating film through (g); and (i) after (h), a gate electrode is formed on the field plate electrode via the second insulating film inside the trench.

[0012] A semiconductor device according to one embodiment includes: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a groove formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; a field plate electrode formed inside the groove; a gate electrode formed above the field plate electrode inside the groove; and an insulating film formed inside the groove so as to be located between each of the semiconductor substrate, the field plate electrode and the gate electrode. The corner of the upper portion of the field plate electrode is chamfered or rounded. A portion of the gate electrode is also formed as an embedded portion between the field plate electrode and the semiconductor substrate. The thickness of the insulating film formed between the embedded portion and the field plate electrode is thickest between the deepest portion of the embedded portion and the field plate electrode.

[0013] According to one embodiment, the reliability of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view indicating the semiconductor device in the first embodiment.

[0015] Figure 2is a main portion plan view indicating the semiconductor device in the first embodiment.

[0016] Figure 3 is a main portion plan view indicating the semiconductor device in the first embodiment.

[0017] Figure 4 is a cross-sectional view indicating the semiconductor device in the first embodiment.

[0018] Figure 5 is a main portion sectional view indicating the semiconductor device in the first embodiment.

[0019] Figure 6 is a main portion sectional view indicating the semiconductor device in the first embodiment.

[0020] Figure 7 is a cross-sectional view showing a manufacturing process of the semiconductor device in the first embodiment.

[0021] Figure 8 It is a graphic Figure 7 Cross-sectional view of the subsequent manufacturing process.

[0022] Fig. 9 It is a graphic Figure 8 Cross-sectional view of subsequent fabrication steps.

[0023] Fig.10 It is a graphic Fig. 9 Cross-sectional view of the subsequent manufacturing process.

[0024] Fig.11 It is a graphic Fig.10 Cross-sectional view of subsequent fabrication steps.

[0025] Fig.12 It is a graphic Fig.11 Cross-sectional view of the subsequent manufacturing process.

[0026] Fig.13 It is a graphic Fig.12 Cross-sectional view of the subsequent manufacturing process.

[0027] Fig.14 It is a graphic Fig.13 Cross-sectional view of the subsequent manufacturing process.

[0028] Fig.15 It is a graphic Fig.14 Cross-sectional view of the subsequent manufacturing process.

[0029] Fig.16 It is a graphic Fig.15 Cross-sectional view of subsequent fabrication steps.

[0030] Fig.17 It is a graphic Fig.16 Cross-sectional view of subsequent fabrication steps.

[0031] Fig.18 It is a graphic Fig.17 Cross-sectional view of subsequent fabrication steps.

[0032] Fig.19 It is a graphic Fig.18 Cross-sectional view of subsequent fabrication steps.

[0033] Fig. 20 It is a graphic Fig.19 Cross-sectional view of the subsequent manufacturing process.

[0034] Fig.21 It is a graphic Fig. 20 Cross-sectional view of subsequent fabrication steps.

[0035] Fig. 22 It is a graphic Fig.21 Cross-sectional view of subsequent fabrication steps.

[0036] Fig.23 It is a graphic Fig. 22 Cross-sectional view of subsequent fabrication steps.

[0037] Fig.24 is a main part cross-sectional view showing the semiconductor device in Study Example 1.

[0038] Fig.25 is a main part cross-sectional view showing the semiconductor device in Study Example 1.

[0039] Fig.26 is a main part cross-sectional view showing the semiconductor device in Study Example 2.

[0040] Fig. 27 is a cross-sectional view showing a main portion of the semiconductor device in Study Example 3. DETAILED DESCRIPTION

[0041] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated description is omitted. In the following embodiments, unless particularly necessary, the description of the same or similar parts will not be repeated in principle.

[0042] In addition, the X direction, Y direction, and Z direction described in the present disclosure intersect with each other and are orthogonal to each other. In the present disclosure, the Z direction is described as the vertical direction, height direction, or thickness direction of a specific structure. In addition, the expression "plan view" used in the present disclosure means that the plane formed by the X direction and the Y direction is a "plane", and the "plane" is viewed from the Z direction.

[0043] (First embodiment)

[0044] <Structure of semiconductor device>

[0045] The following will refer to Figures 1 to 6 The semiconductor device 100 in the first embodiment is described. The semiconductor device 100 includes a MOSFET of a trench gate structure as a semiconductor element. The MOSFET of the first embodiment has a split gate structure with a gate electrode GE and a field plate electrode FP.

[0046] The main features of the present disclosure are the shape of the upper portion of the field plate electrode FP, the shape of the embedded insulating film EF1, and the formation method of the insulating film IF2, and after explaining the "Structure of the semiconductor device" and the "Manufacturing method of the semiconductor device", reference will be made to Figure 5 and Figure 6 Describe these features in detail.

[0047] Figure 1 is a plan view of a semiconductor chip serving as the semiconductor device 100 . Figure 2 and Figure 3 yes Figure 1 An enlarged essential portion plan view of region 1A is shown. Figure 3 Shows Figure 2 The lower structure of FIG. 1 mainly shows a trench gate structure formed in a semiconductor substrate SUB. In addition, Figure 2 The positions of the holes CH1, CH2, and CH3 shown in the dashed lines are Figure 3 The positions of the holes CH1, CH2, and CH3 shown in FIG. Figure 4 It is along Figure 2 and Figure 3 A cross-sectional view along line AA and line BB is shown.

[0048] Figure 1 1 shows a wiring pattern mainly formed above a semiconductor substrate SUB. In a plan view, the semiconductor device 100 has a cell region CR and a peripheral region OR surrounding the cell region CR. In the cell region CR, a main semiconductor element such as a plurality of MOSFETs is formed. The peripheral region OR is used to connect the gate wiring GW to the gate electrode GE, and is used as a terminal region, etc.

[0049] like Figure 1 and Figure 2As shown in , most of the cell region CR is covered by the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE. Although not shown here, the source electrode SE and the gate wiring GW are covered with a protective film, such as a polyimide film. An opening is provided in a portion of the protective film, and the source electrode SE and the gate wiring GW exposed in the opening become a source pad SP and a gate pad GP. An external connection member is connected to the source pad SP and the gate pad GP, so that the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring substrate, etc. The external connection member is, for example, a wire made of aluminum, gold, or copper, or a clamp made of a copper plate.

[0050] like Figure 3 As shown in , a plurality of trenches TR are formed in the semiconductor substrate SUB of the unit region CR. The plurality of trenches TR are formed in a stripe shape, extend in the Y direction, and are adjacent to each other in the X direction.

[0051] Also like Figure 4 As shown in the AA cross section of FIG. 1 , inside the trench TR, a field plate electrode FP is formed at a lower portion of the trench TR, and a gate electrode GE is formed at an upper portion of the trench TR. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0052] like Figure 4 As shown in the BB cross section in FIG. 1 , a part of the field plate electrode FP of the cell region CR forms the lead-out portion FPa. The field plate electrode FP constituting the lead-out portion FPa is formed not only in the lower portion of the trench TR but also in the upper portion of the trench TR inside the trench.

[0053] In the cell region CR, a hole CH3 is formed on the lead portion FPa. The lead portion FPa is electrically connected to the source electrode SE via the hole CH3. In the cell region CR, a hole CH1 is formed on the body region PB and the source region NS, which will be described later. The body region PB and the source region NS are electrically connected to the source electrode SE via the hole CH1. In the peripheral region OR, a hole CH2 is formed on the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW via the hole CH2.

[0054] The following will refer to Figure 4 A cross-sectional configuration of the semiconductor device 100 is described.

[0055] like Figure 4As shown in , the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB can be a stack of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate, while phosphorus (P) is introduced by an epitaxial growth method. In this case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0056] The semiconductor substrate SUB has an n-type drain region ND so that a predetermined depth is reached from the lower surface BS of the semiconductor substrate SUB toward the upper surface TS of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. The drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is composed of, for example, a single-layer metal membrane such as an aluminum membrane, a titanium membrane, a nickel membrane, a gold membrane, or a silver membrane, or a laminated membrane in which these metal membranes are laminated accordingly. The drain region ND and the drain electrode DE are formed on the cell region CR and the peripheral region OR. A drain potential is supplied from the drain electrode DE to the semiconductor substrate SUB (drain region ND, drift region NV).

[0057] In the semiconductor substrate SUB, a plurality of trenches TR are formed reaching a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The depth of the trenches TR is, for example, 5 μm (5 micrometers) or more and 7 μm (7 micrometers) or less.

[0058] like Figure 4 As shown in the AA cross section of FIG. 1 , in the trench TR, a field plate electrode FP is formed at a lower portion of the trench TR via the insulating film IF1 and the embedded insulating film EF1 . The position of the upper surface of the insulating film IF1 is lower than that of the upper surface of the field plate FP.

[0059] The embedded insulating film EF1 is formed inside the trench TR on the insulating film IF1. The gate insulating film GI is formed inside the trench TR on the embedded insulating film EF1. The insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the embedded insulating film EF1. The gate electrode GE is formed via the insulating film IF2. Each of the field plate electrode FP and the gate electrode GE is formed, for example, of an n-type doped polysilicon film. The impurity concentration of the polysilicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0060] A portion of the gate electrode GE is also formed in the space between the field plate electrode FP and the semiconductor substrate SUB, and is surrounded by the embedded insulating film EF1, the gate insulating film GI, and the insulating film IF2. Figure 6 As described above, such a portion of the gate electrode GE is referred to as an embedded portion GEa.

[0061] An insulating film IF1 and an embedded insulating film EF1 are formed between the semiconductor substrate SUB and the field plate electrode FP. An insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. A gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. With these films, the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP are electrically insulated from each other.

[0062] In addition, an insulating film IF3 is formed on the gate electrode GE, and the insulating film IF3 is mainly used as a protective film for protecting the cell region CR when another semiconductor element (such as a resistor element) is formed in a region other than the cell region CR. Therefore, if it is not necessary to form other semiconductor devices, it is not necessary to form the insulating film IF3.

[0063] The insulating film IF1, the embedded insulating film EF1, the insulating film IF2, the insulating film IF3 and the gate insulating film GI are made of, for example, a silicon oxide film. The thickness of each of the insulating film IF1 and the embedded insulating film EF1 is greater than the thickness of each of the insulating film IF2 and the gate insulating film GI, and is, for example, greater than or equal to 400nm and less than or equal to 600nm. The thickness of each of the insulating film IF2 and the gate insulating film GI is, for example, not less than 50nm and not more than 70nm. These thicknesses are the thicknesses inside the trench TR and are the thicknesses in the X direction.

[0064] like Figure 5 As shown in , the gate insulating film G1 and the insulating film IF2 are stacked films each including a silicon oxide film OX1 and a silicon oxide film OX2.

[0065] The semiconductor substrate SUB has a p-type body region PB that reaches a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The depth of the body region PB starting from the upper surface TS of the semiconductor substrate SUB is shallower than the trench TR starting from the upper surface TS of the semiconductor substrate SUB. In the body region PB, an n-type source region NS is formed. The source region NS has a higher impurity concentration than the drift region NV.

[0066] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is formed of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less.

[0067] A hole CH1 extending through the interlayer insulating film IL and the source region NS and reaching the body region PB is formed in the interlayer insulating film IL. At the bottom of the hole CH1, a high-concentration diffusion region PR is formed in the body region PB. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. The high-concentration diffusion region PR is mainly provided to reduce the contact resistance with the plug PG and prevent latch-up.

[0068] The source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR via the hole CH1, and supplies a source potential to these impurity regions.

[0069] like Figure 4 As shown in the BB cross section of FIG. 1 , a portion of the field plate electrode FP forms the lead portion FPa of the field plate electrode FP. The position where the respective upper surfaces of the insulating film IF1 and the embedded insulating film EF1 contact the lead portion FPa is higher than the position where the respective upper surfaces of the insulating film IF1 and the embedded insulating film EF1 contact the field plate electrode FP other than the lead portion FPa.

[0070] The insulating film IF2 is formed so as to cover the lead-out portion FPa exposed from the embedded insulating film EF1. The insulating film IF3 is formed on the embedded insulating film EF1, but it is not necessary to form the insulating film IF3 as described above. In addition, a body region PB is formed in the semiconductor substrate SUB adjacent to the lead-out portion FPa, but a source region NS is not formed in this body region PB.

[0071] In the interlayer insulating film IL, a hole CH3 extending through the interlayer insulating film IL, the insulating film IF3 and the insulating film IF2 and reaching the lead-out portion FPa is formed. The source electrode SE is electrically connected to the lead-out portion FPa via the hole CH3 and supplies a source potential to the field plate electrode FP.

[0072] Although not shown here, a hole CH2 extending through the interlayer insulating film IL and the insulating film IF3 and reaching the gate electrode GE is formed in the interlayer insulating film IL. The gate wiring GW is electrically connected to the gate electrode GE via the hole CH2, and supplies a gate potential to the gate electrode GE.

[0073] A plug PG is embedded in each of the holes CH1, CH2, and CH3. The plug PG is formed of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is formed of a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0074] The source electrode SE and the gate wiring GW are formed of, for example, a barrier metal film, such as a titanium tungsten film, and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film, and the conductive film is, for example, an aluminum alloy film to which copper or silicon is added.

[0075] <Method for manufacturing semiconductor device>

[0076] The following will refer to Figures 7 to 23 The respective manufacturing steps included in the manufacturing method of the semiconductor device 100 will be described.

[0077] like Figure 7 As shown in , first, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As described above, the semiconductor substrate SUB may be a stack of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by epitaxial growth.

[0078] Next, a silicon oxide film, for example, is formed on the semiconductor substrate SUB by, for example, CVD (chemical vapor deposition). Next, the silicon oxide film is patterned by photolithography and an anisotropic etching process to form a hard mask HM. Next, an anisotropic etching process using the hard mask HM is performed to form a trench TR in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by, for example, a wet etching process using a solution containing hydrofluoric acid.

[0079] Next, if Figure 8 As shown in FIG. 1 , an insulating film IF1 is formed inside the trench TR and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by thermal oxidation treatment. The thickness of the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB is, for example, 400 nm or more and 600 nm or less. The insulating film IF1 may be a stacked film of a first silicon oxide film formed by thermal oxidation treatment and a second silicon oxide film formed by film formation treatment using a CVD method on the first silicon oxide film.

[0080] Next, a conductive film CF1 is formed on the insulating film IF1 by a film forming process using, for example, a CVD method so as to fill the inside of the trench TR. The conductive film CF1 is, for example, an n-type polysilicon film. The impurity concentration of the polysilicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV). In order to satisfactorily embed the conductive film CF1 in the trench TR, the conductive film CF1 may be formed multiple times, for example, as in the formation of the first polysilicon film and the formation of the second polysilicon film.

[0081] Next, if Fig. 9As shown in , by removing the conductive film CF1 located outside the trench TR, the conductive film CF1 remaining inside the trench TR is formed as the field plate electrode FP.

[0082] Specifically, first, the conductive film CF1 formed outside the trench TR is removed by a polishing process using, for example, CMP (chemical mechanical polishing). Next, an anisotropic etching process using, for example, SF6 gas is performed to retract the position of the upper surface of the conductive film CF1 in the trench TR toward the bottom of the trench TR ( Fig. 9 ). Therefore, the conductive film CF1 remaining in the trench TR is formed as a field plate electrode FP.

[0083] Next, if Fig.10 As shown in , another portion of the field plate electrode FP is selectively removed so that a portion of the field plate electrode FP remains as the lead-out portion FPa.

[0084] Specifically, first, as shown in the BB cross section, a resist pattern RP1 is formed that selectively covers a portion of the field plate electrode FP that becomes the lead-out portion FPa. Next, using the resist pattern RP1 as a mask, an anisotropic etching process using, for example, SF6 gas is performed to remove the other portion of the field plate electrode FP that does not become the lead-out portion FPa. That is, as shown in the BB cross section, Fig.10 As shown in the AA cross section of FIG. 1 , the position of the upper surface of the field plate electrode FP that does not become the lead-out portion FPa is selectively retracted toward the bottom of the trench TR ( Fig.10 ). The unretracted portion of the field plate electrode FP becomes the lead-out portion FPa. Thereafter, the resist pattern RP1 is removed by ashing.

[0085] Next, if Fig.11 As shown in , the insulating film IF1 is isotropically etched to reduce the thickness of the insulating film IF1 and expose the upper portion of the field plate electrode FP from the insulating film IF1. At this time, the upper portion of the lead portion FPa is also exposed from the insulating film IF1. The isotropic etching process is, for example, a wet etching process using a solution containing hydrofluoric acid. The upper portion of the field plate electrode FP and the upper portion of the lead portion FPa are portions including the upper surface of the field plate electrode FP and the upper surface of the lead portion FPa.

[0086] At this time, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and inside the trench TR is not completely removed. Fig. 9 and 10 The upper portion of the field plate electrode FP exposed from the insulating film IF1 and the corner portion CP of each of the lead-out portion FPa are processed into a protruding portion by the anisotropic etching process of FIG.

[0087] Next, if Fig.12As shown in FIG. 1 , an isotropic etching process is performed on the upper portion of each of the field plate electrode FP and the lead portion FPa exposed from the insulating film IF1. The isotropic etching process is a chemical dry etching process using CF4 gas. Thus, the upper corner CP of each of the field plate electrode FP and the lead portion FPa is chamfered or rounded.

[0088] In this isotropic etching process, the thinned insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and inside the trench TR serves as an etching stopper.

[0089] Next, if Fig.13 As shown in , the insulating film IF1 is subjected to an isotropic etching process using a solution containing hydrofluoric acid. As a result, the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB (that is, outside the trench TR) is removed, and the insulating film IF1 located inside the trench TR is retracted toward the bottom of the trench TR, so that the position of the upper surface of the insulating film IF1 located inside the trench TR is further lower than the position of the upper surface of the field plate electrode FP in the cross-sectional view ( Fig.13 ).

[0090] At this time, except for the lead portion FPa, the position where the upper surface of the insulating film IF1 contacts the field plate electrode FP is lower than the position where the upper surface of the insulating film IF1 contacts the lead portion FPa.

[0091] Next, if Fig.14 As shown in FIG. 1 , an embedded insulating film EF1 is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR by using a film forming process such as a CVD method so as to cover the field plate electrode FP and the insulating film IF1. The embedded insulating film EF1 is an insulating film such as a silicon oxide film. The thickness of the embedded insulating film EF1 on the upper surface TS of the semiconductor substrate SUB is, for example, 200 nm or more and 300 nm or less.

[0092] Next, if Fig.15 As shown in , the embedded insulating film EF1 is isotropically etched using a solution containing hydrofluoric acid. As a result, the embedded insulating film EF1 located on the upper surface TS of the semiconductor substrate SUB is removed, and the embedded insulating film EF1 located inside the trench TR is retracted toward the bottom of the trench TR, so that the position of the upper surface of the embedded insulating film EF1 located inside the trench TR is lower than the position of the upper surface of the field plate electrode FP in the cross-sectional view ( Fig.15 ). The isotropic etching process is, for example, a wet etching process using a solution containing hydrofluoric acid.

[0093] Here, the isotropic etching process starts from Fig.14The starting point 10 is located between the field plate electrode FP and the semiconductor substrate SUB (close to the middle). Specifically, the starting point 10 is located between the side of the semiconductor substrate SUB and the field plate electrode FP. Fig.14 The X direction shown in FIG. is adjacent to the field plate electrode FP. Therefore, at the end of the isotropic etching process, as shown in FIG. Fig.15 As shown in , the upper surface of the embedded insulating film EF1 has a curved surface shape which rises as it approaches the side surface of the semiconductor substrate SUB and rises as it approaches the field plate electrode FP.

[0094] Next, if Fig.16 As shown in , the gate insulating film GI is formed inside the trench TR located on the embedded insulating film EF1 , and the insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the embedded insulating film EF1 .

[0095] As reference Figure 5 The gate insulating film G1 and the insulating film IF2 are stacked films including a silicon oxide film OX1 and a silicon oxide film OX2, respectively. These manufacturing steps will be described in detail below.

[0096] First, a silicon oxide film OX1 is formed inside the trench TR on the embedded insulating film EF1, and the silicon oxide film OX1 is formed so as to cover the field plate electrode FP exposed from the embedded insulating film EF1. The silicon oxide film OX1 is formed by a dry oxidation process, which is a thermal oxidation process. That is, it is not a wet oxidation process as a thermal oxidation process. For example, the dry oxidation process is performed using oxygen under the conditions of 1000 degrees Celsius or higher and 1200 degrees Celsius or lower. The thickness of the silicon oxide film OX1 is, for example, 25 nm or more and 35 nm or less.

[0097] Next, a silicon oxide film OX2 is formed on the silicon oxide film OX1 by a film forming process using a CVD method. The silicon oxide film OX2 is a TEOS (tetraethoxysilane) film and has a thickness of, for example, 25 nm or more and 35 nm or less. Thereafter, a heat treatment for densifying the film quality of the silicon oxide film OX2 may be performed. Such heat treatment is performed in a nitrogen atmosphere or an oxygen atmosphere, for example, at a temperature of 900 degrees Celsius or more and 1000 degrees Celsius or less. The silicon oxide film OX2 is also formed on the embedded insulating film EF1.

[0098] The insulating film in contact with the field plate electrode FP and the semiconductor substrate SUB is preferably not the silicon oxide film OX2 but the silicon oxide film OX1. Compared with the silicon oxide film OX2 formed by the film formation process using the CVD method, the silicon oxide film OX1 formed by the dry oxidation process can improve the interface state between the gate insulating film GI and the semiconductor substrate SUB, and improve the interface state between the insulating film IF2 and the field plate electrode FP.

[0099] Next, if Fig.17 As shown in FIG. 1 , a conductive film CF2 is formed on the gate insulating film GI, the insulating film IF2 and the embedded insulating film EF1 by using a film forming process such as a CVD method so as to fill the inside of the trench TR. The conductive film CF2 is, for example, an n-type polysilicon film. The impurity concentration of the polysilicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0100] Next, if Fig.18 As shown in , the conductive film CF2 is polished using a CMP method. Therefore, the thickness of the conductive film CF2 is reduced, and the upper surface of the conductive film CF2 is flattened. Next, an anisotropic etching process is performed on the conductive film CF2 to remove the conductive film CF2 located outside the trench TR. Therefore, the conductive film CF2 left in the trench TR above the field plate electrode FP is formed as the gate electrode GE.

[0101] In order to completely remove the conductive film CF2 outside the trench TR, an anisotropic etching process is performed by over-etching. Fig.18 As shown in the AA cross section of FIG. 1 , the position of the upper surface of the gate electrode GE is lower than the position of the upper surface TS of the semiconductor substrate SUB. In addition, by this anisotropic etching process, the conductive film CF2 formed on the embedded insulating film EF1 and the insulating film IF2 in contact with the lead-out portion FPa is removed.

[0102] Next, if Fig.19 As shown in , by using a film formation process such as a CVD method, the insulating film IF3 is formed on the gate insulating film GI, the gate electrode GE, the insulating film IF2, and the embedded insulating film EF1 so as to cover the trench TR.

[0103] Next, if Fig. 20 As shown in , the insulating film IF3 is subjected to an anisotropic etching process. Therefore, the insulating film IF3 and the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB are removed. As shown in the AA cross section, the insulating film IF3 remains on the gate electrode GE so as to contact the gate insulating film GI. As shown in the BB cross section, the insulating film IF3 remains on the insulating film IF2 and the embedded insulating film EF1 so as to contact the gate insulating film GI.

[0104] Next, if Fig.21 As shown in , a p-type body region PB is selectively formed in the semiconductor substrate SUB by introducing, for example, boron (B) by photolithography and ion implantation. The body region PB is formed so that the depth from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR.

[0105] Next, by introducing, for example, arsenic (As) by photolithography and ion implantation, as shown in the AA cross section, an n-type source region NS is selectively formed in the body region PB of the cell region CR. It should be noted that, as shown in the BB cross section, the source region NS is not formed in the body region PB adjacent to the lead-out portion FPa. Thereafter, the semiconductor substrate SUB is subjected to heat treatment to diffuse the impurities contained in the source region NS and the body region PB.

[0106] Next, if Fig. 22 As shown in , an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR.

[0107] Then, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. Specifically, first, a resist pattern having a pattern for opening the semiconductor substrate SUB in which the source region NS is formed is formed on the interlayer insulating film IL. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a hole CH1 extending through the interlayer insulating film IL and the source region NS and reaching the inside of the body region PB. Next, boron (B), for example, is introduced into the body region PB at the bottom of the hole CH1 by an ion implantation method to form a p-type high-concentration diffusion region PR. Thereafter, the resist pattern is removed by an ashing process.

[0108] Next, on the interlayer insulating film IL, a resist pattern having a pattern opening on the lead-out portion FPa and the gate electrode GE is formed. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a hole CH3 extending through the interlayer insulating film IL, the insulating film IF3, and the insulating film IF2 and reaching the lead-out portion FPa. Although not shown here, in the step of forming the hole CH3, a hole CH2 extending through the interlayer insulating film IL and the insulating film IF3 and reaching the gate electrode GE is also formed. Thereafter, the resist pattern is removed by an ashing process.

[0109] The order of forming the hole CH1 and the order of forming the hole CH2 and the hole CH3 may be interchanged.

[0110] Next, if Fig.23 As shown in , a plug PG is formed inside each of the holes CH1 , CH2 , CH3 , and a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL.

[0111] Specifically, first, a first barrier metal film is formed inside the holes CH1, CH2, CH3 and the interlayer insulating film IL by a film forming process using a sputtering method or a CVD method. The first barrier metal film is formed of, for example, a laminated film of a titanium nitride film and a titanium film. Next, a first conductive film is formed on the first barrier metal film by a film forming process using a CVD method. The first conductive film is formed of, for example, a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the holes CH1, CH2, CH3 are removed by a CMP method or an anisotropic etching process. Thus, a plug PG formed of the first barrier metal film and the first conductive film is formed to fill the inside of the holes CH1, CH2, CH3.

[0112] Next, a second barrier metal film is formed on the interlayer insulating film IL by sputtering. The second barrier metal film is formed of, for example, a titanium tungsten film. Next, a second conductive film is formed on the second barrier metal film by sputtering. The second conductive film is, for example, an aluminum alloy film to which copper or silicon is added. Next, the second barrier metal film and the second conductive film are patterned to form a source electrode SE and a gate wiring GW.

[0113] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. By forming openings in portions of the protective film, regions of the source electrode SE and the gate wiring GW that become the source pad SP and the gate pad GP are exposed.

[0114] Thereafter, the following manufacturing process is used to obtain Figure 4 . First, the lower surface BS of the semiconductor substrate SUB is polished as needed. Next, arsenic (As) or the like is introduced into the lower surface BS of the semiconductor substrate SUB by ion implantation to form an n-type drain region ND. When the semiconductor substrate SUB is composed of a stack of an n-type silicon substrate and an n-type semiconductor layer, the high-concentration n-type silicon substrate forms the drain region ND, and therefore the formation of the drain region ND by the ion implantation described above can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by a sputtering method.

[0115] <Main Features of First Embodiment>

[0116] The following will refer to Figure 5 , Fig.24 , Fig.25 , Fig.26 and Fig. 27 Study Example 1, Study Example 2, Study Example 3 of the first embodiment and semiconductor devices of main features are described. Figure 5 , Fig.24 , Fig.25 , Fig.26 and Fig. 27is a cross-sectional view of the main part, in which the Figure 4 The interior of the groove TR of the AA section.

[0117] like Fig.24 As shown in , in Study Example 1, an insulating film IF1 and a field plate electrode FP are formed inside the trench TR. Fig.25 As shown in FIG. 1 , the insulating film IF1 inside the trench TR is retreated by one isotropic etching process. Here, the isotropic etching process is performed from Fig.24 The process starts from the starting point 11 shown in FIG. Next, a gate insulating film GI and an insulating film IF2 made of a silicon oxide film OX1 are formed by dry oxidation.

[0118] In Study Example 1, unlike the first embodiment, Fig.12 The chemical dry etching process is used. Therefore, the upper corner of the field plate FP remains protruding. Therefore, the electric field tends to concentrate on Fig.25 At the protruding portion 20 shown in FIG. 1 , the insulation resistance between the gate electrode GE and the field plate electrode FP deteriorates, and a leakage current tends to be generated.

[0119] On the other hand, in the first embodiment, the Fig.12 Chemical dry etching process. Figure 5 As shown in , the upper corner of the field plate electrode FP is chamfered or rounded. Therefore, the portion where the electric field concentration occurs between the gate electrode GE and the field plate electrode FP becomes uniform. That is, since the concentration of the electric field is alleviated, the occurrence of leakage current is suppressed. Therefore, the reliability of the semiconductor device 100 can be improved.

[0120] In addition, in Study Example 1, the isotropic etching process is Fig.24 The starting point 11 shown in FIG. Fig.25 As shown in , the position of the portion of the upper surface of the insulating film IF1 that is located inside the trench TR and in contact with the field plate electrode FP is retracted below the position of the portion that is in contact with the side of the semiconductor substrate SUB. That is, the position of the portion that is in contact with the field plate FP is retracted toward the bottom of the trench TR. When the insulating film IF2 is formed by performing a dry oxidation treatment under this condition, oxygen is difficult to reach, and the thickness of the insulating film IF2 near the insulating film IF1 tends to be locally thinned. Therefore, it is difficult to ensure the insulation resistance between the gate electrode GE and the field plate electrode FP. Fig.25 In FIG. 4 , such a location is shown as film location 30 .

[0121] In Study Example 2, in order to ensure the thickness of the thin film portion 30, as Fig.26As shown in , a silicon oxide film OX3 treated by wet oxidation is applied. The wet oxidation treatment is, for example, a thermal oxidation treatment performed using water vapor under the conditions of 850 degrees Celsius or higher and 950 degrees Celsius or lower.

[0122] Since the impurity concentration of the polysilicon film constituting the field plate electrode FP is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV), the thickness of the insulating film IF2 is more likely to be formed thicker than the thickness of the gate insulating film GI due to the influence of accelerated oxidation when the wet oxidation process is performed. In addition, it is easy to ensure the thickness of the insulating film IF2 even near the insulating film IF1.

[0123] On the other hand, in the wet oxidation process, the roughness of the oxidized surface of the field plate electrode FP tends to be rough. Therefore, a portion where the thickness of the insulating film IF2 is locally thinned may appear, and the concentration of the electric field may appear at this portion. In addition, it is also difficult to reduce the concentration of the electric field at the protruding portion of the field plate electrode FP.

[0124] On the other hand, in the dry oxidation process, the effect of accelerating oxidation is smaller than that of the wet oxidation process, but the roughness of the oxidized surface of the field plate electrode FP is improved. Therefore, a means is required to ensure the insulation resistance at the thin film portion 30 even when the dry oxidation process is applied.

[0125] Therefore, in the first embodiment, Fig.14 The embedded insulating film EF1 is formed in Fig.15 The embedded insulating film EF1 is made to retreat by an isotropic etching process. As a result, Figure 5 As shown in , the upper surface of the embedded insulating film EF1 has a curved surface shape which rises as it approaches the semiconductor substrate SUB and rises as it approaches the field plate electrode FP.

[0126] Therefore, even if the thickness of the silicon oxide film OX1 formed by the dry oxidation process is thin near the embedded insulating film EF1, the thickness can be compensated by the embedded insulating film EF1. Therefore, the insulation resistance can be ensured at the thin film portion 30, and the reliability of the semiconductor device 100 can be improved.

[0127] In addition, due to the embedded insulating film EF1, the exposed area of ​​the field plate electrode FP is reduced, so the duration of forming the silicon oxide film OX1 having a predetermined thickness can be shortened during the dry oxidation process. Therefore, the manufacturing process can be shortened.

[0128] In the first embodiment, a stacked film of the silicon oxide film OX1 and the silicon oxide film OX2 is applied to the gate insulating film GI and the insulating film IF2, but the silicon oxide film OX2 is provided mainly for adjusting the thickness of the gate insulating film GI and the insulating film IF2. The silicon oxide film OX2 formed by the film forming process using the CVD method is more likely to be formed to have a uniform thickness than the silicon oxide film formed by the wet oxidation process. Therefore, it is impossible to locally generate a portion having a small thickness, and it is easy to suppress the occurrence of electric field concentration.

[0129] It should be noted that since the silicon oxide film OX2 is easily formed to have a uniform thickness, even in Fig.25 In Study Example 1, the silicon oxide film OX2 is formed on the silicon oxide film OX1, and the thin film portion 30 is still a locally thinned portion. Therefore, it is necessary to compensate for the thickness by the embedded insulating film EF1 such as the first embodiment.

[0130] Furthermore, the number of layers of the silicon oxide film stacked on the silicon oxide film OX1 by the film forming process using the CVD method is not limited to one layer of the silicon oxide film OX2 but may be a plurality of layers.

[0131] Incidentally, the embedded insulating film EF1 is preferably formed after a chemical dry etching process is performed on the field plate electrode FP. Fig. 27 As shown in Study Example 3, when the upper corner of the field plate electrode FP is processed into a protruding shape, the aspect ratio is high. Therefore, when the embedded insulating film EF1 is formed by a film forming process of a CVD method, it is possible to generate a gap 40 in the embedded insulating film EF1.

[0132] When such a gap 40 exists, when passing Fig.15 When the embedded insulating film EF1 is retreated by the isotropic etching process, the etchant may penetrate into the gap 40. In this case, the embedded insulating film EF1 may be quickly etched in the gap 40, and the thickness of the embedded insulating film EF1 may become very thin so that almost all of the embedded insulating film EF1 may be removed. In any case, there is a high possibility that the embedded insulating film EF1 having a desired configuration may not be formed.

[0133] If the corner portion CP of the upper portion of the field plate electrode FP is chamfered or rounded as in the first embodiment, the aspect ratio is reduced so that the embedding property of the embedded insulating film EF1 is improved, and generation of the gap 40 can be suppressed.

[0134] Figure 6 is a cross-sectional view of a main part showing that the semiconductor device 100 of the first embodiment does not have Fig.25 The film portion 30 has a portion and the insulation resistance is improved. Figure 6In the figure, the boundaries of the insulating film IF1, the insulating film IF2, the gate insulating film GI, and the embedded insulating film EF1 are not shown. When such insulating films are of the same type (such as silicon oxide films), if integrated in the trench TR, such insulating films are considered to be one integrated insulating film.

[0135] That is, the integrated insulating film IF is formed inside the trench TR so as to be located between each of the semiconductor substrate SUB, the field plate electrode FP and the gate electrode GE. The semiconductor substrate SUB, the field plate electrode FP and the gate electrode GE are electrically insulated from each other by the integrated insulating film IF.

[0136] A part of the gate electrode GE is also formed as an embedded portion GEa between the field plate electrode FP and the semiconductor substrate SUB.

[0137] As described above, one of the main features of the first embodiment is that the upper surface of the embedded insulating film EF1 is curved and rises as it approaches the field plate electrode FP. Therefore, even if the thickness of the insulating film IF2 is small near the embedded insulating film EF1, the thickness can be compensated by the embedded insulating film EF1.

[0138] In other words, Figure 6 As shown in , the thickness T1 of the integrated insulating film IF formed between the embedded portion GEa and the field plate electrode FP is thickest between the deepest portion of the embedded portion GEa and the field plate electrode FP. For example, at a depth near the middle between the highest portion of the field plate electrode FP and the deepest portion of the embedded portion GEa, the thickness T2 of the integrated insulating film IF is smaller than the thickness T1.

[0139] In addition, the upper surface of the embedded insulating film EF1 rises as it approaches the semiconductor substrate SUB side. The thickness T3 of the integrated insulating film IF formed between the embedded portion GEa and the side surface of the semiconductor substrate SUB is thickest between the deepest portion of the embedded portion GEa and the semiconductor substrate SUB. For example, at a depth near the middle between the highest portion of the field plate electrode FP and the deepest portion of the embedded portion GEa, the thickness T4 of the integrated insulating film IF is smaller than the thickness T3.

[0140] Since the integrated insulating film IF is formed in this manner, it is possible to ensure not only the insulation resistance between the semiconductor substrate SUB and the gate electrode GE but also the insulation resistance between the field plate electrode FP and the gate electrode GE.

[0141] Although the present invention has been described in detail based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof.

[0142] For example, in the first embodiment described above, Fig. 9After forming the field plate electrode FP as shown in Fig.13 Before the isotropic etching process is performed on the insulating film IF1 as shown in Fig.12 As shown in FIG, an isotropic etching process is performed on the upper portion of the field plate electrode FP and the lead-out portion FPa exposed from the insulating film IF1, respectively. However, the etching process in FIG. Fig.12 However, in order to more reliably suppress the generation of the gap 40 described above, it is preferable to perform the isotropic etching process on the upper portion of each of the field plate electrode FP and the lead-out portion FPa after forming the field plate electrode FP as in the first embodiment and before performing the isotropic etching process on the insulating film IF1.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate has an upper surface and a lower surface; (b) after (a), forming a trench in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate to the lower surface of the semiconductor substrate; (c) after (b), forming a first insulating film inside the trench and on the upper surface of the semiconductor substrate; (d) after (c), forming a field plate electrode on the first insulating film inside the trench; (e) after (d), removing the first insulating film on the upper surface of the semiconductor substrate, and making the first insulating film inside the trench retreat toward the bottom of the trench, so that in a cross-sectional view, the position of the upper surface of the first insulating film inside the trench is lower than the position of the upper surface of the field plate electrode; (f) after (e), forming an embedded insulating film on the upper surface of the semiconductor substrate and inside the trench so as to cover the field plate electrode and the first insulating film; (g) after (f), removing the embedded insulating film on the upper surface of the semiconductor substrate, and causing the embedded insulating film inside the trench to retreat toward the bottom of the trench, so that in a cross-sectional view, the position of the upper surface of the embedded insulating film inside the trench is lower than the position of the upper surface of the field plate electrode; (h) after (g), forming a gate insulating film inside the trench on the upper surface of the embedded insulating film by performing a dry oxidation process, and forming a second insulating film so as to cover the field plate electrode exposed from the embedded insulating film by (g); as well as (i) After (h), a gate electrode is formed on the field plate electrode via the second insulating film inside the trench.

2. The method for manufacturing a semiconductor device according to claim 1, wherein (f) is performed by a film formation process using a CVD method, and (g) is performed by an isotropic etching process.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the embedded insulating film is a silicon oxide film, and the isotropic etching process in (g) is performed using a solution containing hydrofluoric acid.

4. The method for manufacturing a semiconductor device according to claim 2, wherein after (g), the upper surface of the embedded insulating film has a curved surface shape that rises as it approaches the semiconductor substrate and rises as it approaches the field plate electrode.

5. The method for manufacturing a semiconductor device according to claim 1, wherein (h) comprises: (h1) forming a first silicon oxide film inside the trench on the upper surface of the embedded insulating film by dry oxidation treatment using oxygen gas under the conditions of 1000 degrees Celsius or higher and 1200 degrees Celsius or lower, and (g) forming the first silicon oxide film so as to cover the field plate electrode exposed from the embedded insulating film; as well as (h2) after (h1), forming a second silicon oxide film on the first silicon oxide film by a film forming process using a CVD method, The gate insulating film and the second insulating film each include the first silicon oxide film and the second silicon oxide film.

6. The method for manufacturing a semiconductor device according to claim 1, further comprising: (j) between (d) and (e), reducing the thickness of the first insulating film and exposing an upper portion of the field plate electrode from the first insulating film; as well as (k) Between (j) and (e), an isotropic etching process is performed on the upper portion of the field plate electrode exposed from the first insulating film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein (d) comprises: (d1) forming a first conductive film on the first insulating film so as to fill the inside of the trench; (d2) after (d1), removing the first conductive film formed outside the trench; as well as (d3) After (d2), the position of the upper surface of the first conductive film in the trench is retracted by an anisotropic etching process, thereby forming the first conductive film remaining inside the trench into the field plate electrode.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the field plate electrode is made of a polysilicon film, and the isotropic etching process in (k) is a chemical dry etching process using CF4 gas. 9 . The method for manufacturing a semiconductor device according to claim 8 , wherein an upper corner of the field plate electrode is chamfered or rounded by the chemical dry etching process.

10. The method of manufacturing a semiconductor device according to claim 7, wherein the first insulating film is made of a silicon oxide film, and (j) and (e) are each performed by an isotropic etching process using a solution containing hydrofluoric acid.

11. A semiconductor device comprising: A semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a groove formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; A field plate electrode formed inside the trench; a gate electrode formed above the field plate electrode inside the trench; as well as an insulating film formed inside the trench so as to be located between each of the semiconductor substrate, the field plate electrode, and the gate electrode, wherein the corners of the upper portion of the field plate electrode are chamfered or rounded, wherein a portion of the gate electrode is also formed as an embedded portion between the field plate electrode and the semiconductor substrate, and The thickness of the insulating film formed between the embedded portion and the field plate electrode is thickest between a deepest portion of the embedded portion and the field plate electrode. 12 . The semiconductor device according to claim 11 , wherein a thickness of the insulating film formed between the embedded portion and the semiconductor substrate is thickest between a deepest portion of the embedded portion and the semiconductor substrate.

13. The semiconductor device according to claim 12, wherein said insulating film is a silicon oxide film.

14. The semiconductor device according to claim 12, further comprising: a body region of a second conductivity type, formed in the semiconductor substrate so that a depth from the upper surface of the semiconductor substrate is shallower than a depth of the trench, the second conductivity type being opposite to the first conductivity type; The source region of the first conductivity type is formed in the body region; as well as The drain region of the first conductivity type is formed in the semiconductor substrate so as to reach a predetermined depth from the lower surface of the semiconductor substrate toward the upper surface of the semiconductor substrate, wherein a gate potential is supplied to the gate electrode, wherein a source potential is supplied to the field plate electrode, the body region and the source region, and A drain potential is supplied to the semiconductor substrate and the drain region.

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