Gallium nitride device capable of improving anti-ESD level and preparation method thereof

Abstract

The invention discloses a gallium nitride device capable of improving an anti-ESD level and a preparation method thereof, the gallium nitride device comprises a heterostructure layer epitaxially grown on a substrate, and the heterostructure layer comprises a barrier layer; the insulating layer is formed on the barrier layer, the insulating layer is provided with a patterned opening, the patterned opening comprises an ohmic contact area and a blank area, the ohmic contact area is exposed out of the barrier layer, and the blank area is located between the insulating layer and the ohmic contact area; the non-doped GaN capacitance layer is locally and epitaxially grown on the blank area so as to provide a Schottky contact area; an electrode disposed on the ohmic contact region; and the metal lamination layer is arranged on the GaN capacitor layer to form Schottky contact, and the metal lamination layer is electrically connected with the electrode. According to the invention, the anti-ESD performance of the device can be obviously improved, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor power devices, and in particular to a gallium nitride device with improved ESD resistance level and a preparation method thereof. Background Art

[0002] As a semiconductor power device, GaN (gallium nitride) devices have small equivalent junction capacitance and low withstand voltage level, especially weak ESD (electrostatic discharge) protection between gate and source. Currently, the commonly used ESD protection method is to provide ESD discharge circuits for the gate and source in the external drive circuit of the GaN device, thereby effectively improving the ESD resistance level of the GaN device.

[0003] Static electricity is unpredictable, yet it is everywhere. Electrostatic failure accounts for a high proportion of semiconductor power devices. ESD events may cause damage to semiconductor power devices and cause them to fail or malfunction. If the gate insulating oxide layer of a GAN power device is subjected to ESD stress, it will be slightly damaged, and may even cause the gate leakage current to continue to increase, eventually leading to device gate failure.

[0004] In order to improve the anti-static ESD level between the gate and source of the GAN device and solve the fatal damage of the ESD event to the GAN device, in the related technology, the patent with the invention publication number CN117133803A discloses a GaN HEMT device with a gate structure of an SBD diode and a manufacturing method thereof, which integrates the SBD structure in the conventional enhanced HEMT GAN device structure to enhance the anti-ESD level between the gate and source, and no longer needs to add an additional ESD discharge loop in the external driving circuit to achieve a higher ESD protection level. However, the GAN device structure of this structure is relatively complex, the production cost is high, and the price of the terminal finished product increases. Summary of the invention

[0005] In order to solve the problem that the traditional enhanced HEMT GAN easily reaches the performance limit and the new SBD structure device integrated between GAN devices leads to high cost, the present application provides a gallium nitride device with improved ESD resistance level and a preparation method thereof.

[0006] A first aspect of the present application provides a gallium nitride device with improved ESD resistance level, comprising: A heterostructure layer is epitaxially grown on a substrate, wherein the heterostructure layer comprises a barrier layer; An insulating layer is formed on the barrier layer, the insulating layer has a patterned opening, the patterned opening includes an ohmic contact area and a blank area that expose the barrier layer, and the blank area is located between the insulating layer and the ohmic contact area; An undoped GaN capacitor layer is locally epitaxially grown on the blank area to provide a Schottky contact area; An electrode, disposed on the ohmic contact region; A metal stack is disposed on the GaN capacitor layer to form a Schottky contact, and the metal stack is electrically connected to the electrode.

[0007] By adopting the above technical solution, the gallium nitride device integrates an undoped GaN capacitor layer and a Schottky contact area between the gate and the source, which can significantly improve the device's ESD resistance performance. No additional external ESD discharge circuit is required, which simplifies the circuit design and reduces production costs, while ensuring the reliability of the device under high-temperature working conditions.

[0008] Optionally, a passivation layer is grown on the upper surface of the insulating layer, a P-cap layer is grown on the upper surface of the passivation layer, and a gate is deposited on the upper surface of the P-cap layer. By adopting the above technical solution, the ESD resistance voltage level between the gate and source of the gallium nitride device can be further improved on the basis of ensuring the high-frequency switching characteristics of the device, making the device more stable and reliable when facing electrostatic discharge.

[0009] Optionally, the insulating layer is a SiO2 insulating layer with a thickness of 30nm, the passivation layer is a SiN passivation layer with a thickness of 20nm, and the P cap layer has a thickness of 1.5um. By adopting the above technical solution, the electrical insulation and mechanical stability between the Schottky contact area and the surrounding structure can be effectively improved, thereby significantly enhancing the device's anti-ESD performance and ensuring the good performance of the device's high-frequency switching characteristics.

[0010] Optionally, the heterostructure layer further includes an ALN ​​nucleation layer with a thickness of 20 nm, a GaN buffer layer with a thickness of 4.0 μm, and a GaN channel layer with a thickness of 0.4 μm, which are arranged in sequence from bottom to top, and the barrier layer is arranged on the upper surface of the GaN channel layer and the barrier layer is an ALGaN barrier layer with a thickness of 20 nm. By adopting the above technical solution, the ALN nucleation layer improves the uniformity and quality of epitaxial growth, the GaN buffer layer effectively alleviates the lattice mismatch stress, and the GaN channel layer provides a good electron transmission channel for the device, so that the entire structure has excellent conductivity and stability, thereby significantly improving the device's ESD resistance level.

[0011] Optionally, the electrode includes a source electrode. By adopting the above technical solution and setting the electrode as the source electrode, the structure and performance of the device are further optimized, the effective discharge of ESD stress is ensured, and the reliability of the device is enhanced.

[0012] Optionally, the upper surface of the metal stack is electrically connected to a metal field plate. By adopting the above technical solution, the upper surface of the metal stack is electrically connected to a metal field plate, which can effectively perform electrical connection and signal transmission, further improving the reliability and stability of the device, so that the device can still maintain good performance under high-frequency working conditions, and suppress the trap effect of the barrier layer, thereby improving the ESD protection performance between the gate and the source.

[0013] A second aspect of the present application provides a method for preparing a gallium nitride device with improved ESD resistance, comprising the following steps: epitaxially growing a heterostructure layer on a substrate, wherein the heterostructure layer includes a barrier layer; forming an insulating layer on the barrier layer, wherein the insulating layer has a patterned opening, the patterned opening includes an ohmic contact area and a blank area that expose the barrier layer, and the blank area is located between the insulating layer and the ohmic contact area; Locally epitaxially growing an undoped GaN capacitor layer on the blank area to provide a Schottky contact area; Disposing an electrode on the ohmic contact region; A metal stack is disposed on the GaN capacitor layer to form a Schottky contact, and the metal stack is electrically connected to the electrode.

[0014] By adopting the above technical solution, the preparation method can form a Schottky contact area and an undoped GaN capacitor layer between the gate and source of the GaN device, thereby improving the ESD resistance level of the GaN device, simplifying the device structure, and reducing the production cost. Specifically, the introduction of the undoped GaN capacitor layer enables the device to have a negative threshold voltage, so that it can work like a normally-off HEMT with a positive threshold voltage when the driving electrical signal moves downward, thereby enhancing the ESD protection capability.

[0015] Optionally, after the step of forming an insulating layer on the barrier layer, the method further comprises: Growing a passivation layer on the upper surface of the insulating layer; Growing a P cap layer on the upper surface of the passivation layer; Depositing a gate on the upper surface of the P cap layer; Wherein, the insulating layer is a SiO2 insulating layer with a thickness of 30 nm, the passivation layer is a SiN passivation layer with a thickness of 20 nm, and the P cap layer has a thickness of 1.5 um.

[0016] By adopting the above technical solution, this solution can effectively improve the ESD resistance level of the device while ensuring that the high-frequency switching characteristics of the device are not affected.

[0017] Optionally, after the step of providing a metal stack on the GaN capacitor layer, the method further comprises: A metal field plate is fabricated on the upper surface of the GaN capacitor layer.

[0018] By adopting the above technical solution, the trap effect of the barrier layer is suppressed and the high-frequency switching characteristics of the device are guaranteed.

[0019] Optionally, the heterogeneous structure layer further includes an AlN nucleation layer, a GaN buffer layer and a GaN channel layer, and the step of epitaxially growing the heterogeneous structure layer on the substrate includes: Growing a 20 nm thick ALN nucleation layer on the substrate; Growing a 4.0 um thick GaN buffer layer on the AlN nucleation layer; Growing a 0.4 um thick GaN channel layer on the GaN buffer layer; A 20 nm thick AlGaN barrier layer is grown on the GaN channel layer.

[0020] In summary, the present application includes at least one of the following beneficial technical effects: 1. The GaN device integrates an undoped GaN capacitor layer and a Schottky contact area between the gate and source, which can significantly improve the device's ESD resistance performance. No additional external ESD discharge circuit is required, which simplifies circuit design and reduces production costs, while ensuring the reliability of the device under high-temperature working conditions; 2. This solution optimizes the simple integrated SBD structure. By integrating an additional parasitic capacitor, the driving electrical signal can be shifted downward, so that the normally-on HEMT GAN with a negative threshold voltage can work like a normally-off HEMT with a positive threshold voltage, and the gate-source ESD resistance voltage level can be further improved. 3. This method has a simple design structure and low cost. It can significantly improve the ESD static level between the gate and the source, which is much higher than the traditional normally-off enhanced GAN device. In addition, the capacitor layer is introduced, and it is fully charged only in the initial state. This clamping circuit does not limit the high-frequency switching characteristics of the GAN device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the overall structure of the gallium nitride device of the present application; Figure 2 It is a schematic diagram of growing a heterogeneous structure layer on a substrate corresponding to step S1 in the process of preparing a gallium nitride device of the present application; Figure 3 is a schematic diagram of forming an insulating layer with a patterned opening corresponding to step S2 in the process of preparing a gallium nitride device of the present application; Figure 4 It is a schematic diagram of growing an undoped GaN capacitor layer in a blank area corresponding to step S3 in the process of preparing a gallium nitride device of the present application; Figure 5It is a schematic diagram of setting an electrode in an ohmic contact region corresponding to step S4 in the process of preparing a gallium nitride device of the present application; Figure 6 It is a schematic diagram of providing a metal stack on a GaN capacitor layer corresponding to step S5 in the process of preparing a gallium nitride device of the present application; Figure 7 It is a schematic diagram of growing a P-cap layer on the upper surface of the passivation layer and depositing a gate on the upper surface of the P-cap layer corresponding to steps S6-S8 in the process of preparing a gallium nitride device of the present application; Figure 8 It is a schematic diagram of depositing metal field plates on the upper surface of the source, the upper surface of the metal stack, the upper surface of the gate and the upper surface of the drain respectively corresponding to step S9 in the process of preparing the gallium nitride device of the present application.

[0022] Description of reference numerals: 10. Substrate; 20. Heterostructure layer; 21. ALN nucleation layer; 22. GaN buffer layer; 23. GaN channel layer; 24. Barrier layer; 30. Insulation layer; 40. GaN capacitor layer; 50. Electrode; 51. Source; 52. Drain; 60. Metal stack; 70. Passivation layer; 71. P cap layer; 80. Gate; 90. Metal field plate. DETAILED DESCRIPTION

[0023] The following will be combined with the attached Figures 1 to 8 , the technical solutions in the embodiments of the present invention are clearly and completely described. The described embodiments are only possible technical implementations of the present invention, not all possible implementations. Those skilled in the art can completely combine the embodiments of the present invention to obtain other embodiments without creative work, and these embodiments are also within the scope of protection of the present invention.

[0024] The inventors of the present application have found that GaN power devices are widely used in the field of power electronics due to their high efficiency characteristics, but their ESD protection capabilities are relatively weak, especially between the gate and the source. The traditional ESD protection method is usually to add a discharge circuit to the external drive circuit, but this method increases the complexity of the system. To this end, the present application mainly adopts the following scheme: by introducing a Schottky contact region and a parasitic capacitance layer (GaN-CAP) between the gate and the source of the normally-on GaN HEMT, the effect of significantly improving the ESD protection level between the gate and the source of the GaN HEMT device is achieved, while maintaining a low production cost and a simplified device structure. The following is a further detailed description of the present application.

[0025] Reference Figure 1, the embodiment of the present application provides a gallium nitride device with improved ESD resistance, including a substrate 10, a heterostructure layer 20, an insulating layer 30, an undoped GaN capacitor layer 40, an electrode 50, a metal stack 60, a passivation layer 70, a gate 80 and a metal field plate 90, the metal stack 60 forms a Schottky contact with the undoped GaN capacitor layer 40, forming an overall structure of a Schottky contact area plus GaN-CAP filling, which achieves the effect of significantly improving the ESD protection level between the gate and source of the GaN HEMT device, while maintaining a low production cost and a simplified device structure. Specifically, the substrate 10 uses a Si epitaxial wafer or a SiC epitaxial wafer. In this embodiment, a P-type Si epitaxial wafer is used, which can have a thickness of 200μm and a resistivity of 0.01Ω·cm.

[0026] The heterostructure layer 20 includes an ALN ​​nucleation layer 21, a GaN buffer layer 22, a GaN channel layer 23 and a barrier layer 24 arranged in sequence from bottom to top. Specifically, the thicknesses of the ALN nucleation layer 21, the GaN buffer layer 22, the GaN channel layer 23 and the barrier layer 24 are 20nm, 4.0μm, 0.4μm and 20nm respectively. For example, the ALN nucleation layer 21 is grown in a hydrogen and nitrogen environment using low-temperature growth technology (-470°C) and has a thickness of 20 nanometers. The main purpose of this layer is to buffer the stress generated by the growth of subsequent layers, thereby ensuring the stability of the subsequent layers during the growth period. The GaN buffer layer 22 is carbon-doped and has a thickness of 4.0 microns. The GaN buffer layer 22 is in a state close to insulation, which effectively reduces the dislocation density. A layer of undoped (intrinsic) GaN two-dimensional electron gas (2DEG) with a thickness of 0.4um is formed on the GaN buffer layer 22. This layer of 2DEG will serve as the GaN channel layer 23 of the transistor and present a weak n-type. The barrier layer 24 may be an ALGaN barrier layer with a thickness of 20 nanometers. Preferably, the ALGaN barrier layer is AL 0.25 Ga 0.75 The N barrier layer has a reasonable content ratio, ensuring good conductivity.

[0027] The insulating layer 30 is formed on the barrier layer 24, and the insulating layer 30 has a patterned opening, wherein the patterned opening includes an ohmic contact region and a blank region that expose the barrier layer 24. The ohmic contact region is a region that directly contacts the barrier layer 24, and the region can achieve ohmic contact with the electrode 50. The blank region is located between the insulating layer 30 and the ohmic contact region, and the undoped GaN capacitor layer 40 is partially epitaxially grown on the blank region to provide a Schottky contact region.

[0028] The electrode 50 is disposed on the ohmic contact region, and the electrode 50 forms an ohmic contact with the barrier layer 24. Specifically, the electrode 50 includes a source electrode 51 and a drain electrode 52, and the source electrode 51 is disposed close to the blank region.

[0029] The thickness of the undoped GaN capacitor layer 40 is generally 2 nm, and needs to be precisely controlled during the epitaxial growth process. In addition, a metal stack 60 is disposed on the undoped GaN capacitor layer 40 to form a Schottky contact.

[0030] Optionally, the metal stack 60 is a stack of Ti / Al / Ni / Au or the like. Taking the Ni / Au stack as an example, the specific structure is that the thickness of the Ni layer and the Au layer are 20nm and 80nm respectively. This design enables the Ni layer or the Au layer to form the positive electrode of the Schottky diode, and a reliable Schottky contact can be formed in a high voltage environment. After that, the quality of the Schottky contact oxide layer and the interface layer can be improved by annealing at 400°C in an oxygen environment for 20 minutes. Among them, the passivation layer 70 is grown on the upper surface of the insulating layer 30. Preferably, the insulating layer 30 includes a SiO2 insulating layer with a thickness of 30nm, and the passivation layer 70 includes a SiN passivation layer with a thickness of 20nm. For example, the SiO2 insulating layer can be grown by chemical vapor deposition (CVD) technology, using O2 and SiH4 gases to grow at 400°C. For another example, the passivation layer 70 can be generated by a plasma enhanced CVD (PECVD) method, and the main material is silicon nitride (SiN). The main function of the passivation layer 70 is to isolate the gate 80 from other device parts, avoid electrical interference, and improve the overall performance.

[0031] A P cap layer 71 is formed on the upper surface of the passivation layer 70. Preferably, the P cap layer 71 has a width of 1 um and a thickness of 1.5 um. A gate 80 is deposited on the upper surface of the P cap layer 71. The gate 80 includes one or more metal layers. The material of the gate 80 is usually metal, such as aluminum (Al), titanium (Ti), titanium tungsten (TiW), etc.

[0032] The metal field plate 90 is deposited on the upper surface of the source 51, the upper surface of the metal stack 60, the upper surface of the gate 80, and the upper surface of the drain 52, respectively, to achieve electrical connection between devices. The metal field plate 90 made on the upper surface of the metal stack 60 can suppress the trap effect of the barrier layer 24 and ensure the high-frequency switching characteristics of the device. Specifically, the metal field plate 90 can be made of aluminum alloy material or copper alloy material. For example, when aluminum alloy material is used, the thickness is 1μm; when copper alloy material is used, the thickness is 2μm. By selecting metal field plates 90 of different materials, their conductivity and heat dissipation performance can be adjusted according to the needs of specific application scenarios. Specifically, when depositing the metal field plate 90, a continuous and uniform metal layer is formed in each target area by adopting chemical plating or electroplating technology. For example, when chemical plating is used, a palladium seed layer is first deposited as a catalytic layer, and then a metal material is deposited on the palladium seed layer.

[0033] The implementation principle of this embodiment is: by introducing a Schottky contact region and a GaN-CAP capacitor layer between the gate source of the GaN HEMT device, an enhanced structure for ESD protection is formed. As an isolation layer, the GaN-CAP capacitor layer can significantly increase the absorption capacity of the ESD current; as a discharge path, the Schottky contact region can release the ESD energy in time, thereby jointly improving the effect of ESD protection. Through reasonable material selection and process optimization, not only the ESD protection level is improved, but also a relatively simple manufacturing process and low cost are maintained. Specifically, by precisely controlling the thickness and doping concentration of each layer, the performance indicators of the device can be further improved, so that it can maintain excellent stability in high-frequency switching applications. In addition, through the reasonable layout and design of the metal field plate 90, the overall electrical connection of the device is more reliable, reducing potential failures caused by electric field concentration. In summary, this embodiment effectively improves the performance of GaNHEMT devices in high-demand application fields through innovative structural design and process optimization.

[0034] This embodiment also provides a method for preparing a gallium nitride device with improved ESD resistance level, including the following steps S1 to S9.

[0035] Step S1: Figure 2 As shown, an epitaxially grown heterostructure layer 20 is formed on a substrate 10, and the heterostructure layer 20 includes a barrier layer 24. The heterostructure layer 20 further includes an AlN nucleation layer 21, a GaN buffer layer 22, and a GaN channel layer 23 sequentially arranged from bottom to top, and the barrier layer 24 is arranged on the upper surface of the GaN channel layer 23.

[0036] Step S1 specifically includes the following sub-steps: S11, using P-type silicon material as substrate 10 to reduce costs; S12, using low temperature growth (-470°C) technology to grow a 20 nm thick ALN nucleation layer 21 in a hydrogen and nitrogen environment; S13, growing a 4 μm thick carbon-doped GaN buffer layer 22 on the upper surface of the AlN nucleation layer 21; S14, growing an undoped (intrinsic) GaN two-dimensional electron gas (2DEG) with a thickness of 0.4 um on the upper surface of the GaN buffer layer 22 to form a GaN channel layer 23; S15, growing a 20 nm thick AlGaN barrier layer 24 on the upper surface of the GaN channel layer 23. Preferably, the AlGaN barrier layer 24 is Al 0.25 Ga 0.75 The N barrier layer 24 has a reasonable content ratio, which ensures good conductivity.

[0037] Step S2 is as follows Figure 3As shown, an insulating layer 30 is formed on the barrier layer 24, and the insulating layer 30 has a patterned opening, and the patterned opening includes an ohmic contact area and a blank area that expose the barrier layer 24, and the blank area is located between the insulating layer 30 and the ohmic contact area. Specifically, a SiO2 insulating layer with a thickness of 30nm is grown on the upper surface of the barrier layer 24 by chemical vapor deposition (CVD) technology and using O2 and SiH4 gases at 400°C. After the SiO2 insulating layer covers the upper surface of the barrier layer 24, the insulating layer 30 is patterned to expose the ohmic contact area and the blank area of ​​the barrier layer 24.

[0038] Step S3 is as follows Figure 4 As shown, an undoped GaN capacitor layer 40 is locally epitaxially grown on the blank area to provide a Schottky contact area. Specifically, the undoped GaN capacitor layer 40 is first epitaxially grown in the ohmic contact area and the blank area, and then the undoped GaN capacitor layer 40 in the ohmic contact area is etched away to retain the undoped GaN capacitor layer 40 in the blank area. Preferably, the thickness of the undoped GaN capacitor layer 40 is 2 nm.

[0039] Step S4 is as follows Figure 5 As shown, an electrode 50 is disposed on the ohmic contact region. Specifically, the electrode 50 includes a source electrode 51 and a drain electrode 52. The source electrode 51 and the drain electrode 52 are both disposed on the ohmic contact region, and the source electrode 51 is disposed adjacent to the blank region.

[0040] Step S5 is as follows Figure 6 As shown, a metal stack 60 is arranged on the GaN capacitor layer to form a Schottky contact, and the metal stack 60 is electrically connected to the electrode 50. Optionally, the metal stack 60 is a stack of Ti / Al / Ni / Au or the like. Taking the Ni / Au stack as an example, the specific structure is that the thickness of the Ni layer and the Au layer are 20nm and 80nm respectively. This design enables the Ni layer or the Au layer to form the positive electrode of the Schottky diode, and a reliable Schottky contact can be formed in a high voltage environment. After that, the quality of the Schottky contact oxide layer and the interface layer can be improved by annealing at 400°C in an oxygen environment for 20 minutes. Among them, the steps of S4 and S5 can also be reversed, and the metal stack 60 can be made first, and then the electrode 50 can be made. Preferably, the thickness of the metal stack 60 is not greater than the thickness of the insulating layer 30 so that the metal stack 60 can be formed by a self-alignment process.

[0041] Step S6 is as follows Figure 7 As shown, a passivation layer 70 is grown on the upper surface of the insulating layer 30. Specifically, the passivation layer 70 can be formed by a plasma enhanced CVD (PECVD) method, and the passivation layer 70 is a SiN passivation layer with a thickness of 20 nm.

[0042] Step S7 is as follows Figure 7As shown, a P cap layer 71 is grown on the upper surface of the passivation layer 70. Preferably, the P cap layer 71 has a width of 1 um and a thickness of 1.5 um.

[0043] Step S8 is as follows Figure 7 As shown, the gate electrode 80 is deposited on the upper surface of the P cap layer 71. Specifically, the gate electrode 80 is grown on the P cap layer 71, and the gate electrode 80 is closer to the source electrode 51 than the drain electrode 52.

[0044] Step S9 is as follows Figure 8 As shown, metal field plates 90 are deposited on the upper surface of the source 51, the upper surface of the metal stack 60, the upper surface of the gate 80, and the upper surface of the drain 52. Specifically, the metal field plates 90 are used for electrical connection, and finally the GAN HENMT normally closed novel structure with improved ESD static level in this application is produced. Among them, the metal field plate 90 made on the upper surface of the metal stack 60 can suppress the trap effect of the barrier layer 24 and ensure the high-frequency switching characteristics of the device.

[0045] The implementation principle of this embodiment is: the preparation method adopts a precise process flow to ensure that the GaN device of this embodiment has a reasonable structure and good stability. Through reasonable design and process flow, the gallium nitride device of this embodiment shows good stability in a high voltage environment, optimizes device performance, and reduces manufacturing costs.

[0046] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A gallium nitride device with improved ESD resistance, characterized in that: include: A heterostructure layer (20) epitaxially grown on a substrate (10), wherein the heterostructure layer (20) comprises a barrier layer (24); an insulating layer (30) formed on the barrier layer (24), the insulating layer (30) having a patterned opening, the patterned opening comprising an ohmic contact region and a blank region exposing the barrier layer (24), the blank region being located between the insulating layer (30) and the ohmic contact region; An undoped GaN capacitor layer (40) is locally epitaxially grown on the blank area to provide a Schottky contact area; An electrode (50) is arranged on the ohmic contact area; A metal stack (60) is arranged on the GaN capacitor layer (40) to form a Schottky contact, and the metal stack (60) is electrically connected to the electrode (50).

2. The gallium nitride device with improved ESD resistance level according to claim 1, characterized in that: A passivation layer (70) is grown on the upper surface of the insulating layer (30), a P cap layer (71) is grown on the upper surface of the passivation layer (70), and a gate electrode (80) is deposited on the upper surface of the P cap layer (71).

3. The gallium nitride device with improved ESD resistance level according to claim 2, characterized in that: The insulating layer (30) is a SiO2 insulating layer (30) with a thickness of 30 nm, the passivation layer (70) is a SiN passivation layer (70) with a thickness of 20 nm, and the P cap layer (71) has a thickness of 1.5 um.

4. The gallium nitride device with improved ESD resistance level according to claim 1, characterized in that: The heterogeneous structure layer (20) further comprises an ALN ​​nucleation layer (21) with a thickness of 20 nm, a GaN buffer layer (22) with a thickness of 4.0 μm, and a GaN channel layer (23) with a thickness of 0.4 μm, which are arranged in sequence from bottom to top; the barrier layer (24) is arranged on the upper surface of the GaN channel layer (23) and the barrier layer (24) is an ALGaN barrier layer (24) with a thickness of 20 nm.

5. The gallium nitride device with improved ESD resistance level according to claim 1, characterized in that: The electrode (50) comprises a source electrode (51).

6. The gallium nitride device with improved ESD resistance level according to claim 1, characterized in that: The upper surface of the metal stack (60) is electrically connected to a metal field plate (90).

7. A method for preparing a gallium nitride device with improved ESD resistance, characterized in that: The following steps are involved: Epitaxially growing a heterostructure layer (20) on a substrate (10), wherein the heterostructure layer (20) comprises a barrier layer (24); forming an insulating layer (30) on the barrier layer (24), the insulating layer (30) having a patterned opening, the patterned opening comprising an ohmic contact region and a blank region exposing the barrier layer (24), the blank region being located between the insulating layer (30) and the ohmic contact region; Locally epitaxially growing an undoped GaN capacitor layer (40) on the blank area to provide a Schottky contact area; Disposing an electrode (50) on the ohmic contact region; A metal stack (60) is arranged on the GaN capacitor layer (40) to form a Schottky contact, and the metal stack (60) is electrically connected to the electrode (50).

8. The method for preparing a gallium nitride device with improved ESD resistance according to claim 7, characterized in that: After the step of forming an insulating layer (30) on the barrier layer (24), the method comprises: Growing a passivation layer (70) on the upper surface of the insulating layer (30); Growing a P cap layer (71) on the upper surface of the passivation layer (70); Depositing a gate electrode (80) on the upper surface of the P cap layer (71); The insulating layer (30) is a SiO2 insulating layer (30) with a thickness of 30 nm, the passivation layer (70) is a SiN passivation layer (70) with a thickness of 20 nm, and the P cap layer (71) has a thickness of 1.5 um.

9. The method for preparing a gallium nitride device with improved ESD resistance according to claim 7, characterized in that: After the step of arranging a metal stack (60) on the GaN capacitor layer (40), the method comprises: A metal field plate (90) is manufactured on the upper surface of the GaN capacitor layer (40).

10. The method for preparing a gallium nitride device with improved ESD resistance level according to claim 7, characterized in that: The heterogeneous structure layer (20) further comprises an AlN nucleation layer (21), a GaN buffer layer (22) and a GaN channel layer (23), and the step of epitaxially growing the heterogeneous structure layer (20) on the substrate (10) comprises: Growing a 20 nm thick ALN nucleation layer (21) on the substrate (10); Growing a 4.0 μm thick GaN buffer layer (22) on the AlN nucleation layer (21); Growing a 0.4 um thick GaN channel layer (23) on the GaN buffer layer (22); A 20 nm thick AlGaN barrier layer (24) is grown on the GaN channel layer (23).

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