Method of forming dielectric material-based layer on etch-based III-V material layer

Abstract

The invention relates to a method for forming a layer based on a dielectric material on a layer based on an etching III-V material, the method comprising at least the following steps: providing at least one layer based on a III-V material, preferably III-N, referred to as a III-V layer (100), the III-V layer (100) having a front face (101); etching at least a portion of the III-V layer (100) from the front face (101) to expose a surface of the III-V layer, referred to as an etched surface (103); exposing at least the etched surface (103) to a plasma treatment of O2 or N2, the step being carried out at a temperature Ttreatmentt, where Ttreatmentt; the temperature is 100 DEG C; a layer based on a dielectric material, referred to as a dielectric layer (200), is deposited at least on the etched surface.

Description

Technical Field

[0001] The present invention relates to forming a layer based on a dielectric material on a layer based on an etched III-V material (e.g. etched GaN). The present invention therefore pertains to the manufacture of devices comprising an interface between a III-N material and a dielectric material. It has particularly advantageous applications in the field of power electronics, such as transistors integrating one or more layers of III-N material. Background Art

[0002] The need to avoid energy waste and the growing demand are driving manufacturers of microelectronic devices to increase the yield and performance of their electrical energy conversion systems. Currently, the conversion circuits are made on the basis of silicon, and a lot of research has been done to develop architectures in order to increase yield and conductivity. However, these known devices have reached the theoretical limits of silicon, so new solutions are being considered. These solutions are based on the use of III-V materials such as GaN. This is the case with high electron mobility transistors (HEMTs).

[0003] Fabricating these types of devices requires performing a number of etching steps in the III-V material, followed by the deposition of a dielectric layer over the etched areas. However, the etching steps severely degrade the chemical and electrical properties of the etched material. As a result, the interface between the III-V material and the dielectric often degrades the electronic properties. For example, plasma etching can cause structural defects that alter the quality of the interface between the etched layer and the dielectric layer. The electrical properties of these interfaces, and therefore the electrical properties of the electronic component, are degraded.

[0004] As is known, existing technologies use etching methods that are inherently less damaging to the quality of the etched layer. Cyclic etching techniques, especially the technique called "atomic layer etching" (ALE), can obtain a minimally damaged etched layer with good electrical properties. However, current ALE techniques are very time-consuming and have a significant impact on productivity. In addition, these techniques are sometimes difficult to implement because they require a generally narrow energy range to selectively and completely remove the layer to be etched.

[0005] Therefore, there is a need to provide a solution to improve the productivity of forming a dielectric layer on an etched III-V material layer without affecting the quality of the formed interface. Summary of the invention

[0006] To achieve this objective, according to one embodiment, a method for forming a layer based on a dielectric material on a layer based on etching a III-V material is provided. The method comprises at least the following steps: - providing at least one layer based on a III-V (preferably III-N) material, referred to as III-V layer, the III-V layer having a front side; - etching at least a portion of the III-V layer from the front side to expose a surface of the III-V layer, called the etched surface; - exposing at least the etched surface to a plasma treatment of O2, N2 or a mixture of O2 and N2 at a temperature T treatment The following is carried out, where T treatment <100°C; - Deposition of a layer based on a dielectric material, called dielectric layer, at least on the etched surface.

[0007] The plasma treatment step implemented in the method according to the invention makes it possible to significantly improve the quality of the III-V material layer (typically etched GaN). In particular, working at low temperatures makes it possible to obtain highly stable etched GaN layers, which makes it possible to facilitate and speed up the processing of samples, improving productivity. The sample does have to be moved from one reactor to another, for example, from the reactor where the plasma treatment is carried out to the reactor where the Al2O3 dielectric layer is deposited. Within the scope of the development of the present invention, it has been noted that with increasing temperature, the stability of the III-N material layer decreases, which poses problems in terms of the robustness of the method. In addition, within the scope of the development of the present invention, it was unexpectedly observed that this reduction in temperature makes the interface quality between the etched III-N material and the dielectric material better than expected. On the contrary, in this case, a person skilled in the art would encourage the application of high temperatures to recrystallize the III-V material located on the surface, because etching changes this surface.

[0008] The improved quality of etching the GaN layer itself leads to a substantial improvement in the quality of etching the GaN / dielectric interface, especially from the perspective of its electrical properties.

[0009] The method according to the invention thus enables a considerable increase in productivity compared to ALE-type solutions, while providing a very satisfactory interface quality.The method according to the invention can, however, also be used together with ALE-type etching.

[0010] It must be noted that the treatment after the step of depositing the non-etched epitaxially grown GaN is not suitable for the treatment of the etched GaN layer, or at least the effect is much worse. In fact, the surface of the non-etched epitaxially grown GaN layer is relatively stable because the layer has usually stayed in the air for a considerable period of time, usually from several hours to several months. The stoichiometry of the epitaxially grown GaN layer is stable, which makes the surface of the layer least reactive, which is completely different from the surface of the etched GaN layer. Therefore, the strategy proposed in the present application of applying plasma treatment to chemically modify the surface of GaN and thereby improve the quality of the interface with the dielectric will have minimal impact on the surface of the epitaxially grown GaN. On the non-etched epitaxially grown surface, the plasma treatment constitutes a cleaning strategy and cannot achieve the structural reconstruction that can be achieved by the method according to the present invention used on the etched GaN layer.

[0011] A method for producing a microelectronic device is also provided, the method comprising forming a dielectric material based layer on an etched III-V material based layer by implementing the above-mentioned forming method, the microelectronic device being selected from a transistor and an LED.

[0012] A method for producing a microelectronic device according to the above production method is also provided, wherein: -The microelectronic device is a transistor; - etching the III-V layer so as to produce trenches in the etched III-V material; - depositing a layer based on a dielectric material on at least a portion of the etched surface of the trench to form a gate dielectric; And comprising the following steps after forming the dielectric layer: - Filling the trench to define at least one gate of the transistor.

[0013] Microelectronic devices are any type of device produced by microelectronic means. In addition to devices with a purely electronic purpose, these devices also include micromechanical or electromechanical devices (MEMS, NEMS, etc.), as well as optical or optoelectronic devices (LED, MOEMS, etc.). This can be a device that is used to ensure electronic, optical, mechanical functions, etc. This can also be an intermediate product that is specifically used to produce another microelectronic device.

[0014] Furthermore, a method for producing a transistor is provided, the method comprising the following steps: - forming a layer based on a dielectric material on the layer based on the etched III-V material by performing the above-mentioned forming method. Etching the III-V layer so as to form a trench in the etched III-V material. Depositing the layer based on the dielectric material on at least a portion of the etched surface of the trench to form a gate dielectric; - Filling the trench to define at least one gate of the transistor.

[0015] Furthermore, a method for producing a transistor is provided, comprising the following steps: - providing at least one layer based on a III-V (preferably III-N) material, referred to as III-V layer, the III-V layer having a front side; - etching at least one trench in the III-V layer from the front side and through a mask to expose a surface of the III-V layer, called the etched surface; - exposing at least the etched surface to an O2 or N2 plasma treatment at a temperature T treatment The following is carried out, where T treatment <100°C; - depositing a layer based on a dielectric material, called dielectric layer, on at least a portion of the etched surface of the trench to form a gate dielectric; - Filling the trench to define at least one gate of the transistor.

[0016] This type of transistor has an improved interface between the III-V layer and the dielectric layer. As a result, this approach improves productivity while enabling transistors to achieve high performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The objects, goals, features and advantages of the present invention will be best understood from the detailed description of the embodiments of the present invention, which are illustrated by the following drawings, in which: Figures 1A to 1G The method steps according to one embodiment of the present invention are shown. Figure 1A The provision of layers based on III-V materials, referred to as III-V layers, is shown.

[0018] Figure 1B Deposition of an optional masking layer over the III-V layer is shown.

[0019] Figure 1C The formation of openings in the mask layer is shown to form an etch mask over the III-V layer.

[0020] Figure 1D The step of etching the III-V layer is shown, thereby enabling renewal of a surface of the III-V layer, referred to as the etched surface.

[0021] Figure 1E The step of exposing the etched surface to a plasma treatment is shown, represented by a set of arrows pointing toward the etched surface.

[0022] Figure 1F Deposition of a dielectric layer on the etched surface is shown.

[0023] Figure 1G Optional mask removal is shown.

[0024] Figure 2A The capacitance-voltage characteristics (CV characteristics or CV curve) of a MOS (Metal Oxide Semiconductor) capacitor manufactured according to a known method in the prior art are shown.

[0025] Figure 2B The CV characteristics of a MOS capacitor manufactured according to an embodiment of the method of the present invention are shown.

[0026] Figure 3 The different steps of an example of a forming method according to the invention are summarized.

[0027] Figure 4 is a graph showing CV characteristics of MOS capacitors produced according to an embodiment of the present invention, one of which is processed at a temperature of 40°C and the other of which is processed at a temperature of 60°C.

[0028] Figure 5A is a graph showing the flat-band voltage values ​​of MOS capacitors produced according to an embodiment of the present invention, one of which is processed at a temperature of 40°C and the other of which is processed at a temperature of 60°C.

[0029] Figure 5B is a graph showing hysteresis values ​​of MOS capacitors produced according to an embodiment of the present invention, one of which is processed at a temperature of 40°C and the other of which is processed at a temperature of 60°C.

[0030] The accompanying drawings are provided as examples and do not limit the present invention. They constitute schematic diagrams of the principles, are intended to facilitate understanding of the present invention, and are not necessarily in proportion to actual applications. In particular, the thickness of each layer does not represent the actual situation. DETAILED DESCRIPTION

[0031] Before starting to describe the embodiments of the present invention in detail, optional features will be described below, which can be used in combination or alternatively: According to one embodiment, the etching step and the plasma treatment step are performed in the same reactor.

[0032] According to an example, T treatment >40°C.

[0033] According to an example, T treatment <80°C.

[0034] According to one example, the plasma treatment step has a duration T treatment , where T treatment <5min, i.e. T treatment <300s, preferably T treatment <2min, i.e. Ttreatment <120s.

[0035] According to one embodiment, the method comprises a wet cleaning step prior to the step of depositing the dielectric layer.

[0036] According to one embodiment, the step of depositing the dielectric layer is performed under vacuum conditions.

[0037] According to one example, the etching step includes chlorine plasma etching.

[0038] According to an example, the etching step comprises at least one ALE type etching cycle.

[0039] According to one example, the etching is performed to etch the III-V material to a thickness greater than 100 nm (10 -9 m), preferably greater than 500 nm, preferably greater than 1 μm (10 -6 m), preferably greater than 3µm.

[0040] According to one example, the plasma treatment step is performed at a zero bias voltage V bias The following is carried out.

[0041] According to one example, the plasma treatment step is performed by injecting a mass flow rate D flow This is carried out at an O2 flow, a N2 flow or a mixed flow of O2 and N2 between 50 sccm and 1000 sccm, preferably between 100 sccm and 500 sccm.

[0042] According to one example, the plasma treatment step is performed by injecting a power source P between 100 W and 4000 W, preferably between 300 W and 1000 W. source This is done by producing an O2 flow, a N2 flow, or a mixture flow of O2 and N2.

[0043] According to an example, the III-V material is one of GaN and AlGaN.

[0044] According to an example, the dielectric material is one of AlN, Al2O3, and HfO2.

[0045] It should be noted that within the scope of the present invention, the terms "on", "over", "covering", "underlying", "opposite" and their equivalents do not necessarily mean "contacting". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but rather means that the first layer at least partially covers the second layer, is either in direct contact with the second layer, or is separated from the second layer by at least one other layer or at least one other element.

[0046] Furthermore, a layer may consist of multiple sub-layers of the same material or of different materials.

[0047] The so-called "based on" material M substrate, layer, device refers to a substrate, layer, device that only includes such material M, or a substrate, layer, device that includes such material M and optional other materials, such as alloying elements, impurities or doping elements. Therefore, a material based on III-N material can include III-N material with dopants added. Similarly, a GaN-based layer typically includes GaN and AlGaN or InGaN alloys.

[0048] The term "III-V material" refers to a semiconductor composed of one or more elements from columns III and V of the Mendeleev periodic table. Elements from column III include boron, gallium, aluminum, or indium. Elements from column V include, for example, nitrogen, arsenic, antimony, and phosphorus.

[0049] By "selective etching relative to..." or "etching with selectivity relative to...", it is meant that the etching is configured to remove material A or layer A relative to material B or layer B, and the etching rate of material A is greater than the etching rate of material B. The selectivity is the ratio of the etching rate of material A to the etching rate of material B. The selectivity between A and B is expressed as SA:B.

[0050] Figure 1A A reference coordinate system is shown, preferably an orthogonal reference system including x, y, z axes. This reference system can be extended to other figures.

[0051] In the present patent application, it is preferred to consider the thickness of a layer and the height of a structure or device. The thickness is taken along the normal direction of the main extension plane of the layer, and the height is taken perpendicular to the base plane XY. Thus, when a layer extends mainly along the plane XY, it usually has a thickness along z, while a protruding element, such as an isolation trench, has a height along the z axis. The relative terms "upper", "lower", "bottom layer" preferably refer to a position taken along the direction z.

[0052] The steps of the claimed methods are to be understood in a broad sense and may optionally be performed in a plurality of sub-steps.

[0053] Now refer to Figures 1A to 1G and Figure 3 An example of a production method is described. This method enables obtaining Figure 1G The structure shown includes etching the interface 1000 between the III-V material layer 100 and the dielectric layer 200 .

[0054] like Figure 1AAs shown, the first step is to provide a layer 100 based on at least one III-V material, preferably based on at least one III-N material. Typically, this material is based on GaN. This layer is called III-V layer 100. III-V layer 100 has an upper surface 101 and a lower surface 102, both of which extend mainly on a plane XY of an orthogonal reference system XYZ. It has a thickness e along a direction z. 100 .

[0055] The III-V layer 100 may be formed of homogeneous layers, typically of one single material. Alternatively, the III-V layer 100 may be formed of a stack of III-N material layers, at least some of which have different compositions. For example, the III-V layer 100 may be formed of one or more GaN layers and one or more P-, AlGaN-, AlN- and / or InGaN-doped GaN layers. Typically, the III-V layer 100 may be formed of an assembly of one or more GaN layers and an AlGaN layer, the AlGaN layer covering the assembly. This is the case, for example, in certain HEMT-type transistors.

[0056] The III-V layer 100 may be placed on a substrate, typically a support substrate or a growth substrate. Figures 1A to 1G One or more intermediate layers, in particular nucleation layers, may be arranged between the substrate and the lower surface 102 of the III-V layer 100 .

[0057] The second step is to etch at least a portion of the III-V layer 100 from its upper surface 101 and perform thickness etching. Figure 3 Block 31 in FIG. 3 is shown. Etching is advantageously performed so as to obtain a thickness greater than 100 nm (10 -9 m), preferably greater than 500 nm, preferably greater than 1 μm (10 -6 m), preferably an etching thickness greater than 3 μm etching The III-V layer 100 is etched. Figure 1C As shown, in order to etch only certain areas of the III-V layer 100, a mask 310 may be formed on the III-V layer 100. However, the presence of the mask 310 is not mandatory for implementing the etching method described below. According to one example, the mask 310 is disposed in direct contact with the upper surface 101 of the III-V layer 100. For example, the mask 310 is formed by photolithography of a mask layer 300 deposited or transferred onto the III-V layer 100, as shown in FIG. Figure 1B As shown. Preferably, mask 310 is a hard mask. It is preferably based on a polymer (eg, resin) or a dielectric. For example, it is based on SiO2 or Si x N YWhere x and Y are non-zero integers. For example, the hard mask 310 can be formed of one of the following materials or a mixture of several of the following materials: SiN, Si3N4, SiOCN, SiCBN. Figure 1C As shown, the mask 310 has at least one opening 311 through which the etching of the III-V layer 100 is performed.

[0058] The etching may be dry etching or wet etching. For example, this may be a chlorine or fluorocarbon chemical plasma etching step. The etching step may be carried out in a reactive ion etching (RIE) reactor, preferably an inductively coupled plasma (ICP) reactor. It is also possible to implement a self-limiting cyclic etching method, such as atomic layer etching (ALE), alone or as a supplement to conventional plasma etching. This method generally consists of one or more cycles, comprising the following steps: - a step of modifying a portion of the layer to be etched, preferably situated on the surface of this same layer, for example by self-limiting chlorination by exposure to a Cl2 / BCl3 plasma; - etching the thus selectively modified portion of the layer to be etched into the rest of the layer to be etched, for example using an Ar-based plasma and at a non-zero bias voltage.

[0059] The self-limiting cyclic etching method can significantly limit the damage to the etched layer. In conjunction with the plasma treatment step described below, the step of etching the III-V layer 100 by this method can further improve the quality of the interface 1000. However, the step of etching the III-V layer 100 can be limited to conventional plasma etching.

[0060] The above-mentioned etching techniques are merely illustrative and in no way constitute an exhaustive list of contemplated techniques.

[0061] like Figure 1D As shown, the etching step just described enables exposure of a surface of the III-V layer 100, referred to as the etched surface 103. According to one example, this etching enables the formation of trenches in the III-V layer 100, for example.

[0062] The third step includes exposing the etched surface 103 to Figure 1E The treatment is shown in FIG. 1 by the vertical arrows pointing toward the etched surface 103. The treatment is performed by a plasma based on oxygen (O2) and / or nitrogen (N2). This step is performed by Figure 3Represented by block 32. Advantageously, the step of etching the III-V layer 100 is carried out in the same chamber. Preferably, it is an ICP reactor. The step of carrying out an in-situ plasma treatment makes it possible to limit the contamination caused by the exhaust of the sample and to increase the productivity. This also has advantages associated with the structural defects caused by the etching step. In fact, after the etching step, the etched surface 103 constitutes a reactive surface, which reacts with the air during the exhaust process to form defects. For example, the gaps on the etched surface 103 caused by etching will be filled with pollutants in the air (for example carbon-based or oxygen-based pollutants). Therefore, the latter will constitute a capture trap that can hinder the dielectric deposition step detailed above and / or change the electronic properties of the device obtained after additional subsequent steps. Before the exhaust of the sample, the etched surface 103 is subjected to an in-situ plasma treatment, making it possible to fill these gaps with favorable elements provided by the plasma, thereby limiting the filling of these same gaps with elements present in the air. For example, the nitrogen gaps of the GaN-based etched surface 103 can be filled with nitrogen atoms provided by the N2-based plasma treatment.

[0063] However, the plasma treatment can be performed in a different chamber than the chamber used to etch the III-V layer 100 .

[0064] O2 flow or N2 flow is generated in the treatment chamber by a source, the power of which is between 100W and 4000W, preferably between 300W and 1000W. The power of the flow is a parameter that has a direct influence on the reactivity of the formed plasma. Within the scope of the present invention, it is sought to obtain a plasma with high chemical reactivity to ensure that the etched surface 103 is well reconstructed within a reduced processing time. This is particularly characterized by a high reactive radical concentration and a limited number of ions. Increasing the power of the flow enables the number of reactive radicals to be increased, but also has the effect of increasing the ion density. Therefore, the above preferred values ​​constitute a good compromise. The flow can be pure or can be mixed with other trace gases. For example, this can be a flow composed of N2 and O2, N2 and Ar, or O2 and Ar. The flow rate of the substance is advantageously between 50sccm and 1000sccm (cubic centimeters per minute), preferably between 100sccm and 500sccm. The duration of the plasma treatment step is advantageously between a few seconds (preferably 30s) and hundreds of seconds. The bias voltage is preferably zero. In fact, choosing a non-zero bias voltage, combined with the fact that the plasma contains ions, increases the risk of degradation.

[0065] The plasma treatment step is carried out at a temperature below 100°C, instead of at high temperatures as in current etch layer recrystallization techniques. Such treatment conditions make it possible to improve the quality of the interface 1000 in unexpected proportions. This low temperature level makes it possible in particular to obtain a stable interface 1000 after the plasma treatment step. This makes it possible to improve the robustness of the method and therefore the quality of the interface, while increasing productivity. Moreover, in the case of an O2-based plasma treatment, low temperature operation makes it possible to avoid undesired oxidation on the etched surface 103.

[0066] The treatment temperature, i.e. the temperature of the substrate carrier on which the III-V layer 100 is placed in the plasma treatment chamber, is preferably greater than 20° C. Preferably, it is less than 90° C. Advantageously, it is between 40° C. and 80° C., preferably between 60° C. and 80° C. Increasing the temperature makes it possible in particular to improve the reactivity of the etched surface 103 and thus optimize the structural reconstruction of the III-V layer 100.

[0067] Advantageously, but optionally, after the step of exposure to the plasma treatment, a wet cleaning of the etched surface 103 of the III-V layer 100 is provided. This cleaning is advantageously HCl-, HF-based or based on a mixture of HCl and HF. This step enables the etched surface to be cleaned before the deposition of the dielectric layer 200 and constitutes a complement to the plasma treatment. It also enables the electrical properties of the interface between the etched III-V layer 100 and the dielectric layer 200 to be improved. The extent of improvement in these electrical properties is surprising. This cleaning step is carried out outside the reactor capable of etching the III-V layer 100. This optional step consists of Figure 3 This is indicated by a block 33 drawn with a dotted line.

[0068] The fourth step is Figure 1F and Figure 3 As shown in block 34 of , it includes depositing a layer based on a dielectric material at least on the etched surface 103 of the III-V layer 100. This layer is called dielectric layer 200. Preferably, the dielectric layer 200 is composed of a dielectric material selected from one of the following materials or a mixture of these materials: AlN, Al2O3, HfO2. Preferably, the deposition of the dielectric layer 200 is carried out by ALD (atomic layer deposition). This can be a thermal or plasma ALD method. In the specific case where the dielectric layer 200 is an Al2O3 layer and is deposited by thermal ALD, the oxygen-based precursor can be water (H2O) or ozone (O3), and the aluminum-based precursor can be trimethylaluminum (TMA). If the deposition is carried out by plasma ALD, the oxygen-based precursor can be a dioxygen (O2)-based plasma. The deposition of the dielectric layer 200 is preferably carried out under vacuum conditions to avoid contamination.

[0069] The contact area between the lower surface 202 of the dielectric layer 200 and the etched surface 103 of the III-V layer 100 constitutes an interface 1000 between the III-V layer 100 and the dielectric layer 200 .

[0070] Figure 1G An optional step of removing certain portions of the mask 310 and the dielectric layer 200 is shown. This removal can be performed before or after the step of exposing the etched surface 103 to the plasma treatment and before or after the step of depositing the dielectric layer 200. For example, this removal can be performed simultaneously with the cleaning step. In this case, HF or HCl and HF-based solvents are preferably used. Advantageously, the mask 310 is retained until the step of exposing to the plasma treatment, during which it can act as a mask. As shown in FIG. Figure 1F As shown, the mask 310 may also be retained until the step of depositing the dielectric layer 200 .

[0071] Figure 2A and Figure 2B One of the advantages provided by the method according to the invention is shown. Figure 2A The graph shown is a CV (capacitance-voltage) characteristic of a MOS capacitor including an interface between an etched GaN layer and an Al2O3 layer and obtained by a method that does not include plasma treatment after etching the GaN layer. Figure 2B The graph shown is the CV characteristics of a MOS capacitor designed by the same method and the same materials according to an embodiment of the present invention, but its etched GaN layer has been subjected to plasma treatment and HCL-based wet cleaning in an ICP reactor. Figure 2A and Figure 2B In FIG. 5 , the CV characteristics at different frequencies of the AC signal applied to the MOS capacitor under study are recorded respectively.

[0072] It is worth noting that, especially at low frequencies (see the characteristics at 5kHz in particular) and high frequencies (see the characteristics at 500kHz in particular), Figure 2A The performance of the MOS capacitor characterized in Figure 2B The slope of the characteristic at each frequency studied is actually lower than Figure 2B This reflects the slower transition from the accumulation state to the reversal state in response to the voltage change. Figure 2A and Figure 2B It can be found that the performance of electronic components involving etching of III-V material / dielectric interfaces is significantly improved due to the method of the present invention.

[0073] Figure 4 , Figure 5A and Figure 5BThis illustrates the fact that, as mentioned above, the choice of the treatment temperature makes it possible to optimize the performance of the device produced according to the invention. Figure 4 Shown are graphs of the CV characteristics of a MOS capacitor comprising an interface between a dielectric and a III-V material obtained by implementing an embodiment of a method according to the invention and for two different processing temperatures: 40°C and 60°C. Figure 5A and Figure 5B The flatband voltage Vfb and hysteresis ΔVfb values ​​of the two samples are shown. It can be seen that the MOS capacitor treated at 60°C has better electrical performance than the MOS capacitor treated at 40°C. In particular, its flatband voltage is larger (T treatment =40°C is about 1.61V vs. 1.35V, and its hysteresis is significantly smaller (T treatment =40°C is about 0.56 V vs. 0.65 V). Therefore, increasing the treatment temperature in the plasma treatment step can significantly improve the performance of the device to a certain extent, because the surface defects are better absorbed.

[0074] However, it is worth noting that, surprisingly, the performance of the MOS capacitors drops rapidly and drastically when the temperature exceeds 80°C. This illustrates the fact that treating samples at high or even ultra-high temperatures in the hope of obtaining better recrystallization is not always appropriate. On the contrary, too fast recrystallization can freeze structural defects, especially surface defects, leading to a degradation of the device's performance.

[0075] These results therefore illustrate the optimization of the structural reconstruction of III-V layers in the range of 60°C–80°C.

[0076] The advantage of the solution proposed by the invention is that the steps of exposing the etched III-V layer 100 to a plasma treatment and depositing the dielectric layer 200 can be performed after any type of etching and for any III-V material. The method according to the invention thus provides a universal solution to the problem of the interface quality between the etched III-V material and the dielectric. Furthermore, this adaptability also allows a certain standardization of the methods for manufacturing electronic components, in which the method according to the invention can be integrated.

[0077] Another advantage of the proposed solution is that the plasma treatment step is a fast step which can be performed in the same reactor immediately after the etching step. Thus, the method according to the invention can be integrated into a method for manufacturing microelectronic devices without affecting the production efficiency.

[0078] It can be clearly seen from the above different embodiments that the present invention provides an effective solution for improving the productivity of etching an interface between a III-V material layer and a dielectric layer while ensuring good quality of the interface.

[0079] The proposed method is particularly advantageous for power applications such as power transistors, LEDs or µLEDs, where the thickness of the III-V material to be etched, such as GaN, can vary from a hundred nanometers to several micrometers.

[0080] The present invention is not limited to the above-described embodiments, but extends to all embodiments encompassed by the spirit thereof.

Claims

1. A method for forming a layer based on a dielectric material on a layer based on an etched III-V material, the method comprising at least the following steps: • providing at least one layer based on a III-V material, preferably a III-N material, referred to as III-V layer ( 100 ), said III-V layer ( 100 ) having a front side ( 101 ); • etching at least a portion of the III-V layer (100) from the front side (101) to expose a surface of the III-V layer, which is referred to as an etched surface (103); • exposing at least the etched surface (103) to a plasma treatment of O2, N2 or a mixture of O2 and N2 at a temperature T between 60°C and 80°C treatment Next proceed; • Depositing a layer based on a dielectric material, called dielectric layer (200), at least on said etched surface.

2. The method according to the preceding claim, wherein: The etching step and the plasma treatment step are performed in the same reactor.

3. A method according to any one of the preceding claims, wherein: The duration of the plasma treatment step is t treatment <5min, preferably, the duration t treatment <2min.

4. The method according to any one of the preceding claims, further comprising a wet cleaning step prior to the step of depositing the dielectric layer.

5. A method according to any one of the preceding claims, wherein: The step of depositing the dielectric layer is performed under vacuum.

6. A method according to any one of the preceding claims, wherein: The etching step includes chlorine plasma etching.

7. A method according to any one of the preceding claims, wherein: The etching step comprises at least one ALE type etching cycle.

8. A method according to any one of the preceding claims, wherein: The plasma treatment step is performed at a zero bias voltage V bias The following is carried out.

9. A method according to any one of the preceding claims, wherein: The etching is performed to etch the III-V material to a thickness greater than 100 nm (10 -9 m), preferably greater than 500 nm, preferably greater than 1 μm (10 -6 m), preferably greater than 3µm.

10. A method according to any one of the preceding claims, wherein: The plasma treatment step is performed by injecting a mass flow rate D flow This is carried out at an O2 flow, a N2 flow or a mixed flow of O2 and N2 between 50 sccm and 1000 sccm, preferably between 100 sccm and 500 sccm.

11. A method according to any one of the preceding claims, wherein: The plasma treatment step is performed by injecting a power source P between 100W and 4000W, preferably between 300W and 1000W. source This is done by producing an O2 flow, a N2 flow, or a mixture flow of O2 and N2.

12. A method according to any one of the preceding claims, wherein: The III-V material is one of GaN and AlGaN.

13. A method according to any one of the preceding claims, wherein: The dielectric material is one of AlN, Al2O3 and HfO2.

14. A method for manufacturing a microelectronic device, comprising forming a layer based on a dielectric material (200) on an etched III-V material based layer (100) by implementing the method of any one of the preceding claims, the microelectronic device being selected from a transistor and an LED.

15. Method for manufacturing a microelectronic device according to the preceding claim, wherein: • the microelectronic device is a transistor; • etching the III-V layer (100) so as to produce trenches in the etched III-V material; • depositing said layer based on dielectric material (200) on at least a portion of the etched surface of said trench to form a gate dielectric; After forming the dielectric layer (200), the method comprises the following steps: • Filling the trench to define at least one gate of the transistor.

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