Semiconductor package

Abstract

A semiconductor package according to an embodiment includes: a first substrate including a first pad and a second pad; a first connection unit disposed on the first pad of the first substrate; a second substrate coupled to the first connection unit; a second connection unit disposed on the second pad of the first substrate; an element mounted on the second connection unit; and a molding layer disposed on the first substrate to mold the element. The element includes one of a capacitor and an inductor, and the second substrate includes a patterned layer functionally different from the element among the capacitor and the inductor.

Description

Technical Field

[0001] Embodiments relate to a semiconductor package, and more particularly, to a semiconductor package including an inductor substrate. Background Art

[0002] The demand for portable devices in today's electronics market is growing rapidly, and in order to meet this demand, miniaturization of components installed in the system is essential.

[0003] In order to achieve miniaturization of components, technology for reducing the individual size of mounted components, SOC (System on Chip) technology for integrating multiple individual devices into a single chip, and SIP (System in Package) technology for integrating multiple individual devices into a single package, etc. are required.

[0004] In recent years, in accordance with the trend of multifunctionalization and miniaturization of mobile communication terminals such as mobile phones, PDAs (personal digital assistants), smart phones, and various media terminals, various components installed in the terminals or modules installed in headphones are moving toward miniaturization. In order to miniaturize these modules, research is being conducted to implement components such as RF (radio frequency) devices and IC chips into a single package.

[0005] Therefore, conventional semiconductor packaging is to mount an integrated passive device (IPD) on a substrate to reduce the overall volume. However, when multiple integrated passive devices are placed on a single substrate, electrical reliability issues arise due to interference between them. Summary of the invention

[0006] Technical issues

[0007] Embodiments provide a semiconductor package with improved electrical reliability.

[0008] In addition, the embodiment provides a semiconductor package in which a second substrate having a function of a second device is disposed on a first substrate on which a first device is disposed, thereby minimizing interference between the first device and the second device.

[0009] In addition, the embodiment provides a semiconductor package capable of greatly reducing the thickness of a second substrate having the function of a second device.

[0010] In addition, the embodiment provides a semiconductor package including a second substrate formed on an insulating layer, the second substrate having a plurality of coil patterns with different inductance values.

[0011] In addition, the embodiment provides a semiconductor package capable of reducing the thickness.

[0012] Technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the proposed embodiments belong from the following description.

[0013] Technical Solution

[0014] According to an embodiment, a semiconductor package includes: a first substrate, which includes a first pad and a second pad; a first connecting part, which is arranged on the first pad of the first substrate; a second substrate, which is coupled to the first connecting part; a second connecting part, which is arranged on the second pad of the first substrate; a device, which is mounted on the second connecting part; and a molding layer, which is arranged on the first substrate and molds the device, wherein the device includes one of a capacitor and an inductor, and the second substrate includes a pattern layer having a function different from that of the device.

[0015] In addition, the second substrate includes: a second insulating layer; a second circuit pattern disposed on the second insulating layer and corresponding to the pattern layer; and a second through electrode penetrating the second insulating layer.

[0016] In addition, the second substrate further includes a second protection layer disposed at the upper and lower surfaces of the second insulating layer, and the molding layer molds the device at a position spaced apart from the second substrate.

[0017] In addition, the mold layer molds the second insulating layer and the second circuit pattern of the second substrate.

[0018] In addition, the second substrate is an inductor substrate including a coil pattern forming an inductor, and the device includes: a first device corresponding to a capacitor; and a second device spaced apart from the first device and corresponding to an inductor.

[0019] In addition, the second substrate is a capacitor substrate including a capacitor pattern forming a capacitor, and the device includes: a first device corresponding to the capacitor; and a second device spaced apart from the first device and corresponding to the inductor.

[0020] In addition, the second circuit pattern includes a first pattern layer arranged on the upper surface of the second insulating layer, and a second pattern layer arranged on the lower surface of the second insulating layer, wherein the first pattern layer includes a plurality of coil patterns, and the plurality of coil patterns include a first coil pattern having a first spacing distance from the second pattern layer, and a second coil pattern having a second spacing distance from the second pattern layer different from the first spacing distance.

[0021] In addition, the first coil pattern is disposed in a pattern groove formed at an upper surface of the second insulating layer, and the second coil pattern protrudes on the upper surface of the second insulating layer.

[0022] In addition, the first coil pattern is disposed in a first groove having a first depth formed at an upper surface of the second insulating layer, and the second coil pattern is disposed in a second groove having a second depth different from the first depth formed at an upper surface of the second insulating layer.

[0023] In addition, the second insulating layer includes PID (Photo Imageable Dielectric Resin).

[0024] Beneficial Effects

[0025] The semiconductor package of the embodiment includes a first substrate and a second substrate. In addition, the semiconductor package includes at least one device mounted on the first substrate. In addition, the second substrate is mounted on the first substrate and can perform an inductor function or a capacitor function.

[0026] Specifically, the embodiment configures one of the inductor and the capacitor as a core-type device, and configures the other of the inductor and the capacitor as a substrate-type device. Therefore, the embodiment can ensure the design space of the semiconductor package, and thereby ensure the degree of freedom of design. In addition, the embodiment implements different types of inductors and capacitors to solve reliability problems that may occur between the inductor and the capacitor. For example, when the inductor and the capacitor are arranged adjacent to each other, there may be a problem of degradation of the characteristics of each function due to interference therebetween. Therefore, the embodiment implements different types of inductors and capacitors, and can solve the problem of degradation of the characteristics of each function. In addition, the embodiment can maximize the characteristics of the inductor function and the capacitor function, thereby further improving product reliability.

[0027] In addition, embodiments include a plurality of inductors or a plurality of capacitors. In addition, one of the plurality of inductors is configured as a core-type device, and another of the plurality of inductors is configured as a substrate-type device. In addition, in embodiments, one of the plurality of capacitors is configured as a core-type device, and another of the plurality of capacitors is configured as a substrate-type device.

[0028] Therefore, the embodiments can further maximize the inductor function or the capacitor function and thereby further improve product performance.

[0029] In addition, the second substrate of the embodiment includes a second insulating layer, which includes a photosensitive material. In addition, the pattern layer of the second substrate is inserted into the groove of the second insulating layer or has a protruding structure. In addition, the groove of the second insulating layer can include a plurality of grooves with different depths, and the pattern layer can be respectively arranged in the plurality of grooves. Through this, the embodiment can realize a plurality of inductors in one second substrate. Therefore, the embodiment can further improve product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1is a diagram showing a semiconductor package according to a first embodiment.

[0031] Figure 2 is a diagram showing a semiconductor package according to a second embodiment.

[0032] Figure 3a It is shown Figure 1 or Figure 2 A first pattern layer diagram of a second circuit pattern of a second substrate.

[0033] Figure 3b It is shown Figure 1 or Figure 2 A diagram of a second pattern layer of a second circuit pattern of a second substrate.

[0034] Figure 3c It is shown Figure 1 or Figure 2 A diagram of a third pattern layer of a second circuit pattern of a second substrate.

[0035] Figure 4 is a diagram showing a specific layer structure of the second substrate according to the first embodiment.

[0036] Figure 5 is a diagram showing a specific layer structure of a second substrate according to the second embodiment.

[0037] Figure 6 is a diagram showing a specific layer structure of a second substrate according to a third embodiment.

[0038] Figure 7 is a diagram showing a specific layer structure of a second substrate according to a fourth embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] However, the spirit and scope of the present disclosure are not limited to parts of the depicted embodiments and can be implemented in various other forms, and one or more elements of the embodiments can be selectively combined and rearranged within the spirit and scope of the present disclosure.

[0041] In addition, unless otherwise clearly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present disclosure can be interpreted as the same meaning as the meaning generally understood by a person of ordinary skill in the art to which the present disclosure belongs, and the terms defined in common dictionaries can be interpreted as having the same meaning as the meaning in the context of the relevant field. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0042] In this specification, unless otherwise specified in a phrase, a singular form can also include a plural form, and can include at least one of all combinations that can be combined among A, B, and C when described in “at least one (or more) of A (and), B, and C”. In addition, when describing elements of an embodiment of the present disclosure, terms such as first, second, A, B, (a), and (b) can be used.

[0043] These terms are only used to distinguish an element from other elements, and these terms are not limited to the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "in contact with" another element, it can include not only when the element is directly "connected", "coupled" or "in contact with" the other element, but also when the element is "connected", "coupled" or "in contact with" another element between the element and the other element.

[0044] In addition, when described as being formed or disposed “on (above)” or “below (below)” of each element, “on (above)” or “below (below)” can include not only when two elements are directly connected but also when one or more other elements are formed or disposed between the two elements. Furthermore, when expressed as “on (above)” or “below (below)”, based on one element, it can include not only an upper direction but also a lower direction.

[0045] -Electronic Devices-

[0046] Before describing the embodiment, the electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. Various semiconductor devices can be mounted on the semiconductor package. In a broad sense, the various semiconductor devices mounted on the semiconductor package can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as central processing units (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and application-specific ICs (ASICs).

[0047] Additionally, a device or chip may include passive devices and active devices.

[0048] An active device refers to a component that actively utilizes the nonlinear part of the signal characteristics. In addition, a passive device refers to a component that does not utilize the nonlinear signal characteristics even if both linear and nonlinear signal characteristics exist. For example, active devices may include transistors, IC semiconductor devices, and passive devices may include capacitors, resistors, inductors, etc. Passive devices can increase the signal processing speed of a semiconductor chip as an active device, or perform a filtering function. In addition, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communications.

[0049] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (package stacking) and SIP (system in package), but is not limited thereto.

[0050] In this case, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a display, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0051] Figure 1 is a diagram showing a semiconductor package according to a first embodiment, Figure 2 is a diagram showing a semiconductor package according to a second embodiment, Figure 3a It is shown Figure 1 or Figure 2 a diagram of a first pattern layer of a second circuit pattern of a second substrate, Figure 3b It is shown Figure 1 or Figure 2 a second pattern layer of a second circuit pattern of a second substrate, and Figure 3c It is shown Figure 1 or Figure 2 A diagram of a third pattern layer of a second circuit pattern of a second substrate.

[0052] refer to Figures 1 to 3c , the semiconductor package of the embodiment includes a first substrate 100 and a second substrate 200. The first substrate 100 includes a plurality of pads. In addition, the semiconductor package of the embodiment may include a device disposed on at least one of the plurality of pads of the first substrate 100. For example, the semiconductor package of the embodiment may include a first device 300 and a second device 400 mounted on the first substrate 100.

[0053] The first substrate 100 may have a multi-layer structure.

[0054] The first substrate 100 may have a six-layer structure based on the number of layers of the insulating layer. However, the embodiment is not limited thereto.

[0055] For example, the first substrate 100 may have a layer structure of five or fewer layers based on the number of layers of the insulating layer. Different from this, the first substrate 100 may have a layer structure of seven or more layers based on the number of layers of the insulating layer. Hereinafter, for ease of explanation, the first substrate 100 is described as having a six-layer structure based on the number of layers of the insulating layer.

[0056] The first substrate 100 includes a first insulating layer 110. The first insulating layer 110 may have a six-layer structure.

[0057] For example, the first insulating layer 110 may include, from the bottom, a first-first insulating layer 111, a first-second insulating layer 112, a first-third insulating layer 113, a first-fourth insulating layer 114, a first-fifth insulating layer 115, and a first-sixth insulating layer 116. The first-second insulating layer 112, the first-third insulating layer 113, the first-fourth insulating layer 114, and the first-fifth insulating layer 115 may be inner insulating layers in the inner layers provided in the laminated structure of the first substrate 100. In addition, the first-first insulating layer 111 may be a first outer insulating layer provided at the lowermost side in the laminated structure of the first substrate 100. In addition, the first-sixth insulating layer 116 may be a second outer insulating layer 100 provided at the uppermost side in the laminated structure of the first substrate.

[0058] The first insulating layer 110 is a substrate on which a circuit capable of changing wiring is formed, and may include all of a printing, a wiring board, and an insulating substrate made of an insulating material capable of forming a circuit pattern on a surface.

[0059] The first insulating layer 110 may be rigid or flexible. For example, the first insulating layer 110 may include glass or plastic. Specifically, the first insulating layer 110 may include chemically strengthened / semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. Alternatively, the first insulating layer 110 may include reinforced or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). Alternatively, the first insulating layer 110 may include sapphire.

[0060] In addition, the first insulating layer 110 may include an optically isotropic film. For example, the first insulating layer 110 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0061] In addition, the first insulating layer 110 may be formed of a material including an inorganic filler and an insulating resin. For example, the first insulating layer 110 may include a structure in which an inorganic filler such as silicon dioxide or aluminum oxide is dispersed in a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. For example, the first insulating layer 110 may include ABF (Ajinomoto deposited film), FR-4, BT (bismaleimide triazine), PID (photoimageable dielectric resin), BT, etc.

[0062] In addition, the first insulating layer 110 may be bent while partially having a curved surface. That is, the first insulating layer 111 may be bent while partially having a plane and partially having a curved surface. In detail, the first insulating layer 110 may be bent while having a curved end, or may be bent or curved while having a surface including an arbitrary curvature.

[0063] In addition, the first insulating layer 110 may be a flexible substrate having a flexible property. In addition, the first insulating layer 110 may be a curved or bent substrate. At this time, the first insulating layer 110 expresses the electrical wiring connecting the circuit components based on the circuit design as a wiring diagram, and is able to reproduce the electrical conductor on the insulating material. In addition, the first insulating layer 110 may mount the device and form the wiring that electrically connects them. In addition, in addition to the electrical connection function of the device, the first insulating layer 110 may also mechanically fix the device.

[0064] Each layer of the first insulating layer 110 may have a thickness in the range of 10 μm to 60 μm. Preferably, each layer of the first insulating layer 110 may have a thickness in the range of 12 μm to 50 μm. More preferably, each layer of the first insulating layer 110 may have a thickness in the range of 15 μm to 40 μm.

[0065] If the thickness of at least one layer among each layer of the first insulating layer 110 is less than 10 μm, the circuit pattern on the first substrate 100 may not be stably protected. If the thickness of at least one layer among each layer of the first insulating layer 110 exceeds 60 μm, the thickness of the first substrate 100 and the thickness of the semiconductor package including the first substrate 100 may increase. In addition, if the thickness of at least one layer among each layer of the first insulating layer 110 exceeds 60 μm, the thickness of the circuit pattern and the thickness of the through electrode may increase accordingly. In addition, if the thickness of the circuit pattern and the thickness of the through electrode increase, the signal transmission loss may increase.

[0066] Meanwhile, the first substrate 100 may be a coreless substrate, but is not limited thereto. For example, the first substrate 100 may be a core substrate. In addition, when the first substrate 100 is a core substrate, at least one of the inner insulating layers of the first insulating layer 110 may be a core layer. In addition, the core layer may have a thickness greater than that of other layers of the first insulating layer 110.

[0067] The first substrate 100 includes a first circuit pattern 120 disposed on the first insulating layer 110. The first circuit pattern 120 may be disposed on a surface of each layer of the first insulating layer 110.

[0068] The first circuit pattern 120 may be formed of a metal material having high electrical conductivity as a wiring for transmitting electrical signals. To this end, the first circuit pattern 120 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern 120 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit pattern 120 may be formed of copper (Cu) having high electrical conductivity and relatively low price.

[0069] The first circuit pattern 120 may be formed by a conventional manufacturing process of a printed circuit board such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), and a detailed description thereof is omitted herein.

[0070] The first circuit pattern 120 includes a trace and a pad. A trace means a long line-shaped wiring that transmits an electrical signal. In addition, a pad may mean a mounting pad on which a component such as a chip is mounted, a terminal pad or a core pad or a BGA pad for connection with an external circuit board, or a through-hole pad connected to a through-hole.

[0071] Preferably, the first circuit pattern 120 may include a plurality of pads. At this time, the plurality of pads may mean a portion of the first circuit pattern 120 disposed at the uppermost side.

[0072] The first circuit pattern 120 includes pads disposed on the upper surface of the first insulating layer 110. For example, the first circuit pattern 120 includes pads disposed on the upper surfaces of the first to sixth insulating layers 116 disposed at the uppermost side among the first insulating layers 110.

[0073] The first circuit pattern 120 includes a first pad 123. The first pad 123 may serve as a bonding pad for bonding the second substrate 200 to the first substrate 100.

[0074] The first pad 123 can be formed in plurality on the upper surface of the first insulating layer 110. In addition, the plurality of first pads 123 may be electrically connected to pads (not shown) of the second substrate 200, respectively.

[0075] The first circuit pattern 120 may include a second pad 121 disposed on the upper surface of the first insulating layer 110. The second pad 121 may be used as a first mounting pad for mounting the first device 340 on the first substrate 100. The second pad 121 may include a plurality of pads. The number of the second pads 121 may correspond to the number of the first terminals 345 of the first device 340. For example, the first device 340 may include two first terminals 345. Therefore, the second pad 121 can be configured in two numbers.

[0076] The first circuit pattern 120 may include a third pad 122 disposed on the upper surface of the first insulating layer 110. The third pad 122 may be used as a second mounting pad for mounting the second device 350 on the first substrate 100. The third pad 122 may include a plurality of pads. The number of the third pads 122 may correspond to the number of the second terminals 355 of the second device 350.

[0077] The first device 340 and the second device 355 may be active devices, or alternatively, may be passive devices. For example, at least one of the first device 340 and the second device 355 may include an integrated passive device (IPD). For example, the integrated passive device may include a capacitor. For example, at least one of the first device 340 and the second device 355 may be a multilayer ceramic capacitor (MLCC). The multilayer ceramic capacitor may have a two-terminal structure, or alternatively, may have a three-terminal structure. However, the embodiment is not limited thereto. For example, at least one of the first device 340 and the second device 355 may include an inductor. Specifically, the embodiment configures at least one of the capacitor and the inductor as a core-type device. In addition, the embodiment configures at least another of the capacitor and the inductor as a substrate type.

[0078] For example, the second substrate 200 may be an inductor substrate including a coil pattern used as an inductor. In this case, at least one of the first device 340 and the second device 355 may include a capacitor.

[0079] In addition, the second substrate 200 may be a capacitor substrate including a pattern used as a capacitor. In this case, at least one of the first device 340 and the second device 355 may include an inductor.

[0080] The semiconductor package of the embodiment includes a first substrate and a second substrate. In addition, the semiconductor package includes at least one device mounted on the first substrate. In addition, the second substrate is mounted on the first substrate and can perform an inductor function or a capacitor function.

[0081] Specifically, the embodiment configures one of the inductor and the capacitor as a core-type device, and configures the other of the inductor and the capacitor as a substrate-type device. Therefore, the embodiment can ensure the design space of the semiconductor package, and thereby ensure the degree of freedom of design. In addition, the embodiment implements different types of inductors and capacitors to solve reliability problems that may occur between the inductor and the capacitor. For example, when the inductor and the capacitor are arranged adjacent to each other, there may be a problem of degradation of the characteristics of each function due to interference therebetween. Therefore, the embodiment implements different types of inductors and capacitors, and can solve the problem of degradation of the characteristics of each function. In addition, the embodiment can maximize the characteristics of the inductor function and the capacitor function, thereby further improving product reliability.

[0082] In addition, embodiments include a plurality of inductors or a plurality of capacitors. In addition, one of the plurality of inductors is configured as a core-type device, and another of the plurality of inductors is configured as a substrate-type device. In addition, in embodiments, one of the plurality of capacitors is configured as a core-type device, and another of the plurality of capacitors is configured as a substrate-type device.

[0083] Therefore, the embodiments can further maximize the inductor function or the capacitor function and thereby further improve product performance.

[0084] Meanwhile, the first circuit pattern 120 may have a thickness of 10 μm to 25 μm. Preferably, the first circuit pattern 120 may have a thickness of 12 μm to 23 μm. More preferably, the first circuit pattern 120 may have a thickness of 15 μm to 20 μm. If the thickness of the first circuit pattern 120 exceeds 25 μm, it may be difficult to refine the line width or spacing of the first circuit pattern 120. If the thickness of the first circuit pattern 120 is less than 10 μm, it may be difficult to implement a normal circuit.

[0085] The first substrate 100 may include a first through electrode 130. The first through electrode 130 may penetrate the first insulating layer 110. For example, the first through electrode 130 may penetrate at least one insulating layer among a plurality of insulating layers constituting the first insulating layer 110. The first through electrode 130 may individually penetrate each insulating layer constituting the first insulating layer 110. Alternatively, the first through electrode 130 may collectively penetrate at least two insulating layers among the insulating layers constituting the first insulating layer 110.

[0086] The first through-electrode 130 can be formed by forming a first through hole penetrating the first insulating layer 110 and filling the formed first through hole with a conductive material. The first through hole can be formed by any one of mechanical, laser and chemical processing methods. The first through hole can be formed by a mechanical processing method such as milling, drilling and routing. In addition, the first through hole can be formed using a UV or CO2 laser method. In addition, the first through hole can be formed using a chemical processing method using a chemical agent including aminosilane, ketone, etc.

[0087] When forming the first through hole, the first through hole can be filled with a conductive material to form the first through electrode 130. The first through electrode 130 may be formed of any one of a metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni) and palladium (Pd). In addition, the conductive material filling may utilize any one of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing or a combination thereof.

[0088] The first substrate 100 may include a first protective layer. For example, the first substrate 100 may include a first-first protective layer 141 disposed on a lower surface of the first insulating layer 110. In addition, the first substrate 100 may include a first-second protective layer 142 disposed on an upper surface of the first insulating layer 110.

[0089] The first protective layer may be provided to cover a surface of the first insulating layer 110 and a surface of the first circuit pattern 120. In addition, the first protective layer may include an opening overlapping at least one first circuit pattern 120 in a thickness direction.

[0090] For example, the first protective layer may include a first opening overlapping the first pad 123 of the first circuit pattern 120 in the thickness direction. In addition, the first protective layer may include a second opening overlapping the second pad 121 of the first circuit pattern 120 in the thickness direction. In addition, the first protective layer may include a third opening overlapping the third pad 122 of the first circuit pattern 120 in the thickness direction.

[0091] The first protective layer may include an insulating material. The first protective layer may include various materials that can be coated to protect the surface of the first insulating layer 110 and the surface of the first circuit pattern 120, and then cured by heating. The first protective layer may be an anti-etching layer. For example, the first protective layer 150 and the second protective layer 160 may be solder resists including organic polymer materials. As an example, the first protective layer may include epoxy acrylate series resins. In detail, the first protective layer may include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic acid series monomers, etc. However, embodiments are not limited thereto, and the first protective layer may be any one of a photo solder resist, a cover layer, and a polymer material.

[0092] The thickness of the first protective layer may be 1 μm to 20 μm. The thickness of the first protective layer may be 1 μm to 15 μm. For example, the thickness of the first protective layer may be 5 μm to 20 μm. If the thickness of the first protective layer exceeds 20 μm, the overall thickness of the semiconductor package may increase. In addition, if the thickness of the first protective layer is less than 1 μm, the outermost first circuit pattern 120 included in the semiconductor package may not be stably protected.

[0093] The embodiment may include a second substrate 200 , a first device 340 , and a second device 355 , which are disposed on the first substrate 100 .

[0094] At this time, since the first device 340 and the second device 355 have been described above, a detailed description is omitted. Specifically, the first device 340 and the second device 355 may include one of an inductor and a capacitor, and the second substrate 200 may include the other of the inductor and the capacitor. However, the embodiment is not limited thereto.

[0095] For example, the semiconductor package of the embodiment may include a plurality of inductors. In addition, at least one of the plurality of inductors of the semiconductor package may be mounted on the first substrate 100 in a die type, and another one of the plurality of inductors of the semiconductor package may be implemented as the second substrate 200.

[0096] In addition, the semiconductor package of the embodiment may include a plurality of capacitors. In addition, at least one of the plurality of capacitors of the semiconductor package may be mounted on the first substrate 100 in a die type, and another one of the plurality of capacitors of the semiconductor package may be implemented as the second substrate 200.

[0097] Hereinafter, the second substrate 200 will be described in detail. The second substrate 200 may be a substrate used as a capacitor, or may be a substrate used as an inductor. For ease of explanation, the second substrate 200 is described as a substrate used as an inductor. However, the embodiment is not limited thereto.

[0098] refer to Figure 1 , the second substrate 200 may have a structure including a second insulating layer 210 , a second circuit pattern 220 , a second through electrode 230 , and a second protective layer 240 .

[0099] The second insulating layer 210 may be composed of at least one layer. Preferably, the second insulating layer 210 may have a layer structure of two or more layers. Through this, the embodiment can realize various inductances in the second substrate 200.

[0100] The second insulating layer 210 may include the same insulating material as the first insulating layer 110. In contrast, the second insulating layer 210 may include an insulating material different from that of the first insulating layer 110.

[0101] The second substrate 200 includes a second circuit pattern 220. The second circuit pattern 220 may be disposed on a surface of the second insulating layer 210. The second circuit pattern 220 may be a pattern having a coil shape.

[0102] The second substrate 200 includes a second through electrode 230 . The second through electrode 230 passes through the second insulating layer 210 .

[0103] in addition, Figure 1 The second substrate 200 of the first embodiment includes a second protective layer 240. The second protective layer 240 may be disposed on the upper surface and the lower surface of the second insulating layer 210, respectively.

[0104] In contrast, Figure 2 The second substrate 200 a of the second embodiment may have a structure in which the second protective layer 240 is omitted.

[0105] Since basic characteristics of the second substrate 200 have been described in the first substrate 100 , a detailed description thereof will be omitted.

[0106] In addition, the semiconductor package includes a molding layer 360 .

[0107] The molding layer 360 may be disposed on the first substrate 100 .

[0108] Figure 1 The mold layer 360 of the first embodiment may mold the first device 340 and the second device 350 disposed on the first substrate 100. At this time, the mold layer 360 of the first embodiment may not cover the second substrate 200. That is, the second substrate 200 includes the second protective layer 240, and therefore, the mold layer 360 can mold only the first device 340 and the second device 350.

[0109] However, the embodiment is not limited thereto. For example, the mold layer 360 can mold the second substrate 200 together with the first device 340 and the second device 350 .

[0110] in addition, Figure 2 The mold layer 360a of the second embodiment can mold the second substrate 200. At this time, the second substrate 200 can be omitted from the second protective layer 240. Therefore, the mold layer 360 can mold the second insulating layer 210 and the second circuit pattern 220 of the second substrate 200.

[0111] The molding layer 360 can be EMC (Epoxy Molding Compound), but is not limited thereto.

[0112] The mold layer 360 can have a low dielectric constant in order to improve the heat dissipation characteristics. For example, the dielectric constant (Dk) of the mold layer 360 can be 0.2 to 10. For example, the dielectric constant (Dk) of the mold layer 360 can be 0.5 to 8. For example, the dielectric constant (Dk) of the mold layer 360 can be 0.8 to 5. Therefore, in this embodiment, the mold layer 360 has a low dielectric constant, thereby improving the heat dissipation characteristics of the first device 340 and the second device 350.

[0113] In addition, the semiconductor package includes a plurality of connection members. For example, the semiconductor package includes a first connection member 330 disposed on the first pad 123 of the first circuit pattern 120 .

[0114] In addition, the semiconductor package may include a second connection member 310 disposed on the second pad 121 of the first circuit pattern 120 .

[0115] In addition, the semiconductor package may include a third connection member 320 disposed on the third pad 122 of the first circuit pattern 120 .

[0116] The first to third connection parts 310, 320 and 330 may include a spherical shape. For example, the cross-section of the first to third connection parts 310, 320 and 330 may include a circular or semicircular shape. For example, the cross-section of the first to third connection parts 310, 320 and 330 may include a partial or full circular shape. The cross-sectional shape of the first to third connection parts 310, 320, 330 may be flat on one side and curved on the other side. The first to third connection parts 310, 320, 330 may be solder balls, but are not limited thereto.

[0117] In contrast, the first to third connection parts 310, 320, 330 may have a hexahedral shape. For example, the cross-section of the first to third connection parts 310, 320, 330 may include a square. The cross-section of the first to third connection parts 310, 320, 330 may include a rectangle or a square.

[0118] Meanwhile, referring to FIGS. 3A to 3C , the second circuit pattern 220 may mean coil pattern layers respectively disposed on surfaces of a plurality of insulation layers.

[0119] Figure 3a (a) is a plan view showing a first embodiment of the first pattern layer 221, and Figure 3a (b) is a plan view showing a second embodiment of the first pattern layer 221 .

[0120] The first pattern layer 221 of the first embodiment may include a plurality of rectangular patterns spaced apart from each other, such as Figure 3a (a) shown.

[0121] Different from this, the first pattern layer 221 of the second embodiment may have a coil shape.

[0122] Meanwhile, the first pattern layer 221 may be connected to the lower second pattern layer 222 through the second through electrode 230. The first pattern layer 221 may include a pad 221P. In addition, the chip 400 may be mounted on the pad 221P of the first pattern layer 221. The chip 400 may be a multilayer ceramic capacitor (MLCC), but is not limited thereto.

[0123] at the same time, Figure 3b (a) illustrates a second pattern layer 222 of the first embodiment connected to a first pattern layer 221 of the first embodiment, and Figure 3b (b) illustrates the second pattern layer 222 of the second embodiment connected to the first pattern layer 221 of the second embodiment.

[0124] The second pattern layer 222 is disposed on the lower surface of the second-first insulating layer 211 or the upper surface of the second-second insulating layer 212. The second pattern layer 222 has a coil shape. For example, the second pattern layer 222 may include a pattern bent multiple times in one direction on the lower surface of the second-first insulating layer 211 or the upper surface of the second-second insulating layer 212. The second pattern layer 222 may be connected to the first pattern layer 221 and the third pattern layer 223 through the through electrode 230.

[0125] at the same time, Figure 3c (a) illustrates the third pattern layer 223 of the first embodiment, which is connected to the first pattern layer 221 and the second pattern layer 222 of the first embodiment, and Figure 3c (b) illustrates the third pattern layer 223 of the second embodiment, which is connected to the first pattern layer 221 and the second pattern layer 222 of the second embodiment.

[0126] The third pattern layer 223 is disposed on the lower surface of the second-second insulating layer 212. The third pattern layer 223 may include a pad part connected to the first connection part 330. The third pattern layer 223 has a coil shape. For example, the third pattern layer may include a pattern bent multiple times in one direction on the lower surface of the second-second insulating layer 212. The third pattern layer 223 can be connected to the first pattern layer 221 and the second pattern layer 222 through the through electrode 230.

[0127] Hereinafter, the second substrate 200 will be described in detail.

[0128] Figure 4 is a diagram showing a specific layer structure of a second substrate according to the first embodiment, Figure 5 is a diagram showing a specific layer structure of a second substrate according to a second embodiment, Figure 6 is a diagram showing a specific layer structure of a second substrate according to a third embodiment, and Figure 7 is a diagram showing a specific layer structure of a second substrate according to a fourth embodiment.

[0129] refer to Figure 4 The second insulating layer 210 of the second substrate 200 includes a second-first insulating layer 211 and a second-second insulating layer 212 .

[0130] In addition, the second circuit pattern 220 of the second substrate 200 includes a first pattern layer 221 disposed on the upper surface of the second-first insulating layer 211. In addition, the second circuit pattern 220 includes a second pattern layer 222 disposed between the lower surface of the second-first insulating layer 211 and the upper surface of the second-second insulating layer 212. In addition, the second circuit pattern 220 includes a third pattern layer 223 disposed on the lower surface of the second-second insulating layer 212.

[0131] Each of the first pattern layer 221 , the second pattern layer 222 , and the third pattern layer 223 may be a coil pattern forming a specific inductance.

[0132] The first pattern layer 221 , the second pattern layer 222 , and the third pattern layer 223 are disposed on the second insulating layer 210 , and are connected to each other through the second through-electrode 230 to form a specific inductance.

[0133] The inductance formed by the first pattern layer 221, the second pattern layer 222, and the third pattern layer 223 can be determined by the dielectric constant (Dk) of the second insulating layer 210, the distance (δ1, δ2) between circuit patterns disposed in different layers, and the cross-sectional area and length of each pattern layer.

[0134] The first pattern layer 221, the second pattern layer 222 and the third pattern layer 223 can have the same thickness (t1, t2, t3). In addition, the distance (δ1) between the first pattern layer 221 and the second pattern layer 222 and the distance (δ2) between the second pattern layer 222 and the third pattern layer 223 can also be the same.

[0135] to this end, Figure 4 The second substrate shown can be an inductor substrate, which functions as an inductor having a single inductance.

[0136] refer to Figure 5 , the second substrate of the second embodiment includes a second-first insulating layer 211a and a second-second insulating layer 212a. In addition, the second substrate of the second embodiment includes a first pattern layer 221a, which is disposed on the upper surface of the second-first insulating layer 211a. In addition, the second substrate of the second embodiment includes a second pattern layer 222a disposed between the lower surface of the second-first insulating layer 211a and the upper surface of the second-second insulating layer 212a. In addition, the second substrate of the second embodiment includes a third pattern layer 223a disposed on the lower surface of the second-second insulating layer 212a.

[0137] At this time, the first pattern layer 221 and the third pattern layer 223 of the first embodiment have structures protruding from the upper surface of the second-first insulating layer 211 and the lower surface of the second-second insulating layer 212, respectively.

[0138] Different from this, the first pattern layer 221a and the third pattern layer 223a of the second embodiment may have a structure embedded in the upper surface of the second-first insulating layer 211a and the lower surface of the second-second insulating layer 212a.

[0139] To this end, the second-first insulating layer 211a and the second-second insulating layer 212a of the second embodiment may include a photocurable resin or a photosensitive resin. For example, the second-first insulating layer 211a and the second-second insulating layer 212a may be formed of a PID (Photo Imageable Dielectric) material.

[0140] To this end, the second-first insulating layer 211a and the second-second insulating layer 212a may include epoxy resin, photoinitiator, silicon-based filler (Si filler), curing agent, etc. For example, the second-first insulating layer 211a and the second-second insulating layer 212a may be formed by laminating a photocurable resin film or coating a photocurable resin paste or liquid. At this time, in one example, the photocurable resin material may include at least one selected from photocurable polyhydroxystyrene (PHS), photocurable polybenzoxazole (PBO), photocurable polyimide (PI), photocurable benzocyclobutene (BCB), photocurable polysiloxane, photocurable epoxy resin, and phenolic resin.

[0141] Thus, the embodiment forms pattern grooves (not shown) at the upper and lower surfaces of the second-first insulating layer 211a and the second-second insulating layer 212a, respectively. In addition, the embodiment allows the first pattern layer 221 and the third pattern layer 223 to be embedded in the formed pattern grooves.

[0142] refer to Figure 6 , the second substrate of the third embodiment may be an inductor substrate having a plurality of inductors.

[0143] The second substrate of the third embodiment includes a second-first insulating layer 211b and a second-second insulating layer 212b. In addition, the second substrate of the third embodiment includes a first pattern layer 221b disposed on the upper surface of the second-first insulating layer 211b. In addition, the second substrate of the third embodiment includes a second pattern layer 222b disposed between the lower surface of the second-first insulating layer 211b and the upper surface of the second-second insulating layer 212b. In addition, the second substrate of the third embodiment includes a third pattern layer 223b disposed on the lower surface of the second-second insulating layer 212b.

[0144] At this time, the first pattern layer 221b may include a plurality of coil patterns.

[0145] The first pattern layer 221b includes a first coil pattern 221b1. In addition, the first pattern layer 221b includes a second coil pattern 221b2.

[0146] The first coil pattern 221 b 1 and the second coil pattern 221 b 2 may have different arrangement structures.

[0147] For example, the first coil pattern 221b1 may have a structure embedded in the upper surface of the second-first insulating layer 211b. In addition, the second coil pattern 221b2 may have a structure protruding on the upper surface of the second-first insulating layer 211b.

[0148] Therefore, in the second substrate of the third embodiment, a first spacing distance (δ1) between the first coil pattern 221 b 1 and the second pattern layer 222 b may be different from a second spacing distance (δ2) between the second coil pattern 221 b 2 and the second pattern layer 222 b .

[0149] The second spacing distance (δ2) may be greater than the first spacing distance (δ1). For example, the second spacing distance (δ2) may be greater than the first spacing distance (δ1) by the thickness of the first coil pattern 221 b 1.

[0150] Therefore, in the second substrate of the third embodiment, the first coil pattern 221b1 and the second pattern layer 222b can form a first inductor. In addition, the second coil pattern 221b2 and the second pattern layer 222b can form a second inductor different from the first inductor.

[0151] refer to Figure 7 , the second substrate of the fourth embodiment may be an inductor substrate having a plurality of inductors.

[0152] The second substrate of the fourth embodiment includes a second-first insulating layer 211c and a second-second insulating layer 212c. In addition, the second substrate of the fourth embodiment includes a first pattern layer 221c disposed on the upper surface of the second-first insulating layer 211c. In addition, the second substrate of the fourth embodiment includes a second pattern layer 222c disposed between the lower surface of the second-first insulating layer 211c and the upper surface of the second-second insulating layer 212c. In addition, the second substrate of the fourth embodiment includes a third pattern layer 223c disposed on the lower surface of the second-second insulating layer 212c.

[0153] At this time, the first pattern layer 221c may include a plurality of coil patterns.

[0154] The first pattern layer 221c may include a first coil pattern 221c1, a second coil pattern 221c2, a third coil pattern 221c3, and a fourth coil pattern 221c4.

[0155] In addition, the fourth embodiment allows the first coil pattern 221c1, the second coil pattern 221c2, the third coil pattern 221c3, and the fourth coil pattern 221c4 to form different inductances.

[0156] The first coil pattern 221c1 and the second pattern layer 222c may have a first spacing distance (δ1). In addition, the second coil pattern 221c2 and the second pattern layer 222c may have a second spacing distance (δ2). In addition, the third coil pattern 221c3 and the second pattern layer 222c may have a third spacing distance (δ3). In addition, the fourth coil pattern 221c4 and the second pattern layer 222c may have a fourth spacing distance (δ4).

[0157] The first coil pattern 221c1, the second coil pattern 221c2, and the third coil pattern 221c3 may have a structure embedded in the upper surface of the second-first insulating layer 211c. In addition, the fourth coil pattern 221c4 may have a structure protruding from the upper surface of the second-first insulating layer 211c.

[0158] At this time, a plurality of grooves having different depths can be formed at the upper surface of the second-first insulating layer 211c. In addition, the first coil pattern 221c1, the second coil pattern 221c2, and the third coil pattern 221c3 can be disposed in each groove having different depths.

[0159] Therefore, an embodiment may be implemented such that the first to fourth spacing distances (δ1, δ2, δ3, δ4) have different values.

[0160] The semiconductor package of the embodiment includes a first substrate and a second substrate. In addition, the semiconductor package includes at least one device mounted on the first substrate. In addition, the second substrate is mounted on the first substrate and can perform an inductor function or a capacitor function.

[0161] Specifically, the embodiment configures one of the inductor and the capacitor as a core-type device, and configures the other of the inductor and the capacitor as a substrate-type device. Therefore, the embodiment can ensure the design space of the semiconductor package, and thereby ensure the degree of freedom of design. In addition, the embodiment implements different types of inductors and capacitors to solve reliability problems that may occur between the inductor and the capacitor. For example, when the inductor and the capacitor are arranged adjacent to each other, there may be a problem of degradation of the characteristics of each function due to interference therebetween. Therefore, the embodiment implements different types of inductors and capacitors, and can solve the problem of degradation of the characteristics of each function. In addition, the embodiment can maximize the characteristics of the inductor function and the capacitor function, thereby further improving product reliability.

[0162] In addition, embodiments include a plurality of inductors or a plurality of capacitors. In addition, one of the plurality of inductors is configured as a core-type device, and another of the plurality of inductors is configured as a substrate-type device. In addition, in embodiments, one of the plurality of capacitors is configured as a core-type device, and another of the plurality of capacitors is configured as a substrate-type device.

[0163] Therefore, the embodiments can further maximize the inductor function or the capacitor function and thereby further improve product performance.

[0164] In addition, the second substrate of the embodiment includes a second insulating layer, which includes a photosensitive material. In addition, the pattern layer of the second substrate is inserted into the groove of the second insulating layer or has a protruding structure. In addition, the groove of the second insulating layer can include a plurality of grooves with different depths, and the pattern layer can be respectively arranged in the plurality of grooves. Through this, the embodiment can realize a plurality of inductors in one second substrate. Therefore, the embodiment can further improve product performance.

[0165] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. In addition, the characteristics, structures, and effects described in each embodiment can be combined or modified for other embodiments by those skilled in the art to which the embodiments belong. Therefore, the contents related to such combinations and changes should be interpreted as being included in the scope of the embodiments.

[0166] In the above, the embodiment is mainly described, but this is only an example and does not limit the embodiment, and the ordinary technicians in the field to which the embodiment belongs will appreciate that various modifications and applications not described above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiment can be implemented by modification. In addition, the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiment proposed in the appended claims.

Claims

1. A semiconductor package, comprising: A first substrate, the first substrate comprising a first pad and a second pad; a first connecting member, the first connecting member being disposed on the first pad of the first substrate; a second substrate coupled to the first connecting member; a second connecting member, the second connecting member being disposed on the second pad of the first substrate; a device mounted on the second connecting member; as well as a molding layer disposed on the first substrate and molding the device, wherein the device comprises one of a capacitor and an inductor, and Wherein, the second substrate includes a pattern layer having a function different from that of the device.

2. The semiconductor package according to claim 1, wherein The second substrate comprises: a second insulating layer; a second circuit pattern disposed on the second insulating layer and corresponding to the pattern layer; and A second through electrode is provided, wherein the second through electrode penetrates the second insulating layer.

3. The semiconductor package according to claim 2, wherein: The second substrate further includes a second protective layer disposed at the upper surface and the lower surface of the second insulating layer, and The molding layer molds the device at a position spaced apart from the second substrate.

4. The semiconductor package according to claim 1, wherein: The molding layer molds the second circuit pattern and the second insulating layer of the second substrate.

5. The semiconductor package according to claim 1, wherein The second substrate is an inductor substrate including a coil pattern forming an inductor, and Wherein, the device comprises: a first device, the first device corresponding to a capacitor; and The second component is spaced apart from the first component and corresponds to an inductor.

6. The semiconductor package according to claim 1, wherein The second substrate is a capacitor substrate including a capacitor pattern forming a capacitor, and Wherein, the device comprises: a first device, the first device corresponding to a capacitor; and The second component is spaced apart from the first component and corresponds to an inductor.

7. The semiconductor package according to claim 2, wherein: The second circuit pattern includes: a first pattern layer, the first pattern layer is arranged on the upper surface of the second insulating layer; and a second pattern layer, the second pattern layer is arranged on the lower surface of the second insulating layer. Wherein, the first pattern layer includes a plurality of coil patterns, and The plurality of coil patterns include a first coil pattern having a first spacing distance from the second pattern layer, and a second coil pattern having a second spacing distance from the second pattern layer that is different from the first spacing distance.

8. The semiconductor package according to claim 7, wherein: The first coil pattern is disposed in a pattern groove formed at an upper surface of the second insulating layer, and The second coil pattern protrudes on an upper surface of the second insulating layer.

9. The semiconductor package according to claim 7, wherein: The first coil pattern is disposed in a first groove having a first depth formed at an upper surface of the second insulating layer, and The second coil pattern is disposed in a second groove formed at an upper surface of the second insulating layer and having a second depth different from the first depth.

10. The semiconductor package according to any one of claims 7 to 9, wherein: The second insulating layer includes PID (Photo Imageable Dielectric Resin).

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