Testing device and method for quantum chip

Abstract

The invention provides a quantum chip testing device and method. The quantum chip testing device comprises a wire binding plate and a testing plate detachably connected with the wire binding plate. The wire binding board comprises a first connecting structure, the test board comprises a second connecting structure matched with the first connecting structure, and when the first connecting structure and the second connecting structure are connected together, communication connection between the wire binding board and the test board is achieved. According to the quantum chip testing device, the testing plate and the wire binding plate are separated, and a quantum chip testing solution suitable for wire binding packaging from normal temperature to ultralow temperature is realized through a plug-in type or clamping type design, so that a plurality of chips can be tested at the same time in an ultralow temperature environment, the loss of the chips caused by welding is reduced, and the service life of the chips is prolonged. The test board can be flexibly inserted, pulled or clamped, convenient operation and repeated utilization of the test board are realized, the test board is compatible with different test instruments, the efficiency is improved, the cost is reduced, and the expandability is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a testing device and method for a quantum chip. Background Art

[0002] After the preparation of quantum chips, the parameters and performance of quantum chips need to be tested to ensure the quality of quantum chips. The existing chip test uses a wire binding process to connect the internal circuit of the chip with the gold-plated copper foil of the test circuit board with gold wire or aluminum wire, cover the wire with black glue for isolation protection, and then test the chip through the test circuit board. However, quantum chips need to be in an ultra-low temperature environment (as low as 10mK, about -273℃) to maintain the quantum state, and the measurement and control circuit of the quantum bit or other surrounding circuits need to be set in an ultra-low temperature environment with different temperatures. Compared with chip testing for conventional consumer electronics, ultra-low temperature chip testing for quantum computing is more stringent in the temperature field, and the ultra-low temperature environment brings challenges to instruments, packaging methods, and test hardware. Therefore, the traditional wire binding process cannot meet the testing of quantum chips. In addition, since the existing test device is a disposable wire binding board, the test board is fixed on the wire binding board, and the entire wire binding board must be replaced for each test, which increases the test cost. Therefore, how to achieve convenient and practical quantum chip testing in an ultra-low temperature environment is a technical problem currently faced.

[0003] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present application provides a quantum chip testing device and method, which separates the test board and the wire binding board, and through a plug-in or snap-in design, realizes a quantum chip testing solution for wire binding packaging suitable for room temperature to ultra-low temperature. It can not only realize the simultaneous testing of multiple chips in an ultra-low temperature environment and reduce the loss of chips caused by welding, but also can be flexibly plugged or snap-in to achieve convenient operation and reuse of the test board, and is compatible with different test instruments, thereby improving efficiency, reducing costs, and improving scalability.

[0005] This application is implemented through the following technical solutions:

[0006] A first aspect of the present application is to provide a quantum chip testing device, comprising a wire binding plate and a testing plate detachably connected to the wire binding plate;

[0007] Specifically, the wire binding board includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure. When the first connection structure is connected with the second connection structure, the communication connection between the wire binding board and the test board is achieved.

[0008] Specifically, the first connection structure is a plug structure, and the second connection structure is a slot structure that can accommodate the plug and is compatible with the plug.

[0009] Specifically, the second connection structure is the plug structure, and the first connection structure is the slot structure that can accommodate the plug structure and is adapted to the plug structure.

[0010] Specifically, the wire binding plate further includes a chip fixing area for fixing the chip, and there is a gap between the chip fixing area and the first connection structure to facilitate binding of the chip, and the chip is fixed to the chip fixing area by a wire binding process.

[0011] Specifically, the wire binding plate also includes a first wire, which is respectively connected between the first connection structure and the chip fixing area to provide a communication connection between the quantum chip and the first connection structure to achieve signal transmission.

[0012] Specifically, the test board further includes: a second wire and an interface; the interface includes a microwave high-frequency interface, a flat cable interface, and a micro-device interface, which is used to provide devices suitable for different test scenarios. The two ends of the second wire are respectively connected to the interface and the second connection structure, which are used to provide a communication connection between the interface and the second connection structure to realize the transmission of the signal.

[0013] Specifically, the test board also includes a functional module for improving the performance of the test device according to the test requirements; the functional module includes one or more electrostatic discharge modules, a line conversion module and an analog-to-digital conversion module. The electrostatic discharge module is used to prevent static electricity and improve the robustness of the test board; the multiplexing module is used to control the line of the signal transmission; and the analog-to-digital conversion module is used to convert the analog signal into a digital signal.

[0014] Specifically, the quantum chip testing device of the present application further includes a quantum computer, a testing module and a third wire; the testing module and the quantum computer are respectively connected to the testing board through the third wire to achieve the transmission of the signal. The testing module is connected to the quantum computer to achieve the transmission of the signal.

[0015] Specifically, the test module includes a parsing unit, a signal generating unit and a signal processing unit. The parsing unit is used to receive a test instruction and send it to the signal generating unit; the signal generating unit receives the test instruction to generate a pulse signal and sends it to the test board; the signal processing unit receives the result signal returned by the chip for analysis and sends it to the quantum computer.

[0016] The test board also includes a functional module for improving the performance of the test device according to test requirements; the functional module includes one or more electrostatic release modules, a line conversion module and an analog-to-digital conversion module; the electrostatic release module is respectively connected to the interface and the quantum computer through the third wire to prevent static electricity and improve the robustness of the test board; the multiplexing module is respectively connected to the interface and the quantum computer through the third wire to control the signal transmission line during the test of multiple chips; the analog-to-digital conversion module is respectively connected to the interface and the quantum computer through the third wire to convert the analog signal emitted by the quantum computer into a digital signal.

[0017] A second aspect of the present application is to provide a method for testing a quantum chip, comprising: performing testing using the quantum chip testing device as described above.

[0018] Compared with the prior art, the present application mainly has the following beneficial effects: Compared with the prior art, the quantum chip testing device of the present application has the following advantages:

[0019] (1) Low cost: In the prior art, the wire binding board and the test board are integrated, and the test board cannot be reused. However, the present application uses a flexible plug-in or clamping structure to set the wire binding board as a disposable consumable, so that the test board can be reused, thereby reducing the cost of the test board and its interface and functional modules.

[0020] (2) High compatibility and expandability: Ultra-low temperature test devices with different cooling capabilities or chip tests of different application types correspond to different interfaces. The separate design of the wire binding board and the test board in this application uses the wire binding board as a consumable and the test board as a reusable test platform. As a result, the original test board, which is limited by cost, can be equipped with more different test interfaces and can adopt a higher level of welding technology. In addition, test systems such as digitally controlled multiplexers, analog-to-digital converters, and digital signal processing modules can be added to make an expandable multi-purpose test board with complete packaging, high compatibility, and powerful testing capabilities, which is more suitable for different chips, test instruments, or test environments.

[0021] (3) High test efficiency and reliability: The application of the plug-in structure or the clamping structure of the present application simplifies the connection method between the chip sample and the test equipment. When conducting multi-sample testing, the sample can be replaced only through the adaptive connection of the first connection structure and the second connection structure. By designing the internal circuit interface of the chip and the position of the chip fixing area of ​​the binding board in advance, multiple samples can be replaced by plugging or clamping without changing the remaining wiring, which greatly reduces the test difficulty and significantly improves the test efficiency in ultra-low temperature chip testing with a long test cycle. In addition, the same test instrument can correspond to a set of the same test board. The universal plug-in or clamping structure unifies the signal path between different samples to a high degree. By designing the wires on the test board and selecting the interface specifications and types, the test conditions can be made more rigorous, avoiding signal loss or errors caused by different path interfaces and additional adapter boards, and improving the reliability of the data obtained from the chip test. In addition, when testing in an ultra-low temperature environment, by connecting multiple test boards at a time and placing them in an ultra-low temperature environment, the performance of the chips on multiple test boards can be tested simultaneously, avoiding the long waiting time for heating and cooling in the prior art. Therefore, the present application can improve the testing efficiency of quantum chips in ultra-low temperature environments.

[0022] (4) Scientificity, basic nature, and rich application prospects: This application improves the disadvantages of low-cost wire binding packaging that are not conducive to integration and transfer operations by separating the wire binding board and the test board, and enhances the compatibility of the test board. As a basic design, adding additional equipment or expansion modules can extend the design to different test application directions and achieve good conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 This is a structural diagram of a quantum chip testing device according to an embodiment of the present application.

[0025] Figure 2 A schematic diagram of a test board connected to multiple wire binding boards according to an embodiment of the present application.

[0026] Figure 3 A schematic diagram of signal transmission of a quantum chip testing device according to an embodiment of the present application.

[0027] Figure 4It is a flow chart of a method for testing a quantum chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the implementation methods of this application to clearly and completely describe the technical solutions in the implementation methods of this application. Obviously, the described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] It should be understood that the terms used in this specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. As used in the specification of the embodiments of the present application and the appended claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0031] After the preparation of quantum chips, the parameters and performance of quantum chips need to be tested to ensure the quality of quantum chips. The existing chip test uses a wire binding process to connect the internal circuit of the chip with the gold-plated copper foil of the test circuit board with gold wire or aluminum wire, cover the wire with black glue for isolation protection, and then test the chip through the test circuit board. However, quantum chips need to be in an ultra-low temperature environment (as low as 10mK, about -273℃) to maintain the quantum state, and the measurement and control circuit of the quantum bit or other surrounding circuits need to be set in an ultra-low temperature environment with different temperatures. Compared with chip testing for conventional consumer electronics, ultra-low temperature chip testing for quantum computing is more stringent in the temperature field, and the ultra-low temperature environment brings challenges to instruments, packaging methods, and test hardware. Therefore, the traditional wire binding process cannot meet the testing of quantum chips. In addition, since the existing test device is a disposable wire binding board, the test board is fixed on the wire binding board, and the entire wire binding board must be replaced for each test, which increases the test cost. Therefore, how to achieve convenient and practical quantum chip testing in an ultra-low temperature environment is a technical problem currently faced.

[0032] In view of the above-mentioned deficiencies in the prior art, the present application provides a quantum chip testing device and method, which separates the test board and the wire binding board, and through a plug-in design, realizes a quantum chip testing solution for wire binding packaging suitable for room temperature to ultra-low temperature. It can not only realize testing in ultra-low temperature environments and reduce the loss of chips caused by welding, but also can be flexibly plugged and unplugged to achieve convenient operation and reuse of test boards. It is compatible with different testing instruments and can test multiple quantum chips at a time, thereby improving efficiency and reducing costs.

[0033] like Figure 1 As shown, the first aspect of the present application is to provide a testing device for a quantum chip, including a wire binding board 10 , a testing board 20 , a testing module 30 and a quantum computer 40 .

[0034] Among them, the wire binding plate 10 and the test board 20 are separated from each other but detachably connected, the wire binding plate 10 includes a first connecting structure 11, and the test board 20 includes a second connecting structure 21 adapted to the first connecting structure 11; when the first connecting structure and the second connecting structure are connected together, the communication connection between the wire binding plate and the test board is realized.

[0035] The first connection structure 11 and the second connection structure 21 are snap-connected to achieve communication connection between the wire binding board 10 and the test board 20 .

[0036] Specifically, the first connection structure 11 and the second connection structure 21 are plug-in connections, and the communication connection between the wire binding board 10 and the test board 20 is realized by plugging the first connection structure 11 and the second connection structure 21. Optionally, the first connection structure 11 is a plug structure, and the second connection structure 21 is a slot structure that can accommodate the plug and is compatible with the plug. Specifically, one test board 20 can be connected to multiple wire binding boards 10, such as Figure 2 As shown, the second connection structure 21 of the test board 20 is a slot structure, and the first connection structure 11 of the wire binding board 10 is a plug structure. When the plug is inserted into the slot, the circuit connection between the wire binding board and the test board can be realized. When the plug is pulled out of the slot, the wire binding board 10 and the test board 20 can be separated. Such a design is convenient for plugging and unplugging. Each test only requires replacing a different wire binding board 10 for fixing the chip. The test board can be reused, which is beneficial to saving testing costs. At the same time, since in a conventional test device in which the wire binding board and the test board are fixed together, replacing the chip requires disassembling the wire binding and re-soldering the chip, which may damage the chip in the process and cause additional losses. The plug-in design of the present application can avoid multiple wire binding packages and reduce the loss of the chip. The wire binding board is disposable and the test board can be reused many times.

[0037] Optionally, the first connection structure 11 can be designed as a slot structure, and the second connection structure 21 can be designed as a plug structure, which can also realize the function of plug-in connection. However, the disadvantage is that since the volume of the slot is larger than the plug, if the slot is installed on the wire binding board 10, the thickness of the slot may affect the binding of the chip.

[0038] Optionally, a test board can be provided with multiple second connection structures 21 for connecting multiple wire binding boards to realize the function of simultaneously testing the performance of multiple quantum chips. Since quantum chips need to maintain quantum states in an environment of -273°C, when testing the performance of quantum chips, the chips need to be placed inside a refrigerator, and it takes about 3 hours to drop from room temperature to ultra-low temperature. After the test is completed, the chip can only be taken out when it is heated to room temperature, which also takes about 3 hours. Therefore, each test spends a lot of time waiting for the temperature to rise and fall. Moreover, the sample to be tested is placed in the refrigerator, and it cannot be operated during the entire test process, nor can changes in the appearance of the sample be observed. Through this device, the wire binding board 10 and the test board 20 are independent structures, and the wire binding board can be connected and removed at any time through a plug-in connection, and multiple wire binding boards 10 can be connected to a test board 20, and a chip is placed on each wire binding board 10. Multiple chips can be tested at the same time, and multiple test schemes can be implemented without repeated heating and cooling, thereby improving test efficiency.

[0039] Specifically, Figure 1 As shown, the wire binding board 10 also includes a chip fixing area 12 and a first wire 13. The chip fixing area is used to fix the chip. There is a gap between the chip fixing area 12 and the first connection structure 11 to facilitate binding the chip. Preferably, the main body of the wire binding board 10 is a square, the center of the chip fixing area 12 coincides with the center of the wire binding board, the first connection structure 11 is located on one side of the square and protrudes toward the test board 20, and the protruding plug is adapted to the size of the groove of the second connection structure 21.

[0040] The chip is fixed on the chip fixing area by a bonding process, specifically, the internal circuit of the chip is connected to the gold-plated copper foil (gold finger) area (not shown in the figure) of the bonding board 10 with gold wire or aluminum wire, and covered with black glue for isolation and protection after bonding. The first wire 13 is respectively connected between the first connection structure 11 and the chip fixing area 12 to provide a communication connection between the quantum chip and the first connection structure 11 to realize signal transmission. The first wire 13 can be directly printed on the bonding board 10.

[0041] Preferably, an interface (not shown) may be provided on the wire binding board 10 , and the interface may be connected to a testing instrument via a wire, so that the performance test of the chip fixed on the wire binding board 10 may be realized.

[0042] Specifically, the test board 20 further includes an interface 22 , a functional module 23 and a second wire 24 .

[0043] Specifically, the two ends of the second wire are respectively connected to the interface 22 and the second connection structure 21, which are used to provide a communication connection between the interface 22 and the second connection structure 21 to realize the transmission of the signal. Specifically, the interface 22 is connected to the test module 30 through a third wire, and receives a signal from the test module 30. The signal sent by the test module 30 passes through the third wire 31, the interface 22, the second wire 24, the second connection structure 21, the first connection structure 11 and the first wire 13 in sequence, and is transmitted to the quantum chip fixed in the chip fixing area 12. The response signal generated by the quantum chip to the signal is then reversely transmitted to the test module 30, thereby realizing the signal closed loop during the performance test. Different interface types can be set according to the test requirements. Preferably, the interface includes microwave high-frequency interface (SMA interface), 60-way cable interface, WeChat device interface (such as 15-pin Micro D interface) and other types. The SMA interface can adapt to different test scenarios and has a high signal transmission speed. The 15-pin Micro D interface has 15 signal transmission channels, a small size, and many channels.

[0044] The functional module 23 is connected to the quantum computer 40 through the third wire 31, and is used to set different performances of the test device according to the test requirements; the functional module includes one or more electrostatic discharge modules (ESD), line conversion modules and analog-to-digital conversion modules connected in parallel. The electrostatic discharge module is connected to the interface and the quantum computer respectively through the third wire, which can prevent static electricity and improve the robustness of the test board. The multiplexing module is connected to the interface and the quantum computer respectively through the third wire, and is used to control the line of the signal transmission when testing multiple chips, especially when multiple chips are tested at the same time, for controlling the transmission line of the signal, connecting multiple binding boards with chips to the test board at one time, and controlling the signals sent to different chips through the multiplexing module, and receiving the result signals from different chips, and transmitting them to the quantum computer, so as to realize the performance of multiple chips tested at one time, and avoid the steps of repeatedly installing the connection test board and the binding board. In particular, in the prior art, when testing quantum chips in a low temperature or even ultra-low temperature test environment, the cooling and heating process of the refrigerator takes a long time. By using the plug-in connection test board and wire binding board of the present application, multiple wire binding boards can be connected at one time, which can avoid waiting for the temperature to drop to an ultra-low temperature environment before testing the replacement chip, and also avoid waiting for the temperature to rise to room temperature after the test is completed, thereby improving the test efficiency. The analog-to-digital conversion module (ADC) is used to convert analog signals into digital signals. There can also be other types of functional modules.

[0045] In addition, when the refrigerator is cooling, it has temperature zones inside. Only at the bottom of the cold finger is there an ultra-low temperature (4K) environment that meets the requirements for quantum chip performance testing. Since the refrigerator is a vacuum environment and a vacuum does not conduct heat, in order to make the temperature of the sample to be tested reach an ultra-low temperature, it is necessary to select materials with good thermal conductivity so that the wire binding plate and the cold finger are in full contact to ensure that the sample to be tested is at an ultra-low temperature.

[0046] Optionally, the wire binding board 10 and the test board 20 are PCB boards, and the circuit can be directly printed on the PCB board. Therefore, the first wire 13 can be directly printed on the wire binding board 10, and the second wire 24 can be directly printed on the test board 20.

[0047] like Figure 3 As shown, the test module 30 is a different type of test instrument, including a parsing unit 32, a signal generating unit 33 and a signal processing unit 34. The quantum computer includes an interface terminal 41. After the chip is bound to the wire binding board 10 and the wire binding board 10 is connected to the test board, the signal transmission process during the test is as follows: a control instruction is sent to the test module 30 through the interface terminal of the quantum computer 40, the parsing unit 32 of the test module 30 analyzes the instruction and sends it to the signal generating unit 33, the signal generating unit 33 generates a pulse signal and sends it to the test board 20, the test board 20 sends the signal to the chip on the wire binding board 10, and then returns the result signal from the chip to the test board 20, and then transmits it to the signal processing unit 34 of the test module, the signal processing unit analyzes the result signal and sends it to the interface terminal, so that the test result information can be displayed on the quantum computer 40. At the same time, the interface terminal 41 on the quantum computer 40 can also directly control the test board 20, specifically to control the functional module 23 on the test board 20, such as Figure 1 As shown in FIG. , the quantum computer 40 is connected to the functional module 23 via a third wire, so that line switching can be controlled.

[0048] Preferably, the test module is a test instrument, which can be selected according to actual test requirements, and the quantum computer can also be replaced by a numerical control system.

[0049] The first connection structure and the second connection structure of the present application can also be set as detachable and mutually adaptable clamping structures, and the clamping structures can also provide communication connections, so as to realize flexible connection between the test board and the wire binding board.

[0050] Compared with the prior art, the quantum chip testing device of the present application has the following advantages:

[0051] (1) Low cost: In the prior art, the wire binding board and the test board are integrated, and the test board cannot be reused. However, the present application uses a flexible plug-in or clamping structure to set the wire binding board as a disposable consumable, so that the test board can be reused, thereby reducing the cost of the test board and its interface and functional modules.

[0052] (2) High compatibility and expandability: Ultra-low temperature test devices with different cooling capabilities or chip tests of different application types correspond to different interfaces. The separate design of the wire binding board and the test board in this application uses the wire binding board as a consumable and the test board as a reusable test platform. As a result, the original test board, which is limited by cost, can be equipped with more different test interfaces and can adopt a higher level of welding technology. In addition, test systems such as digitally controlled multiplexers, analog-to-digital converters, and digital signal processing modules can be added to make an expandable multi-purpose test board with complete packaging, high compatibility, and powerful testing capabilities, which is more suitable for different chips, test instruments, or test environments.

[0053] (3) High test efficiency and reliability: The application of the plug-in structure or the clamping structure of the present application simplifies the connection method between the chip sample and the test equipment. When conducting multi-sample testing, the sample can be replaced only through the adaptive connection of the first connection structure and the second connection structure. By designing the internal circuit interface of the chip and the position of the chip fixing area of ​​the binding board in advance, multiple samples can be replaced by plugging or clamping without changing the remaining wiring, which greatly reduces the test difficulty and significantly improves the test efficiency in ultra-low temperature chip testing with a long test cycle. In addition, the same test instrument can correspond to a set of the same test board. The universal plug-in or clamping structure unifies the signal path between different samples to a high degree. By designing the wires on the test board and selecting the interface specifications and types, the test conditions can be made more rigorous, avoiding signal loss or errors caused by different path interfaces and additional adapter boards, and improving the reliability of the data obtained from the chip test. In addition, when testing in an ultra-low temperature environment, by connecting multiple test boards at a time and placing them in an ultra-low temperature environment, the performance of the chips on multiple test boards can be tested simultaneously, avoiding the long waiting time for heating and cooling in the prior art. Therefore, the present application can improve the testing efficiency of quantum chips in ultra-low temperature environments.

[0054] (4) Scientificity, basic nature, and rich application prospects: This application improves the disadvantages of low-cost wire binding packaging that are not conducive to integration and transfer operations by separating the wire binding board and the test board, and enhances the compatibility of the test board. As a basic design, adding additional equipment or expansion modules can extend the design to different test application directions and achieve good conversion.

[0055] The second aspect of the present application is to provide a quantum chip testing method, which is implemented using the above-mentioned quantum chip testing device, such as Figure 4 As shown, the specific steps include:

[0056] S1. Bind the quantum chip on the binding board, connect the binding board to the test board, and then connect the test board to the test module and quantum computer;

[0057] S2, placing the wire binding plate in a normal temperature or ultra-low temperature test environment;

[0058] S3, selecting a control circuit on the control interface of the quantum computer and sending an instruction;

[0059] S4. Record the result information on the control interface to complete the performance test.

[0060] Specifically, the specific process of converting instructions into result information involves the transmission and conversion of models in different components, specifically:

[0061] S5, the parsing unit parses the instruction and sends it to the signal generating unit, thereby generating a pulse signal, and sending it to the test board;

[0062] S6. The test board receives the pulse signal and sends it to the quantum chip on the wire binding board;

[0063] S7, the quantum chip generates a response signal according to the pulse signal and sends it to the test board, and the test board sends the response signal to the signal processing unit of the test module;

[0064] S8. The signal processing unit analyzes the response signal and sends the analysis result to the interface terminal, thereby completing the performance test.

[0065] In summary, the present application provides a test device for a quantum chip, including a wire binding board and a test board detachably connected to the wire binding board; the wire binding board includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure, and when the first connection structure is connected to the second connection structure, the communication connection between the wire binding board and the test board is realized. The test device for a quantum chip of the present application separates the test board from the wire binding board, and through a plug-in or snap-in design, realizes a quantum chip testing solution for wire binding packages suitable for room temperature to ultra-low temperature. It can not only realize the testing of multiple chips at the same time in an ultra-low temperature environment and reduce the loss of chips caused by welding, but also can be flexibly plugged in or snap-in to realize convenient operation and reuse of the test board, and is compatible with different test instruments, improves efficiency, reduces costs, and improves scalability.

[0066] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A quantum chip testing device, characterized in that: It includes a wire binding plate and a test plate detachably connected to the wire binding plate; The wire binding plate includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure. When the first connection structure is connected with the second connection structure, the communication connection between the wire binding plate and the test board is achieved.

2. A quantum chip testing device according to claim 1, characterized in that: The first connection structure and the second connection structure are plug-in connections, and plugging the first connection structure and the second connection structure together realizes the communication connection between the wire binding board and the test board.

3. A quantum chip testing device according to claim 2, characterized in that: The first connection structure is a plug structure, and the second connection structure is a slot structure that can accommodate the plug and adapt to the plug; or, the second connection structure is the plug structure, and the first connection structure is the slot structure that can accommodate the plug structure and adapt to the plug structure.

4. A quantum chip testing device according to claim 1, characterized in that: The wire binding plate further includes a chip fixing area for fixing the chip. There is a gap between the chip fixing area and the first connection structure to facilitate binding of the chip. The chip is fixed to the chip fixing area by a wire binding process.

5. A quantum chip testing device according to claim 4, characterized in that: The wire binding plate also includes a first wire, which is respectively connected between the first connection structure and the chip fixing area to provide a communication connection between the quantum chip and the first connection structure to achieve signal transmission.

6. A quantum chip testing device according to claim 5, characterized in that: The test board also includes: a second wire and an interface; The interfaces include microwave high-frequency interfaces, cable interfaces, and micro-device interfaces, which are used to provide devices suitable for different test scenarios; Two ends of the second wire are respectively connected to the interface and the second connection structure, and are used to provide a communication connection between the interface and the second connection structure to achieve transmission of the signal.

7. A quantum chip testing device according to claim 6, characterized in that: Also included are a quantum computer, a test module, and a third conductor; The test module and the quantum computer are respectively connected to the test board through the third wire to achieve transmission of the signal; The test module is communicatively connected to the quantum computer to achieve transmission of the signal.

8. A quantum chip testing device according to claim 7, characterized in that: The test module includes a parsing unit, a signal generating unit and a signal processing unit; The analysis unit is used to receive the test instruction and send it to the signal generation unit; The signal generating unit receives the test instruction to generate a pulse signal and sends it to the test board; The signal processing unit receives the result signal returned by the chip, analyzes it, and sends it to the quantum computer.

9. A quantum chip testing device according to claim 7, characterized in that: The test board also includes a functional module for improving the performance of the test device according to the test requirements; the functional module includes one or more electrostatic discharge modules, a line conversion module and an analog-to-digital conversion module; The electrostatic discharge module is connected to the interface and the quantum computer respectively through the third wire, so as to prevent static electricity and improve the robustness of the test board; The line conversion module is connected to the interface and the quantum computer respectively through the third wire, and is used to control the line of the signal transmission during the process of testing the plurality of chips; The analog-to-digital conversion module is connected to the interface and the quantum computer respectively through the third wire, and is used to convert the analog signal sent by the quantum computer into a digital signal.

10. A method for testing a quantum chip, characterized in that: include: The test is performed using a quantum chip testing device as described in any one of claims 1 to 9.

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