Array substrate and display panel

Abstract

The array substrate comprises a plurality of pixel units arranged in an array mode, the array substrate comprises a driving circuit layer, a first passivation layer, a first electrode layer, a second passivation layer and a second electrode layer, and the driving circuit layer, the first passivation layer, the first electrode layer, the second passivation layer and the second electrode layer are sequentially arranged on the surface of a substrate in a stacked mode and correspond to each pixel unit. The first electrode layer comprises a plurality of strip-shaped electrodes which are arranged in parallel at preset intervals, the second electrode layer covers the second passivation layer in a flat plate shape, and the orthographic projection of the first electrode layer on the substrate is located in the orthographic projection of the second electrode layer on the substrate. The first electrode layer and the second electrode layer are respectively arranged to respectively drive the display medium so as to control the pixel units to emit light rays with different brightness and different visual angles, so that compatible large-visual-angle and high-brightness display is realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of optoelectronic display technology and semiconductor manufacturing technology, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has become one of the mainstream display devices due to its advantages of lightness, energy saving, high display quality, and mature and stable manufacturing process. TFT-LCD has a variety of commonly used display modes, such as vertical alignment (VA) display, horizontal alignment (IPS) display, twisted alignment (TN) display, etc. Among them, the VA mode has better dark state performance and better contrast than other display modes, but its field of view angle is relatively poor. At present, multi-domain display is often used to improve the viewing angle of VA display, such as 4domain and 8domain. Among them, the multi-domain display method can make the human eye accumulate better and solve the problem of color deviation better, but due to the low overall brightness of the 4domain and 8domain panels, they are not compatible with high-brightness display. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present application provides an array substrate and a display panel that can effectively be compatible with a large viewing angle and high brightness.

[0004] The present application provides an array substrate, comprising a plurality of pixel units arranged in an array, wherein corresponding to each pixel unit, the array substrate comprises a driving circuit layer, a first passivation layer, a first electrode layer, a second passivation layer and a second electrode layer which are sequentially stacked on a surface of a base substrate, wherein the first electrode layer comprises a plurality of strip electrodes which are spaced at a preset distance and arranged parallel to each other, and the second electrode layer is arranged in a flat plate shape covering the second passivation layer, and an orthographic projection of the first electrode layer on the base substrate is located within an orthographic projection of the second electrode layer on the base substrate.

[0005] Optionally, the pixel unit includes a first pixel area and a second pixel area, the first electrode layer includes a first main electrode and a first sub-electrode, the first main electrode is arranged corresponding to the first pixel area, and is used to drive the first pixel area, the first sub-electrode is arranged corresponding to the second pixel area, and is used to drive the second pixel area, and the second electrode layer is arranged corresponding to the first pixel area and the second pixel area, and is used to simultaneously drive the first pixel area and the second pixel area.

[0006] Optionally, corresponding to the first pixel area, the driving circuit layer includes a first switch tube and a second switch tube, the first switch tube is connected in series with the second switch tube, the first switch tube is also electrically connected to the data input end and the first main electrode respectively, the second switch tube is also electrically connected to the second electrode layer, the first main electrode receives a data signal from the data input end through the first switch tube, and the second electrode layer receives a data signal from the data input end through the first switch tube and the second switch tube; corresponding to the second pixel area, the driving circuit layer also includes a third switch tube and a fourth switch tube, the third switch tube is connected in series with the fourth switch tube, the third switch tube is also electrically connected to the data input end and the first sub-electrode, and the first sub-electrode receives a data signal from the data input end through the third switch tube.

[0007] Optionally, the array substrate also includes multiple data lines and multiple scan lines, the pixel unit is arranged at the intersection of the data line and the scan line, the pixel unit is electrically connected to the data line and the scan line, and is used to receive a scan signal from the scan line and receive a data signal from the data line according to the scan signal; the control end of the first switch tube is electrically connected to the scan line, the first conductive end of the first switch tube is electrically connected to the data line through the data input end, and the second conductive end of the first switch tube is electrically connected to the first main electrode; the control end of the third switch tube is electrically connected to the scan line, the first conductive end of the third switch tube is electrically connected to the data line, and the second conductive end of the third switch tube is electrically connected to the first sub-electrode; the first switch tube and the third switch tube are used to be turned on simultaneously under the control of the scan signal to transmit the data signal to the first main electrode and the first sub-electrode in the first electrode layer.

[0008] Optionally, the driving circuit layer also includes a voltage-dividing capacitor, the control end of the second switch tube is electrically connected to the first control signal end, the first conductive end of the second switch tube is electrically connected to the second conductive end of the first switch tube, and the second conductive end of the second switch tube is electrically connected to the second electrode layer, and the second switch tube is used to be turned on under the control of the first control signal end to transmit the data signal to the second electrode layer; the control end of the fourth switch tube is electrically connected to the second control signal end, the control end of the fourth switch tube is electrically connected to the second control signal end, the first conductive end of the fourth switch tube is electrically connected to the second conductive end of the third switch tube, and the second conductive end of the fourth switch tube is electrically connected to the voltage-dividing capacitor, and the fourth switch tube is used to be turned on under the control of the second control signal end to transmit the data signal to the voltage-dividing capacitor.

[0009] Optionally, the fourth switch tube and the second switch tube are not turned on at the same time. If the second switch tube is turned on, the data signal is loaded and transmitted to the second electrode layer through the data input terminal; if the fourth switch tube is turned off, the first sub-electrode and the main electrode receive the same data signal to be loaded to the same voltage. If the fourth switch tube is turned on, the data signal loaded on the first sub-electrode is partially released through the fourth switch tube to be loaded to a different voltage from the first main electrode.

[0010] The present application also provides a display panel, including a counter substrate, a display medium layer and the aforementioned array substrate, the array substrate and the counter substrate are arranged relatively parallel with a preset distance, the display medium layer is arranged between the array substrate and the counter substrate, the counter substrate includes a common electrode, the array substrate and the counter substrate are used to form an electric field to drive the display medium in the display medium layer to rotate to emit light, wherein the second electrode layer and the first electrode layer do not form an electric field with the common electrode at the same time to drive the display medium layer to perform image display.

[0011] Optionally, the first pixel area includes four first sub-pixel areas arranged in an array, and the second pixel area includes four second sub-pixel areas arranged in an array; the first main electrode is used to form different electric fields with the common electrode according to the data signal to drive the display media in the four first sub-pixel areas to rotate different angles respectively to emit four kinds of light with different brightnesses, and the first auxiliary electrode forms different electric fields with the common electrode according to the received data signal to drive the display media in the four second sub-pixel areas to rotate different angles to emit four kinds of light with different brightnesses, wherein, if the first main electrode and the first auxiliary electrode are loaded to the same voltage, the brightness of the four kinds of light emitted from the first pixel area is consistent with that of the four kinds of light emitted from the second pixel area, and if the first main electrode and the first auxiliary electrode are loaded to different voltages, the four kinds of light emitted from the first pixel area are different from the four kinds of light emitted from the second pixel area; the second electrode layer forms an electric field with the common electrode according to the received data signal to drive the display media in the first sub-pixel area and the second sub-pixel area to rotate the same angle to emit light with the same brightness.

[0012] Optionally, corresponding to the first pixel area, the driving circuit layer also includes a first pixel capacitor and a first storage capacitor, the first pixel capacitor and the first storage capacitor are formed by coupling between the first main electrode and the common electrode, and the second conductive end of the first switch tube is electrically connected to the first pixel capacitor and the first storage capacitor, and is used to transmit data to the first pixel capacitor and the first storage capacitor.

[0013] Optionally, corresponding to the second pixel area, the driving circuit layer also includes a second pixel capacitor and a second storage capacitor, the second pixel capacitor and the second storage capacitor are formed by coupling between the first sub-electrode and the common electrode, and the second conductive end of the third switch tube is electrically connected to the second pixel capacitor and the second storage capacitor, for transmitting data to the second pixel capacitor and the second storage capacitor.

[0014] Optionally, when the first switch tube, the second switch tube and the third switch tube are turned on and the fourth switch tube is turned off, the second electrode layer forms an electric field with the common electrode according to the data signal to drive the display medium to emit the same light, and the first pixel area and the second pixel area emit the same light of the first brightness; when the first switch tube and the third switch tube are turned on and the second switch tube and the fourth switch tube are turned off, the first main electrode and the first sub-electrode are loaded to the same voltage, the four light rays emitted from the first pixel area are consistent with the four light rays emitted from the second pixel area and have the second brightness, and the first brightness is greater than the second brightness; when the first switch tube, the third switch tube and the fourth switch tube are turned on and the second switch tube is turned off, the first sub-electrode releases part of the data signal through the voltage-dividing capacitor, the first main electrode and the first sub-electrode are loaded to different voltages, and the four light rays emitted from the first pixel area are different from the four light rays emitted from the second pixel area.

[0015] Compared with the problems in the prior art, the present application sets a first electrode layer and a second electrode layer so that the first electrode layer and the second electrode layer can drive the display medium to rotate at different times. Since the first electrode layer and the second electrode layer have different structures, the corresponding display medium can be controlled to rotate at different angles. Therefore, the conversion between the wide viewing angle and the high brightness mode can be achieved by switching the first electrode layer and the second electrode layer, so that the display panel can be compatible with both high brightness and wide viewing angle display modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram of the structure of a display device provided in the first embodiment of the present application;

[0018] Figure 2 for Figure 1 A schematic diagram of the side structure of the display panel;

[0019] Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the display panel;

[0020] Figure 4 is a schematic diagram of the cross-sectional structure of a corresponding pixel unit in an array substrate;

[0021] Figure 5 for Figure 4 Schematic diagram of the planar layout of the first electrode layer;

[0022] Figure 6 for Figure 4 Schematic diagram of the planar layout of the second electrode layer;

[0023] Figure 7 for Figure 3 Schematic diagram of the equivalent circuit of the driving circuit in the pixel unit.

[0024] Description of the accompanying drawings: display device-100, display panel-10, power supply module-20 display area-10a, non-display area-10b, timing control circuit-11, data driving circuit-12, scanning driving circuit-13, pixel unit-30, backlight module-17, common electrode-Vcom, array substrate-10c, display medium layer-10e, opposite substrate-10d, clock signal-CLK, horizontal synchronization signal-Hsyn, vertical synchronization signal-Vsyn, gate output control signal-Cg, source output control signal-Cs, first direction-F1, second direction-F2, m data lines-S1~Sm, n scanning lines-G1~Gn, first pixel area-31, second pixel area-32, first sub-pixel area-311, second sub-pixel area-321, slit-st, base substrate-101, driving circuit layer-102, first passivation layer-103, first electrode layer-104, The second passivation layer-105, the second electrode layer-106, the first conductive layer-1021, the first insulating layer-1022, the active layer-1023, the second conductive layer-1024, the first gate-Gate1, the second gate-Gate2, the first sub-active layer-a1, the second sub-active layer-a2, the first source-s1, the first drain-d1, the second source-s2, the second drain-d2, the first through hole-H1, the second through hole-H2, the first main electrode- 1041, the first sub-electrode-1042, the i-th scanning line-Gi, the j-th data line-Sj, the first switch tube-T1, the second switch tube-T2, the third switch tube-T3, the fourth switch tube-T4, the first pixel capacitor-Clc1, the first storage capacitor-Cst1, the first capacitor-C1, the second pixel capacitor-Clc2, the second storage capacitor-Cst2, the first control signal terminal-K1, the second control signal terminal-K2, and the second capacitor-C2. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0026] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0027] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order.

[0028] In addition, the terms "include", "may include", "contain", or "may include" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "contain" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0030] See also Figure 1 , Figure 1A schematic diagram of the structure of a display device provided in the first embodiment of the present application. The display device 100 includes a display panel 10 and a power module 20, and the power module 20 is arranged on the back side of the display panel 10, that is, the non-display side of the display panel 10. The power module 20 is used to provide a power supply voltage for the display panel 10 to display an image. In the embodiment of the present application, the display device 100 can be a portable electronic device, such as a mobile phone, a tablet computer, etc.

[0031] See also Figure 2 , Figure 2 for Figure 1 Schematic diagram of the side structure of the display panel.

[0032] The display panel 10 includes an array substrate 10c, an opposing substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposing substrate 10d. A corresponding electric field is generated between the common electrodes Vcom disposed on the array substrate 10c and the opposing substrate 10d according to a data signal (Data), thereby driving the display medium in the display medium layer 10e to emit light of corresponding brightness to perform image display. The display medium may be liquid crystal molecules, miniLED, Micro-LED, OLED, etc., which is not limited in this application.

[0033] Taking the liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules, and the display panel 10 also includes a backlight module 17 (BM), wherein the backlight module 17 is used to provide light for display to the display medium layer 10e, and the liquid crystal molecules are deflected at a relative angle according to the data signal to emit the light transmitted by the backlight module 17 to the opposite substrate to perform image display.

[0034] Please also read Figure 3 , Figure 3 for Figure 2 Schematic diagram of the planar layout structure of the display panel.

[0035] like Figure 3 As shown, the display panel 10 further includes a timing control circuit 11, a data driving circuit 12 and a scanning driving circuit 13. The timing control circuit 11, the data driving circuit 12 and the scanning driving circuit 13 are arranged in the non-display area 10b of the display panel 10.

[0036] In the display area 10a of the display panel 10, m data lines (Source lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn are arranged in a grid shape. The m data lines S1 to Sm extend along a first direction F1, and the n scan lines G1 to Gn extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. The intersections of the n scan lines G1 to Gn and the m data lines S1 to Sm are correspondingly provided with pixel units 30.

[0037] The timing control circuit 11 receives an image signal Dv representing image information, a clock signal CLK for synchronization, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn from an external signal source, and outputs a gate output control signal Cg for controlling the scan drive circuit 13, a source output control signal Cs for controlling the data drive circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and transmits the data signal to the data drive circuit 12.

[0038] The m data lines S1 to Sm are connected to the data driving circuit 12 for receiving data signals stored and transmitted in the form of grayscale values ​​provided by the data driving circuit 12 . The n scan lines G1 to Gn are connected to the scan driving circuit 13 for receiving scan signals from the scan driving circuit 13 .

[0039] The pixel unit 30 receives the data voltage of the grayscale value in the corresponding data signal provided by the m data lines S1~Sm in a predetermined time period under the control of the n scanning lines G1~Gn, and drives the display medium layer 10e to deflect the corresponding angle accordingly, so that the received backlight emits light of corresponding brightness according to the corresponding deflection angle, so as to achieve image display by emitting light of corresponding brightness according to the image signal.

[0040] The scanning driving circuit 13 receives the gate output control signal Cg output by the timing control circuit 11, and outputs scanning signals to the n scanning lines G1 to Gn. The data driving circuit 12 receives the source output control signal Cs output by the timing control circuit 11, and outputs data signals for driving elements in each pixel unit 30 in the display area 10a to perform image display to the m data lines S1 to Sm. The data signal provided to the display panel 10 is a grayscale voltage in analog form. The scanning driving circuit 13 outputs a scanning signal to control the pixel unit 30 to receive the data signal output by the data driving circuit 12, so as to control the pixel unit 30 to display the corresponding image.

[0041] Please also read Figure 4 , Figure 5 and Figure 6 , Figure 4It is a schematic diagram of the cross-sectional structure of the corresponding pixel unit in the array substrate.

[0042] Figure 5 for Figure 4 Schematic diagram of the planar layout of the first electrode layer 104, Figure 6 for Figure 4 Schematic diagram of the planar layout of the second electrode layer 106.

[0043] like Figure 4 As shown, corresponding to each pixel unit 30, the array substrate 10c includes a base substrate 101, a driving circuit layer 102, a first passivation layer 103, a first electrode layer 104, a second passivation layer 105, and a second electrode layer 106 which are sequentially stacked in the thickness direction. The first electrode layer 104 includes a plurality of strip electrodes spaced at a preset distance and arranged parallel to each other, and the second electrode layer 106 is arranged in a flat plate shape to cover the second passivation layer 105. The orthographic projection of the first electrode layer 104 on the base substrate 101 is located within the orthographic projection of the second electrode layer 106 on the base substrate 101, that is, the second electrode layer 106 covers the first electrode layer 104.

[0044] The driving circuit layer 102 includes a first conductive layer 1021, a first insulating layer 1022, an active layer 1023, and a second conductive layer 1024. The first conductive layer 1021 is stacked on the base substrate 101 along the thickness direction. The first conductive layer 1021 includes a first gate Gate1 and a second gate Gate2 that are spaced at a preset distance. The first insulating layer 1022 covers the first gate Gate1 and the second gate Gate2.

[0045] The active layer 1023 is stacked on the first insulating layer 1022 away from the first conductive layer 1021, corresponding to the first pixel region 31 ( Figure 5 ), the active layer 1023 includes a first sub-active layer a1 and a second sub-active layer a2, the first sub-active layer a1 and the second sub-active layer a2 are arranged at a preset distance, the projection of the first sub-active layer a1 along the thickness direction on the base substrate 101 coincides with the first gate Gate1, and the projection of the second sub-active layer a2 along the thickness direction on the base substrate 101 coincides with the second gate Gate2.

[0046] The second conductive layer 1024 is stacked on the side of the first insulating layer 1022 away from the first conductive layer 1021, and the second conductive layer 1024 partially covers the active layer 1023. The second conductive layer 1024 includes a first source s1, a first drain d1, a second source s2, and a second drain d2, wherein the first source s1 and the first drain d1 are respectively arranged on both sides of the first sub-active layer a1 and partially cover the first active layer a1, and the second source s2 and the second drain d2 are respectively arranged on both sides of the second sub-active layer 104b and partially cover the second active layer a2, wherein the first gate Gate1, the first source s1, the first drain d1 and the first active layer a1 constitute a first switch tube T1, the second gate Gate2, the second source s2, the second drain d2 and the second active layer a2 constitute a second switch tube T2, and the first drain d1 is electrically connected to the second source s2.

[0047] The first passivation layer 103 is stacked on the side of the second conductive layer 1024 away from the first insulating layer 1022, and covers the active layer 1023 and the second conductive layer 1024. The first electrode layer 104 is stacked on the side of the first passivation layer 103 away from the second conductive layer 1024, and the first passivation layer 103 includes a first through hole H1, and the first electrode layer 104 is electrically connected to the first drain electrode d1 through the first through hole H1.

[0048] The second passivation layer 105 is stacked on the side of the first electrode layer 104 away from the first passivation layer 103, and the second electrode layer 106 is stacked on the side of the second passivation layer 105 away from the first electrode layer 104. The first passivation layer 103 and the second passivation layer 105 are provided with second through holes H2 at positions corresponding to the second drain d2, and the second electrode layer 106 is electrically connected to the second drain d2 through the second through holes H2.

[0049] like Figure 5 and Figure 6 As shown, the pixel unit 30 includes a first pixel area 31 and a second pixel area 32 that are adjacently arranged, and the first pixel area 31 and the second pixel area 32 respectively include four sub-pixel areas, that is, the first pixel area 31 includes four first sub-pixel areas 311, and the second pixel area 32 includes four second sub-pixel areas 321, that is, the first pixel area 31 and the second pixel area 32 constitute a pixel structure of a two-area eight-domain vertical alignment (VA) architecture. Among them, the first electrode layer 104 includes a first main electrode 1041 and a first sub-electrode 1042, the first main electrode 1041 is arranged corresponding to the first pixel area 31, and the first sub-electrode 1042 is arranged corresponding to the second pixel area 32, and a plurality of slits st that are arranged at intervals and parallel to each other are arranged in the first main electrode 1041 and the first sub-electrode 1042, and the second electrode layer 106 is in the shape of a plate and is arranged parallel to the first electrode layer 104 at a preset distance.

[0050] Corresponding to the first pixel area 31, the driving circuit layer 102 includes a first switch tube T1 and a second switch tube T2, the first switch tube T1 and the second switch tube T2 are connected in series, the first switch tube T1 is also electrically connected to the data input end (data line S) and the first main electrode 1041, the second switch tube T2 is also electrically connected to the second electrode layer 106, the first main electrode 1041 receives the data signal from the data input end through the first switch tube T1, and the second electrode layer 106 receives the data signal from the data input end through the first switch tube T1 and the second switch tube T2. Corresponding to the second pixel area 32, the driving circuit layer 102 also includes a third switch tube T3 ( Figure 7 ) and the fourth switch tube T4 ( Figure 7 ), the third switch tube T3 is connected in series with the fourth switch tube T4, the third switch tube T3 is also electrically connected to the data input end and the first auxiliary electrode 1042, and the first auxiliary electrode 1042 receives the data signal from the data input end through the third switch tube T3.

[0051] When the first main electrode 1041 and the common electrode Vcom form an electric field to drive the first pixel area 31 to emit light, the rotation angles of the liquid crystals in the four first sub-pixel areas 311 are different, so as to emit four kinds of light with different brightness. When the first auxiliary electrode 1042 and the common electrode Vcom form an electric field to drive the second pixel area 32 to emit light, the rotation angles of the liquid crystals in the four second sub-pixel areas 321 are different, so as to emit four kinds of light with different brightness. The first main electrode 1041 and the first auxiliary electrode 1042 have the same structure, that is, the four rotation angles of the liquid crystals in the first pixel area 31 and the second pixel area 32 are the same under the same voltage drive, so that the four kinds of light emitted by the first pixel area 31 and the second pixel area 32 are consistent, so as to form a 4-domain pixel display. When an electric field is formed between the second electrode layer 106 and the common electrode Vcom to drive the pixel unit 30 to emit light, the first pixel area 31 and the second pixel area 32 simultaneously emit light with the same brightness to form a 1-domain pixel display.

[0052] See also Figure 7 , Figure 7 for Figure 3 Schematic diagram of the equivalent circuit of the driving circuit in the pixel unit.

[0053] like Figure 7As shown, corresponding to the first pixel area 31, the driving circuit layer 102 includes a first switch tube T1 and a second switch tube T2, wherein the control end of the first switch tube T1 is electrically connected to the i-th scan line Gi, the first conductive end of the first switch tube T1 is electrically connected to the j-th data line Sj, and the second conductive end of the first switch tube T1 is electrically connected to the first main electrode 1041. The first main electrode 1041 and the common electrode Vcom are coupled to form a first pixel capacitor Clc1 and a first storage capacitor Cst1, which is equivalent to the second conductive end of the first switch tube T1 being electrically connected to the first pixel capacitor Clc1 and the first storage capacitor Cst1. Wherein, 1≤i≤n, 1≤j≤m

[0054] The control end of the second switch tube T2 is electrically connected to the first control signal end K1, the first conductive end of the second switch tube T2 is electrically connected to the second conductive end of the first switch tube T1, and the second conductive end of the second switch tube T2 is electrically connected to the second electrode layer 106, wherein the second electrode layer 106 and the common electrode Vcom are coupled to form a first capacitor C1, and therefore, it is equivalent to being electrically connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is electrically connected to the common electrode Vcom.

[0055] Corresponding to the second pixel area 32, the driving circuit layer 102 also includes a third switch tube T3 and a fourth switch tube T4, wherein the control end of the third switch tube T3 is electrically connected to the i-th scan line Gi, the first conductive end of the third switch tube T3 is electrically connected to the j-th data line Sj, the second conductive end of the third switch tube T3 is electrically connected to the first auxiliary electrode 1042, and the first auxiliary electrode 1042 is coupled with the common electrode Vcom to form a second pixel capacitor Clc2 and a second storage capacitor Cst2. Therefore, it is equivalent to that the second conductive end of the third switch tube T3 is electrically connected to the first end of the second pixel capacitor Clc2 and the first end of the second storage capacitor Cst2, the second end of the second pixel capacitor Clc2 is electrically connected to the common electrode Vcom, and the second end of the second storage capacitor Cst2 is electrically connected to the common electrode Vcom.

[0056] The control end of the fourth switch tube T4 is electrically connected to the second control signal end K2, the first conductive end of the fourth switch tube T4 is electrically connected to the second conductive end of the third switch tube T3, the second conductive end of the fourth switch tube T4 is electrically connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is electrically connected to the common electrode Vcom, wherein the second capacitor C2 is a voltage dividing capacitor, and when the fourth switch tube T4 is turned on, the voltage transmitted to the first sub-electrode 1042 is partially released to the second capacitor C2.

[0057] The display panel 10 includes a first display mode, a second display mode and a third display mode. When the display panel 10 executes the first display mode, the first switch tube T1, the second switch tube T2 and the third switch tube T3 are turned on, and the fourth switch tube T4 is turned off, so as to transmit the data signal to the second electrode layer 106. Since the second electrode layer 106 is arranged in a flat plate shape, an electric field is formed between the second electrode layer 106 and the common electrode Vcom to control the liquid crystal molecules in the four sub-pixel areas in the first pixel area 31 and the second pixel area 32 to rotate at the same angle, thereby emitting light of the same brightness to achieve high-brightness display, that is, to achieve 1-domain pixel display.

[0058] When the display panel 10 executes the second display mode, the first switch tube T1 and the third switch tube T3 are turned on, and the second switch tube T2 and the fourth switch tube T4 are turned off. The data signal is transmitted to the first main electrode 1041 through the first switch tube T1 to be stored in the first pixel capacitor Clc1 and the first storage capacitor Cst1, and is used to control the four first sub-pixel areas 311 in the first pixel area 31 to emit four different brightness lights respectively. The data signal is transmitted to the first sub-electrode 1042 through the third switch tube T3 to be stored in the second pixel capacitor Clc2 and the second storage capacitor Cst2, and is used to control the four second sub-pixel areas 311 in the second pixel area 32 to emit four different brightness lights respectively. Area 321 emits four kinds of light with different brightness respectively, wherein the first pixel capacitor Clc1 has the same capacitance value as the second pixel capacitor Clc2, and the first storage capacitor Cst1 has the same capacitance value as the second storage capacitor Cst2. Therefore, the four kinds of light with different brightness emitted by the first pixel area 31 are consistent with the four kinds of light with different brightness emitted by the second pixel area 32, that is, each pixel unit 30 emits four bright lines with different brightness to realize the image display corresponding to the 4-domain pixel architecture, so that when the user watches at a wide viewing angle, the rotation angle of the liquid crystal is not in the same direction, and the accumulation effect of the human eye is better, thereby solving the problem of color deviation at a wide viewing angle.

[0059] When the display panel 10 executes the third display mode, the first switch tube T1, the third switch tube T3 and the fourth switch tube T4 are turned on, and the second switch tube T2 is turned off. The data signal is transmitted to the first main electrode 1041 through the first switch tube T1 to be stored in the first pixel capacitor Clc1 and the first storage capacitor Cst1, and is used to control the four first sub-pixel areas 311 in the first pixel area 31 to respectively emit four kinds of light with different brightness. The data signal is transmitted to the first sub-electrode 1042 through the third switch tube T3 to be stored in the second pixel capacitor Clc2 and the second storage capacitor Cst2, and is used to control the four second sub-pixel areas 321 in the second pixel area 32 to respectively emit four kinds of light with different brightness. The data signal is also transmitted to the first auxiliary electrode 1042 through the third switch tube T3 to be stored in the second pixel capacitor Clc2 and the second storage capacitor Cst2, and is used to control the four second sub-pixel areas 321 in the second pixel area 32 to respectively emit four kinds of light with different brightness. The transistor T4 transmits the power to the second capacitor C2, and the second capacitor C2 is used for dividing the voltage of the second pixel capacitor Clc2 and the second storage capacitor Cst2 to control the charge stored in the second pixel capacitor Clc and the second storage capacitor Cst2 to be smaller than the charge in the first pixel capacitor Clc1 and the first storage capacitor Cst1, so as to control the four kinds of light with different brightness emitted by the first pixel area 31 and the four kinds of light with different brightness emitted by the second pixel area 32 to be different, that is, each pixel unit 30 emits 8 kinds of bright lines with different brightness to realize the image display corresponding to the 8-domain pixel architecture, so that when the user watches at a wide viewing angle, the rotation angle of the liquid crystal is not in the same direction, and the accumulation effect of the human eye is better, thereby further solving the problem of color deviation at a wide viewing angle.

[0060] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. An array substrate, characterized in that: The invention comprises a plurality of pixel units arranged in an array, and corresponding to each of the pixel units, the array substrate comprises a driving circuit layer, a first passivation layer, a first electrode layer, a second passivation layer and a second electrode layer which are sequentially stacked on the surface of a base substrate, the first electrode layer comprises a plurality of strip electrodes which are spaced at a preset distance and arranged parallel to each other, the second electrode layer is arranged in a flat plate shape covering the second passivation layer, and the orthographic projection of the first electrode layer on the base substrate is located within the orthographic projection of the second electrode layer on the base substrate.

2. The array substrate according to claim 1, characterized in that: The pixel unit includes a first pixel area and a second pixel area, the first electrode layer includes a first main electrode and a first sub-electrode, the first main electrode is arranged corresponding to the first pixel area, and is used to drive the first pixel area, the first sub-electrode is arranged corresponding to the second pixel area, and is used to drive the second pixel area, and the second electrode layer is arranged corresponding to the first pixel area and the second pixel area, and is used to simultaneously drive the first pixel area and the second pixel area.

3. The array substrate according to claim 2, characterized in that: Corresponding to the first pixel area, the driving circuit layer includes a first switch tube and a second switch tube, the first switch tube and the second switch tube are connected in series, the first switch tube is also electrically connected to the data input terminal and the first main electrode, respectively, the second switch tube is also electrically connected to the second electrode layer, the first main electrode receives a data signal from the data input terminal through the first switch tube, and the second electrode layer receives the data signal from the data input terminal through the first switch tube and the second switch tube; Corresponding to the second pixel area, the driving circuit layer also includes a third switch tube and a fourth switch tube, the third switch tube is connected in series with the fourth switch tube, the third switch tube is also electrically connected to the data input end and the first sub-electrode, and the first sub-electrode receives the data signal from the data input end through the third switch tube.

4. The array substrate according to claim 3, characterized in that: The array substrate further comprises a plurality of data lines and a plurality of scan lines, the pixel unit is arranged at the intersection of the data lines and the scan lines, the pixel unit is electrically connected to the data lines and the scan lines, and is used to receive a scan signal from the scan line and receive the data signal from the data line according to the scan signal; The control end of the first switch tube is electrically connected to the scan line, the first conductive end of the first switch tube is electrically connected to the data line through the data input end, and the second conductive end of the first switch tube is electrically connected to the first main electrode; the control end of the third switch tube is electrically connected to the scan line, the first conductive end of the third switch tube is electrically connected to the data line, and the second conductive end of the third switch tube is electrically connected to the first sub-electrode; the first switch tube and the third switch tube are used to be turned on simultaneously under the control of the scan signal to transmit the data signal to the first main electrode and the first sub-electrode in the first electrode layer.

5. The array substrate according to claim 4, characterized in that: The driving circuit layer further includes a voltage-dividing capacitor, the control end of the second switch tube is electrically connected to the first control signal end, the first conductive end of the second switch tube is electrically connected to the second conductive end of the first switch tube, the second conductive end of the second switch tube is electrically connected to the second electrode layer, and the second switch tube is used to be turned on under the control of the first control signal end to transmit the data signal to the second electrode layer; The control end of the fourth switch tube is electrically connected to the second control signal end, the control end of the fourth switch tube is electrically connected to the second control signal end, the first conductive end of the fourth switch tube is electrically connected to the second conductive end of the third switch tube, the second conductive end of the fourth switch tube is electrically connected to the voltage-dividing capacitor, and the fourth switch tube is used to be turned on under the control of the second control signal end to transmit the data signal to the voltage-dividing capacitor.

6. The array substrate according to claim 5, characterized in that: The fourth switch tube and the second switch tube are not turned on at the same time. If the second switch tube is turned on, the data signal is loaded and transmitted to the second electrode layer through the data input terminal; If the fourth switch tube is turned off, the first sub-electrode and the main electrode receive the same data signal to be loaded to the same voltage; if the fourth switch tube is turned on, the data signal loaded on the first sub-electrode is partially released through the fourth switch tube to be loaded to a different voltage from the first main electrode.

7. A display panel, characterized in that: It includes an opposing substrate, a display medium layer and an array substrate as described in any one of claims 3 to 5, wherein the array substrate and the opposing substrate are arranged relatively parallel to each other with a preset distance, the display medium layer is arranged between the array substrate and the opposing substrate, and the opposing substrate includes a common electrode. The array substrate and the opposing substrate are used to form an electric field to drive the display medium in the display medium layer to rotate to emit light, wherein the second electrode layer and the first electrode layer do not form an electric field with the common electrode at the same time to drive the display medium layer to perform image display.

8. The display panel according to claim 7, wherein: The first pixel region includes four first sub-pixel regions arranged in an array, and the second pixel region includes four second sub-pixel regions arranged in an array; The first main electrode is used to form different electric fields with the common electrode according to the data signal to drive the display media in the four first sub-pixel areas to rotate at different angles respectively to emit four kinds of light with different brightnesses; the first sub-electrode forms different electric fields with the common electrode according to the received data signal to drive the display media in the four second sub-pixel areas to rotate at different angles to emit four kinds of light with different brightnesses, wherein if the first main electrode and the first sub-electrode are loaded to the same voltage, the brightness of the four kinds of light emitted from the first pixel area is consistent with that of the four kinds of light emitted from the second pixel area; if the first main electrode and the first sub-electrode are loaded to different voltages, the four kinds of light emitted from the first pixel area are different from those of the four kinds of light emitted from the second pixel area; The second electrode layer forms an electric field with the common electrode according to the received data signal to drive the display media in the first sub-pixel area and the second sub-pixel area to rotate at the same angle to emit light with the same brightness.

9. The display panel according to claim 8, wherein: Corresponding to the first pixel area, the driving circuit layer also includes a first pixel capacitor and a first storage capacitor, the first pixel capacitor and the first storage capacitor are formed by coupling between the first main electrode and the common electrode, and the second conductive end of the first switch tube is electrically connected to the first pixel capacitor and the first storage capacitor, and is used to transmit the data to the first pixel capacitor and the first storage capacitor.

10. The display panel according to claim 9, wherein: Corresponding to the second pixel area, the driving circuit layer also includes a second pixel capacitor and a second storage capacitor, the second pixel capacitor and the second storage capacitor are formed by coupling between the first sub-electrode and the common electrode, and the second conductive end of the third switch tube is electrically connected to the second pixel capacitor and the second storage capacitor, and is used to transmit the data to the second pixel capacitor and the second storage capacitor.

11. The display panel according to claim 10, wherein: When the first switch tube, the second switch tube and the third switch tube are turned on and the fourth switch tube is turned off, the second electrode layer forms an electric field with the common electrode according to the data signal to drive the display medium to rotate at the same angle, and the first pixel area and the second pixel area emit light of the same first brightness; When the first switch tube and the third switch tube are turned on, and the second switch tube and the fourth switch tube are turned off, the first main electrode and the first sub-electrode are loaded with the same voltage, the four light rays emitted from the first pixel area are consistent with the four light rays emitted from the second pixel area and have a second brightness, and the first brightness is greater than the second brightness; When the first switch tube, the third switch tube and the fourth switch tube are turned on and the second switch tube is turned off, the first sub-electrode releases part of the data signal through the voltage-dividing capacitor, the first main electrode and the first sub-electrode are loaded with different voltages, and the four light rays emitted from the first pixel area are different from the four light rays emitted from the second pixel area.

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