High transient response PMOS (P-channel Metal Oxide Semiconductor) driving stage voltage stabilizing circuit without off-chip capacitor

Abstract

The invention discloses a PMOS (P-channel Metal Oxide Semiconductor) driving stage voltage stabilizing circuit with high transient response and no off-chip capacitor, which belongs to the field of voltage stabilizing circuits and comprises a reference voltage generating unit, an auxiliary pull-up unit, a main adjusting unit and an auxiliary pull-down unit. The PMOS driving stage voltage stabilizing circuit without the off-chip capacitor is realized by adopting the high-voltage MOS device, so that the chip area can be reduced, the transient response speed of the circuit is improved, and stable voltage is provided for the driving stage circuit.

Description

Technical Field

[0001] The invention belongs to the field of power integrated circuits, and in particular relates to a PMOS driving-level voltage stabilizing circuit with high transient response and no off-chip capacitor, which can be applied to driving circuits of power devices such as PMOS. Background Art

[0002] As a kind of power integrated circuit, the function of the driving circuit is to amplify the low-voltage logic control signal to sufficient power to drive the power tube to work normally. Power tubes are usually divided into PMOS power tubes and NMOS power tubes. NMOS power tubes can achieve higher driving capabilities and speeds than PMOS power tubes in the same area because their carriers are electrons, with higher mobility and stronger conductivity. Therefore, the load of common driving circuits is usually NMOS power tubes. However, under the application conditions of driving high-side NMOS power tubes, the source voltage of the NMOS tube is not fixed, and the device needs the assistance of a bootstrap circuit to turn on normally, and the power tube cannot be kept in the on state for a long time. Therefore, in practical applications, PMOS power tubes are also used as high-side power devices.

[0003] Figure 1 This is a typical application diagram of a PMOS drive circuit. The input signal is a logic control signal generated by the corresponding control circuit, which is used to control the opening or closing of the PMOS power device, and its reference voltage is GND. However, the gate drive signal of the high-side PMOS power tube should be referenced to a high voltage, so it is necessary to use a level shift circuit to raise the input signal from the low voltage domain with GND as the reference voltage to the high voltage domain. The reference ground of the high voltage domain is VREG, and the power supply is VCC. The reference ground VREG is usually generated by the driver-level power supply circuit, and the difference between VREG and VCC is the gate drive voltage of the PMOS device. When the switching state of the PMOS power tube changes, a large current will be drawn from the driver-level power supply circuit instantly, causing VREG to fluctuate, and ultimately causing the switching speed of the PMOS power tube to slow down and the switching loss to increase. To solve the above problems, the most direct approach is to connect a larger off-chip voltage stabilizing capacitor to the output of the driver-level power supply circuit. However, the introduction of off-chip capacitors will occupy additional system area, which is not conducive to improving the system power density.

[0004] Traditional driver-level power supply circuits such as Figure 2As shown, the circuit includes transistors Q1 and Q2, resistors R1 and R2, and voltage stabilizing diodes D1 and D2. The output voltage VREG can be adjusted by changing the number of forward diodes in series. When the output voltage fluctuates downward due to external response, the voltage |VBE| from the emitter to the base of transistor Q2 decreases, the current flowing through the emitter of transistor Q2 decreases, and VCC raises the output voltage to normal output through resistor R2. When the output voltage VREG fluctuates upward, the |VBE| of transistor Q2 increases, the current flowing through the emitter of transistor Q2 increases, and transistor Q2 pulls the output voltage down to normal output. However, in the traditional voltage stabilizing circuit, the pull-up capability of resistor R2 is weak, and the reverse recovery time is long when the output voltage fluctuates downward, which seriously affects the switching speed of the circuit.

[0005] Figure 3 It is an LDO (low dropout regulator, low voltage difference linear regulator) structure, and can also output a stable voltage. The circuit consists of a reference voltage generating circuit, an error amplifier circuit, a voltage divider sampling circuit and a transistor adjustment circuit. When the output voltage Vout decreases due to load changes or other reasons, the voltage output by the sampling resistor will also decrease. When the potential at point A is lower than the reference voltage VREF, the error amplifier output increases the gate voltage of the high-voltage PMOS device HMP5, thereby increasing the on-resistance of the high-voltage PMOS device HMP5, thereby increasing the output voltage Vout. When the output voltage Vout increases due to load changes, the voltage regulation principle is similar to the adjustment process when it decreases.

[0006] Figure 3 The LDO structure shown has some problems in the driving application of high-speed response PMOS devices. First, there is a large transient switching current in the output drive stage circuit of the PMOS device, and the stability design of the LDO is more difficult. In addition, in the high power supply voltage scenario, high-precision comparators, current mirrors and other circuits require the use of more high-voltage devices, occupying a larger layout area. Third, when the load change generates a large transient current and causes the output voltage of the LDO to fluctuate downward, due to the influence of the feedback delay of the LDO, the output voltage fluctuates downward more and the recovery time will be longer. The general solution is to add a load discharge circuit at the output end to solve the problem of large overcharge of the output voltage downward. The circuit can also be designed symmetrically as a push-pull structure to enhance the pull-up and pull-down capabilities of the LDO at the same time, but the implementation of this structure is more complicated. Summary of the invention

[0007] The purpose of the present invention is to provide a PMOS driver-level voltage stabilizing circuit with high transient response and no external capacitor, which overcomes the problem of slow recovery time after the output voltage fluctuates when the load-side switch state is switched in the traditional power supply circuit. The present invention is optimized on the basis of the traditional circuit structure to solve the problem of large overcharge voltage generated by the output of the high-side driver-level power supply circuit when a large transient switching current is generated at the load end, and to improve the transient response speed and stability of the circuit.

[0008] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0009] A PMOS driver-level voltage stabilizing circuit with high transient response and no off-chip capacitors, comprising: a reference voltage generating unit, an auxiliary pull-up unit, a main adjustment unit and an auxiliary pull-down unit;

[0010] The reference voltage generating unit includes a reference current source I1, a high-voltage PMOS tube HMP1 and a resistor R1; the gate and drain of the high-voltage PMOS tube HMP1 are connected to one end of the reference current source I1, the other end of the reference current source I1 is connected to the ground GND, the source of the high-voltage PMOS tube HMP1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC;

[0011] The auxiliary pull-up unit includes a high-voltage PMOS tube HMP2, a medium-voltage PMOS tube HMP4, a medium-voltage NMOS tube HMN1, a medium-voltage NMOS tube HMN2, a capacitor C1, a reference current source I2 and a reference current source I3; the drain of the high-voltage PMOS tube HMP2 is connected to the ground GND, the gate of the high-voltage PMOS tube HMP2 is connected to the gate of the high-voltage PMOS tube HMP1, the source of the high-voltage PMOS tube HMP2 is connected to the source of the medium-voltage NMOS tube HMN1, and the medium-voltage NM The gate and drain of the OS transistor HMN1 are connected to the gate of the medium voltage NMOS transistor HMN2 and one end of the reference current source I2, the other end of the reference current source I2 is connected to the power supply VCC, the drain of the medium voltage NMOS transistor HMN2 is connected to the gate of the medium voltage PMOS transistor HMP4 and one end of the reference current source I3, the other end of the reference current source I3 and the source of the medium voltage PMOS transistor HMP4 are connected to the power supply VCC, and the two ends of the capacitor C1 are respectively connected to the source and drain of the medium voltage NMOS transistor HMN2;

[0012] The main adjustment unit includes a high-voltage PMOS tube HMP3 and a resistor R2; the gate of the high-voltage PMOS tube HMP3 is connected to the gate of the high-voltage PMOS tube HMP2, the source of the high-voltage PMOS tube HMP3 is connected to the drain of the medium-voltage PMOS tube HMP4 and one end of the resistor R2, and the other end of the resistor R2 is connected to the power supply VCC;

[0013] The auxiliary pull-down unit includes a high-voltage NMOS tube HMN3 and a resistor R3; the gate of the high-voltage NMOS tube HMN3 is connected to the drain of the high-voltage PMOS tube HMP3 and the resistor R3, the source of the high-voltage NMOS tube HMN3 and the other end of the resistor R3 are connected to the ground GND, and the drain of the high-voltage NMOS tube HMN3 is connected to the source of the high-voltage PMOS tube HMP3 and outputs the voltage VREG.

[0014] Furthermore, the PMOS driver-level voltage stabilizing circuit with high transient response and no off-chip capacitor also includes an isolation unit to reduce the influence of the output voltage VREG on the reference voltage; the isolation unit includes a high-voltage PMOS tube HMP6 and a reference current source I4; the drain of the high-voltage PMOS tube HMP6 is connected to the ground GND, the source of the high-voltage PMOS tube HMP6 is connected to the reference current source I4 and the gate of the high-voltage PMOS tube HMP2, the other end of the reference current source I4 is connected to the power supply VCC, and the gate of the high-voltage PMOS tube HMP6 is connected to the gate of the high-voltage PMOS tube HMP1; the reference voltage generating unit also includes a high-voltage PMOS tube HMP5, whose drain and gate are connected to the source of the high-voltage PMOS tube HMP1, and the source of the high-voltage PMOS tube HMP5 is connected to one end of the resistor R1.

[0015] Furthermore, the sizes of the high-voltage PMOS tube HMP2 and the high-voltage PMOS tube HMP3 are proportional; the sizes of the medium-voltage NMOS tube HMN1 and the medium-voltage NMOS tube HMN2 are the same; and the current value of the reference current source I3 is twice the current value of the reference current source I2.

[0016] Furthermore, the size of the high-voltage PMOS tube HMP3 is 10 times the size of the high-voltage PMOS tube HMP2.

[0017] Furthermore, the reference voltage generating unit generates a reference voltage with the power supply voltage as a reference, and the reference voltage does not change with the power supply voltage. The reference voltage is realized by a voltage drop generated by a reference current source I1 on a resistor R1. In addition, it can be realized by connecting multiple Zener diodes in series in the reverse breakdown region or by a low voltage difference linear regulator through feedback.

[0018] The PMOS driver-level voltage stabilizing circuit with high transient response and no external capacitor of the present invention has the following advantages:

[0019] 1. No external voltage stabilizing capacitors are required, which greatly improves the integration of the circuit and reduces the chip area.

[0020] 2. When the switching state of the PMOS power tube in the PMOS driving circuit changes, the auxiliary unit involved in the present invention can reduce the positive and negative fluctuations of the output voltage, improve the transient response speed, and thus improve the switching speed of the PMOS power tube and reduce the switching loss.

[0021] 3. The fluctuation of the output voltage of the present invention will not be coupled to the reference voltage generating unit due to the effect of the isolation unit, thereby improving the stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a typical application diagram of a PMOS drive circuit;

[0023] Figure 2 This is a diagram of the traditional voltage stabilization circuit structure;

[0024] Figure 3 It is the structure diagram of the traditional low voltage drop linear regulator;

[0025] Figure 4 A PMOS driver-level voltage stabilizing circuit with high transient response and no off-chip capacitor provided according to the first embodiment of the present invention;

[0026] Figure 5 A PMOS driver-level voltage stabilizing circuit diagram with high transient response and no off-chip capacitor provided according to a second embodiment of the present invention;

[0027] Figure 6 The waveform diagrams are the input signal VIN of the PMOS driving circuit, the output signal of the high-side driving stage circuit, the output voltage of the traditional voltage stabilizing circuit and the output voltage of the present invention;

[0028] Markings in the figure: 001, reference voltage generating unit; 002, auxiliary pull-up unit; 003, main adjustment unit; 004, auxiliary pull-down unit; 005, isolation unit. DETAILED DESCRIPTION

[0029] In order to better understand the purpose, structure and function of the present invention, a PMOS driver-level voltage stabilizing circuit with high transient response and no off-chip capacitor of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0030] Figure 4 The first embodiment of the PMOS driver-level voltage stabilizing circuit with high transient response and no off-chip capacitor proposed by the present invention is used to stabilize the voltage fluctuation generated by the high-side power rail of the PMOS device driver circuit when the load changes, specifically including Figure 4 The reference voltage generating unit 001, the auxiliary pull-up unit 002, the main adjustment unit 003 and the auxiliary pull-down unit 004 are shown;

[0031] The reference voltage generating unit 001 includes a reference current source I1, a high-voltage PMOS tube HMP1 and a resistor R1; the gate and drain of the high-voltage PMOS tube HMP1 are connected to one end of the reference current source I1, the other end of the reference current source I1 is connected to the ground GND, the source of the high-voltage PMOS tube HMP1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the power supply VCC;

[0032] The auxiliary pull-up unit 002 includes a high-voltage PMOS tube HMP2, a medium-voltage PMOS tube HMP4, a medium-voltage NMOS tube HMN1, a medium-voltage NMOS tube HMN2, a capacitor C1, a reference current source I2 and a reference current source I3; the drain of the high-voltage PMOS tube HMP2 is connected to the ground GND, the gate of the high-voltage PMOS tube HMP2 is connected to the gate of the high-voltage PMOS tube HMP1, the source of the high-voltage PMOS tube HMP2 is connected to the source of the medium-voltage NMOS tube HMN1, and the medium-voltage The gate and drain of the NMOS tube HMN1 are connected to the gate of the medium voltage NMOS tube HMN2 and one end of the reference current source I2, the other end of the reference current source I2 is connected to the power supply VCC, the drain of the medium voltage NMOS tube HMN2 is connected to the gate of the medium voltage PMOS tube HMP4 and one end of the reference current source I3, the other end of the reference current source I3 and the source of the medium voltage PMOS tube HMP4 are connected to the power supply VCC, and the two ends of the capacitor C1 are respectively connected to the source and drain of the medium voltage NMOS tube HMN2;

[0033] The main adjustment unit 003 includes a high-voltage PMOS tube HMP3 and a resistor R2; the gate of the high-voltage PMOS tube HMP3 is connected to the gate of the high-voltage PMOS tube HMP2, the source of the high-voltage PMOS tube HMP3 is connected to the drain of the medium-voltage PMOS tube HMP4 and one end of the resistor R2, and the other end of the resistor R2 is connected to the power supply VCC;

[0034] The auxiliary pull-down unit 004 includes a high-voltage NMOS tube HMN3 and a resistor R3; the gate of the high-voltage NMOS tube HMN3 is connected to the drain of the high-voltage PMOS tube HMP3 and the resistor R3, the source of the high-voltage NMOS tube HMN3 and the other end of the resistor R3 are connected to the ground GND, and the drain of the high-voltage NMOS tube HMN3 is connected to the source of the high-voltage PMOS tube HMP3 and outputs the voltage VREG.

[0035] when Figure 1 When the high-side driver output is at the falling edge, the driver power supply circuit needs to provide a large pull-down current, which corresponds to Figure 4The output voltage VREG has a large current flowing into the source node of the high-voltage PMOS tube HMP3. Under the limited tube size, the output voltage VREG will be overcharged upward, increasing the gate-source voltage of the high-voltage PMOS tube HMP3 (only the absolute value is discussed here) to enhance the current capacity. The larger overcharge voltage will reduce Figure 1 The present invention adopts a resistor R3 and a high-voltage NMOS tube HMN3 to enhance the pull-down current capability of the output voltage VREG. When the current flowing into the source node of the high-voltage PMOS tube HMP3 is large, the voltage drop across the resistor R3 increases, thereby increasing the gate voltage of the high-voltage NMOS tube HMN3 and the current flowing into the drain node of the high-voltage NMOS tube HMN3. Since the current capability of NMOS devices of the same size is relatively strong, the use of NMOS devices can effectively assist in increasing the pull-down current capability of the output voltage VREG, thereby reducing the positive overcharge of the output terminal VREG.

[0036] At the same time, since the high-voltage NMOS tube HMN3 has a strong pull-down current capability, when the output voltage of the driver stage ends its falling edge, the potential of the power supply voltage VREG will be pulled down by the current flowing into the drain node of the high-voltage NMOS tube HMN3, resulting in negative overcharge. Therefore, a feedback circuit is introduced to solve the problem of negative overcharge. When the output voltage VREG drops, the source voltage of the medium-voltage NMOS tube HMN2 drops. At this time, the gate-source voltage of the medium-voltage NMOS tube HMN2 increases, so that the on-resistance of the medium-voltage NMOS tube HMN2 decreases, and the gate voltage of the medium-voltage PMOS tube HMP4 decreases. When its gate voltage decreases to VCC-|Vth| (Vth is the threshold voltage of the medium-voltage PMOS tube HMP4), the medium-voltage PMOS tube HMP4 turns on and provides a pull-up current to the output terminal VREG together with the auxiliary medium-voltage NMOS tube HMN2, thereby reducing the negative overcharge of the output terminal VREG. In this negative feedback process, adding capacitor C1 can increase the phase margin of the feedback circuit and improve the stability of the circuit.

[0037] Taking into account the process deviation of the medium voltage NMOS tubes HMN1 and HMN2, when the reference current sources I2 and I3 flow through the same current, there is still a risk that the medium voltage PMOS tube HMP4 is turned on when the output voltage VREG is near a stable value. Therefore, a certain redundancy needs to be set so that the output voltage VREG drops to a certain extent before the auxiliary pull-up unit can be turned on. Specifically, the current value of the reference current source I3 can be set to twice the current value of the reference current source I2, so that when the output voltage VREG is lower than the stable value to a certain extent, the gate voltage of the medium voltage PMOS tube HMP4 can be reduced to turn on the medium voltage PMOS tube HMP4.

[0038] like Figure 5The second embodiment of the PMOS driver-level voltage stabilizing circuit with high transient response and no off-chip capacitor of the present invention is shown. An isolation unit 005 is added between the reference voltage generating unit 001 and the auxiliary pull-up unit 002 of the first embodiment, and the reference voltage generating unit 001 also includes a high-voltage PMOS device HMP5 to balance the gate-source voltage of the high-voltage PMOS device HMP6 of the isolation unit 005. Since the size of the high-voltage PMOS device HMP3 is large, its gate-source capacitance Cgs3 is also increased. When the output voltage VREG fluctuates, it will be coupled to the reference voltage generating unit through Cgs3, affecting the stability of the voltage. Therefore, this embodiment adds a common drain isolation unit, and the size of the high-voltage PMOS device HMP6 is relatively small, which can effectively reduce the influence of the fluctuation of the output voltage VREG on the reference voltage.

[0039] Figure 6 The working waveform diagram of the input and output signals of the present invention and the comparison diagram of the output waveform of the present invention and the traditional voltage stabilizing circuit are shown. When the input signal is input into the logic control signal generated by the corresponding control circuit, the traditional voltage stabilizing circuit has obvious positive and negative overcharge when the output signal of the high-side driving stage circuit changes, which will affect the stabilization speed of VREG; the present invention greatly reduces the positive and negative overcharge of the output voltage by adding the auxiliary pull-up unit 002 and the auxiliary pull-down unit 004, and improves the transient response speed of the circuit.

[0040] The high transient response PMOS driver stage voltage stabilization circuit without off-chip capacitors proposed in an embodiment of the present invention uses medium and high voltage PMOS devices and NMOS devices, which can provide a stable voltage for the PMOS driver stage, thereby improving the transient response speed and stability of the circuit. At the same time, the lack of off-chip capacitors improves the integration of the chip.

[0041] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A PMOS driver-level voltage regulator circuit with high transient response and no off-chip capacitor, which is characterized by comprising: A reference voltage generating unit (001), an auxiliary pull-up unit (002), a main adjustment unit (003) and an auxiliary pull-down unit (004); The reference voltage generating unit (001) comprises a reference current source I1, a high-voltage PMOS tube HMP1 and a resistor R1; the gate and drain of the high-voltage PMOS tube HMP1 are connected to one end of the reference current source I1, the other end of the reference current source I1 is connected to a ground GND, the source of the high-voltage PMOS tube HMP1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to a power supply VCC; The auxiliary pull-up unit (002) comprises a high-voltage PMOS tube HMP2, a medium-voltage PMOS tube HMP4, a medium-voltage NMOS tube HMN1, a medium-voltage NMOS tube HMN2, a capacitor C1, a reference current source I2 and a reference current source I3; the drain of the high-voltage PMOS tube HMP2 is connected to the ground GND, the gate of the high-voltage PMOS tube HMP2 is connected to the gate of the high-voltage PMOS tube HMP1, the source of the high-voltage PMOS tube HMP2 is connected to the source of the medium-voltage NMOS tube HMN1, and the medium The gate and drain of the medium-voltage NMOS tube HMN1 are connected to the gate of the medium-voltage NMOS tube HMN2 and one end of the reference current source I2, the other end of the reference current source I2 is connected to the power supply VCC, the drain of the medium-voltage NMOS tube HMN2 is connected to the gate of the medium-voltage PMOS tube HMP4 and one end of the reference current source I3, the other end of the reference current source I3 and the source of the medium-voltage PMOS tube HMP4 are connected to the power supply VCC, and the two ends of the capacitor C1 are respectively connected to the source and drain of the medium-voltage NMOS tube HMN2; The main adjustment unit (003) comprises a high-voltage PMOS tube HMP3 and a resistor R2; the gate of the high-voltage PMOS tube HMP3 is connected to the gate of the high-voltage PMOS tube HMP2, the source of the high-voltage PMOS tube HMP3 is connected to the drain of the medium-voltage PMOS tube HMP4 and one end of the resistor R2, and the other end of the resistor R2 is connected to a power supply VCC; The auxiliary pull-down unit (004) comprises a high-voltage NMOS tube HMN3 and a resistor R3; the gate of the high-voltage NMOS tube HMN3 is connected to the drain of the high-voltage PMOS tube HMP3 and the resistor R3, the source of the high-voltage NMOS tube HMN3 and the other end of the resistor R3 are connected to the ground GND, and the drain of the high-voltage NMOS tube HMN3 is connected to the source of the high-voltage PMOS tube HMP3 and outputs a voltage VREG.

2. The high transient response PMOS driver-level voltage stabilizing circuit without external capacitor according to claim 1, characterized in that: The device also includes an isolation unit (005); the isolation unit (005) includes a high-voltage PMOS tube HMP6 and a reference current source I4; the drain of the high-voltage PMOS tube HMP6 is connected to the ground GND, the source of the high-voltage PMOS tube HMP6 is connected to the reference current source I4 and the gate of the high-voltage PMOS tube HMP2, the other end of the reference current source I4 is connected to the power supply VCC, and the gate of the high-voltage PMOS tube HMP6 is connected to the gate of the high-voltage PMOS tube HMP1; the reference voltage generating unit (001) also includes a high-voltage PMOS tube HMP5, the drain and gate of which are connected to the source of the high-voltage PMOS tube HMP1, and the source of the high-voltage PMOS tube HMP5 is connected to one end of the resistor R1.

3. The high transient response PMOS driver-level voltage stabilizing circuit without external capacitor according to claim 1 or 2, characterized in that: The sizes of the high-voltage PMOS tube HMP2 and the high-voltage PMOS tube HMP3 are proportional; the sizes of the medium-voltage NMOS tube HMN1 and the medium-voltage NMOS tube HMN2 are the same; the current value of the reference current source I3 is twice the current value of the reference current source I2.

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