Multifunctional reset circuit

Abstract

The invention discloses a multifunctional reset circuit, which is connected with a processor and is consistent with the processor in power supply, and comprises a monitoring circuit used for monitoring the power supply voltage of the processor and a CD4011 NAND gate circuit connected with the monitoring circuit, the monitoring circuit comprises an MAX791 monitoring chip, and the MAX791 monitoring chip is connected with the CD4011 NAND gate circuit. The sixteenth pin end and the fifteenth pin end of the MAX791 monitoring chip are connected with the CD4011 NAND gate circuit, the CD4011 NAND gate circuit comprises a CD4011 chip, and the CD4011 NAND gate circuit is used for outputting a reset signal; the device has the advantages of being simple in structure, complete in function and wide in application range, the power-on reset function, the manual reset function and the crash reset function of the processor can be completed, watchdog shielding can be achieved through manual control, the software online loading function is completed, and the software online loading efficiency is improved. The method can be used for equipment requiring manual reset, power-down reset, software online upgrade and reset time, and is suitable for various processors.

Description

Technical Field

[0001] The invention relates to the technical field of processor reset circuits, in particular to a multifunctional reset circuit. Background Art

[0002] In the application equipment of commercial, industrial, aerospace and other fields, in order to ensure the normal and reliable operation of the core processor of the product, it is often necessary to add necessary power-on reset, manual reset, and watchdog timeout reset functions when the software crashes. At the same time, due to some changes in requirements and addition of software functions in the application process, it is often necessary to change the software of the processor, but it often takes time and cost to return the equipment to the factory for software upgrade after leaving the factory. The time cost is high. Therefore, the in-situ software upgrade function of the equipment is indispensable. Therefore, in these occasions where software online loading is required, the watchdog signal in the reset circuit needs to be manually shielded to realize the in-situ software online upgrade of the equipment. The existing reset circuit has a relatively single function. Therefore, a multifunctional reset circuit is proposed. Summary of the invention

[0003] The object of the present invention is to provide a multifunctional reset circuit to solve the problems of single function and high time cost mentioned in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions: A multifunctional reset circuit is connected to a processor and is consistent with the processor power supply, comprising a monitoring circuit for monitoring the processor power supply voltage, and a CD4011 NAND gate circuit connected to the monitoring circuit, the monitoring circuit comprising a MAX791 monitoring chip, the 16th pin end and the 15th pin end of the MAX791 monitoring chip are connected to the CD4011 NAND gate circuit, the MAX791 monitoring chip is used for inputting signals, and the input signals comprise a dog feeding signal, a watchdog shielding signal and a manual reset control signal, the watchdog shielding signal and the manual reset control signal are both ground / open signals, and the dog feeding signal is connected to the signal port of the processor; The CD4011 NAND gate circuit includes a CD4011 chip, a pull-up resistor R1, a pull-up resistor R5, a pull-up resistor R7, a pull-up resistor R8, a pull-up resistor R9 and a current limiting resistor R6. The CD4011 NAND gate circuit is used to output a reset signal, the reset signal is connected to the reset pin end of the processor, and the CD4011 chip is used for logic conversion between input signals and output reset signals.

[0005] Furthermore, the monitoring circuit also includes a decoupling capacitor C1, a decoupling capacitor C2 and a filter capacitor C3, wherein the filter capacitor C3 is used as a watchdog timeout adjustment capacitor, and the monitoring circuit is used to power on and reset the processor when the processor power supply voltage is lower than its normal operating voltage.

[0006] Furthermore, the monitoring circuit also includes a resistor R2, a resistor R3 and a resistor R4 connected to the MAX791 monitoring chip, and the resistance value of the voltage divider resistor R2 and the resistor R4 can be adjusted to adapt to the normal power supply voltage range of the processor.

[0007] Furthermore, the CD4011 NAND gate circuit further includes a decoupling capacitor C4, an input end of the decoupling capacitor C4 is connected to a 3.3V power supply, and an output end of the decoupling capacitor C4 is connected to a power ground DGND.

[0008] The beneficial effects of the present invention are as follows: the present invention has the characteristics of simple structure, complete functions and wide application range, can complete the power-on reset, manual reset and crash reset functions of the processor, and can also realize watchdog shielding through manual control to complete the software online loading function; while realizing the power-on reset of the device processor and the software crash timeout reset function, it can also realize online loading through manual control reset and manual control shielding of the watchdog, and the watchdog reset time can be set by adjusting the device parameters as needed to meet the application requirements of the equipment with reset time requirements, and is suitable for a variety of processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a multifunctional reset circuit diagram of the present invention.

[0010] In the figure: 1 MAX791 monitoring chip, 2 watchdog feeding signal, 3 CD4011 NAND gate circuit, 4 reset signal, 5 watchdog shield signal, 6 manual reset control signal. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] See also Figure 1, which provides a technical solution for the present invention, a multifunctional reset circuit, connected to a processor and consistent with the processor power supply, including a monitoring circuit for monitoring the processor power supply voltage, and a CD4011 NAND gate circuit 3 connected to the monitoring circuit, the monitoring circuit includes a MAX791 monitoring chip 1, the sixteen-pin end and the fifteen-pin end of the MAX791 monitoring chip 1 are connected to the CD4011 NAND gate circuit 3, the MAX791 monitoring chip 1 is used to input signals, and the input signals include a dog feeding signal 2, a watchdog shielding signal 5 and a manual reset control signal 6, the watchdog shielding signal 5 and the manual reset control signal 6 are both ground / open signals, and the dog feeding signal 2 is connected to the signal port of the processor; the CD4011 NAND gate circuit 3 includes a CD4011 chip, a pull-up resistor R1, a pull-up resistor R5, a pull-up resistor R7, a pull-up resistor R8, a pull-up resistor R9 and a current limiting resistor R6, the CD4011 NAND gate circuit 3 is used to output a reset signal, the reset signal is connected to the reset pin end of the processor, the pull-up resistor R1 , pull-up resistor R5, pull-up resistor R7, pull-up resistor R8, and pull-up resistor R9 play the role of fixing the level; the CD4011 chip is used for logic conversion between input signals and output reset signals; the CD4011 NAND gate circuit also includes a decoupling capacitor C4, the input end of the decoupling capacitor C4 is connected to a 3.3V power supply, and the output end of the decoupling capacitor C4 is connected to the power ground DGND; wherein, the dog feeding signal 2 is marked as a WDI signal, the WDI signal is sent by the processor, and continuously flips to a normal dog feeding state, and a continuous high or low level is an abnormal state; the watchdog shielding signal 5 is marked as a CON1 signal, and the CON1 signal is used to shield the dog feeding timeout reset function during online upgrades. The signal is grounded and valid, and the normal state input is open; the manual reset control signal 6 is marked as a CON2 signal, and the CON2 signal is grounded when the processor needs to be manually reset, and the normal state input is open; the function of the current limiting resistor R6 is to ensure that the circuit will not be damaged when the CON2 signal input conflicts with the CD4011 chip output level.

[0013] In this embodiment, the monitoring circuit mentioned also includes a decoupling capacitor C1, a decoupling capacitor C2 and a filter capacitor C3, wherein the filter capacitor C3 is used as a watchdog timeout adjustment capacitor, and the monitoring circuit is used to power on and reset the processor when the processor power supply voltage is lower than its normal operating voltage; the monitoring circuit also includes a resistor R2, a resistor R3 and a resistor R4 connected to the MAX791 monitoring chip 1, and the voltage divider resistance value of the resistor R2 and the resistor R4 can be adjusted to adapt to the normal power supply voltage range of the processor.

[0014] The multifunctional reset circuit realizes the watchdog circuit function through the MAX791 monitoring chip 1, CD4011 NAND gate, resistors, capacitors and other devices. The MAX791 monitoring chip 1 and CD4011 chip are used to realize logic combination and switching. The resistors and capacitors are used for filtering and delaying the transmission signal between the NAND gates. By controlling the setting of the resistor and capacitor parameters, the configuration function of the power-off reset threshold and the timeout reset time is realized.

[0015] The multifunctional reset circuit is used when the 3.3V power supply starts to supply power. Before the minimum voltage of 3.029V for the processor power supply is reached, the six-pin PFO signal of the MAX791 monitoring chip 1 is output as a low level. At this time, the eleven-pin RESET reset signal of the CD4011 chip maintains a low level, and the processor maintains a reset state; after power-on, the fifteen-pin RET signal of the MAX791 monitoring chip 1 maintains a low level for 140ms to 280ms, preferably 200ms, at this time, the 11-pin RESET reset signal of the CD4011 chip maintains a low level, and the processor maintains a reset state; after the power-on reset is completed, the six-pin PFO signal and the fifteen-pin RET signal of the MAX791 monitoring chip 1 are The output is high level. At this time, the eleventh pin RESET reset signal of CD4011 chip is high level, the processor is no longer reset, and the reset circuit is fed normally through the WDI signal. At this time, the fourteenth pin WDO output of MAX791 monitoring chip 1 is high level, MR is the nine pins of MAX791 monitoring chip 1 to maintain high level, CON1 signal and CON2 signal are open circuit input signals, and the processor works normally; when the processor power supply voltage is lower than 3.029V, the six-pin PFO signal output of MAX791 monitoring chip 1 is low level through power-off reset, CD401 11 pin RESET reset signal of chip 1 is set to low level, and the processor is reset; when the processor works abnormally and stops feeding the dog, the 14 pin WDO output of MAX791 monitoring chip 1 is low level, MR is set to low level, at this time, the 15 pin RET of MAX791 monitoring chip 1 will output low level, the 11 pin RESET reset signal of CD4011 chip is also low level, and the processor is reset; when the processor needs to be manually reset during normal operation, the CON2 signal input is grounded at a low level, which is equivalent to MR being set to a low level, at this time, the 15 pin RET of MAX791 monitoring chip 1 will output a low level, the 11 pin RESET reset signal of CD4011 chip is also low level, and the processor is reset; when the processor needs to be upgraded online software during normal operation, the CON1 signal input is grounded at a low level, at this time, no matter what state the WDI signal and WDO signal are, the MR signal is high level, and the processor will not be reset; it should be noted that: when the CON2 input is maintained at a low level, the manual reset is always valid, and the software cannot be upgraded online through CON1; the logic truth table of the multi-function reset circuit is as follows:

[0016] In summary: combined with the logic truth table 1, this multifunctional reset circuit can realize the power-on reset of the device processor and the software crash timeout reset function, and the reset time is adjustable. At the same time, it can also realize online loading by manually controlling the reset and manually controlling the shielding of the watchdog. It is not only suitable for a variety of processors, but also has the advantages of simple circuit structure, complete functions, and a wide range of applications.

[0017] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0018] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be understood that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. In the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", "connection", "fixation" and the like should be understood in a broad sense, for example, it can be a fixed connection, or a detachable connection, or integrated; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components; among them, there are many ways of detachable installation, for example, it can be through the way of plug-in and snap-fit, for example, through the way of bolt connection, etc.

[0019] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A multifunctional reset circuit connected to a processor and having the same power supply as the processor, characterized in that: It includes a monitoring circuit for monitoring the processor power supply voltage, and a CD4011 NAND gate circuit connected to the monitoring circuit, the monitoring circuit includes a MAX791 monitoring chip, the 16th pin end and the 15th pin end of the MAX791 monitoring chip are connected to the CD4011 NAND gate circuit, the MAX791 monitoring chip is used for inputting signals, and the input signals include a dog feeding signal, a watchdog shielding signal and a manual reset control signal, the watchdog shielding signal and the manual reset control signal are both ground / open signals, and the dog feeding signal is connected to the signal port of the processor; The CD4011 NAND gate circuit includes a CD4011 chip, a pull-up resistor R1, a pull-up resistor R5, a pull-up resistor R7, a pull-up resistor R8, a pull-up resistor R9 and a current limiting resistor R6. The CD4011 NAND gate circuit is used to output a reset signal, the reset signal is connected to the reset pin end of the processor, and the CD4011 chip is used for logic conversion between input signals and output reset signals.

2. The multifunctional reset circuit according to claim 1, characterized in that: The monitoring circuit also includes a decoupling capacitor C1, a decoupling capacitor C2 and a filter capacitor C3. The filter capacitor C3 is used as a watchdog timeout adjustment capacitor. The monitoring circuit is used to power on and reset the processor when the processor power supply voltage is lower than its normal working voltage.

3. The multifunctional reset circuit according to claim 1, characterized in that: The monitoring circuit further comprises a resistor R2, a resistor R3 and a resistor R4 connected to the MAX791 monitoring chip. The resistance value of the voltage divider of the resistor R2 and the resistor R4 can be adjusted to adapt to the normal power supply voltage range of the processor.

4. The multifunctional reset circuit according to claim 1, characterized in that: The CD4011 NAND gate circuit further includes a decoupling capacitor C4, the input end of the decoupling capacitor C4 is connected to a 3.3V power supply, and the output end of the decoupling capacitor C4 is connected to a power ground DGND.

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