Novel transaction ID coding method applied to AXI protocol

Abstract

The invention belongs to the field of integrated circuit design, and provides a novel transaction ID coding method applied to an AXI protocol. Address decoding is carried out in advance in an AXI host interface, gating signals of all slaves are compiled into transaction IDs in a one-hot code mode, and therefore coding of all transaction IDs can be completed in the host interface instead of expanding the bit width of ID coding step by step in next-level interconnection. The address decoder is located on the critical path of the interconnection matrix in a traditional interconnection architecture, the address decoder is moved into the host interface, the delay of the critical path in the interconnection matrix is shortened, the dominant frequency of the system can be improved, address decoding is not needed in the interconnection matrix any more, combinational logic in the interconnection matrix can be simplified, and the system reliability is improved. The design complexity is reduced, meanwhile, the data cache position needing to be returned in an order-preserving mode can be closer to a host end, the memory access efficiency is improved, and the problem of a memory wall is effectively relieved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, and proposes a novel transaction ID encoding method based on advance address decoding applied in an AXI protocol. Background Art

[0002] The AMBA (Advanced Microcontroller Bus Architecture) protocol is a bus protocol defined by ARM, which aims to provide high-performance, low-power and scalable bus solutions for connecting processors, memory, peripherals and other system components. The AMBA protocol defines a set of bus interface standards, including AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus) and AXI (Advanced eXtensible Interface). The AXI protocol is a high-performance, low-latency and scalable bus protocol in the AMBA protocol. The AXI protocol supports features such as multi-master devices, out-of-order data transmission, out-of-order data transmission, and burst transmission. It aims to provide high performance and flexibility and is suitable for complex SoC designs.

[0003] With the development of processors, the speed of performance improvement has far exceeded the speed of memory access speed improvement. The clock frequency and instruction-level parallelism of processors have been continuously improved, but the access speed of memory has not increased synchronously, which causes the processor to waste a lot of clock cycles while waiting for memory data, resulting in a performance bottleneck, which is called "Memory Wall". The peak computing power of hardware has increased by about 60,000 times in the past 20 years, but the bandwidth growth of DRAM has only increased by 100 times. The existence of the memory wall has a significant impact on the performance of computer systems. The processor needs to frequently read data and instructions from the memory, while the access speed of the memory is relatively slow, resulting in the execution efficiency of the processor being limited. This situation is particularly obvious in large-scale data processing, high-concurrency applications and data-intensive tasks. Improving the efficiency of memory access has become the key to improving the performance of computing systems.

[0004] The AXI protocol has been widely used in on-chip interconnect systems due to its advantages such as high performance, scalability, and low latency. In the traditional AXI architecture, address decoding is generally performed in the interconnect and is used to select the corresponding slave to realize data routing from the host to the slave. Since the performance bottleneck of the current computing system is the memory access efficiency, although the AXI protocol itself is a high-performance, high-bandwidth bus protocol, it is still far from meeting the bandwidth requirements of current high-performance processors. The AXI protocol can achieve out-of-order completion of transactions due to the presence of ID signals in the read channel and the write channel, thereby improving the efficiency of memory access. The protocol stipulates that transactions with the same ID must be returned in order, and transactions with different IDs can be returned out of order, but the bit width and encoding method of the ID are not specified. The bandwidth and main frequency of the AXI bus can be improved at the interconnection hierarchy level by flexibly encoding the AWID and WID signals of the write channel and the ARID and RID signals of the read channel. Figure 1 This is a traditional AXI bus architecture component diagram. The Master component represents the AXI host interface, the Slave component represents the AXI slave interface, and the interconnect is the bus interconnection part, which generally includes three components: decoder, arbitrator, and multiplexer. The arbitrator receives access requests from each host and authorizes the corresponding host to access rights according to the arbitration algorithm when resource competition occurs (multiple hosts request the same bus at the same time). The host that initiates the request but does not obtain access authorization needs to wait for authorization. Common arbitration algorithms include fixed priority arbitration, polling priority arbitration, and weighted polling priority arbitration. The decoder is responsible for translating the request information on the bus into a selection signal according to the mapping. For example, in the AXI protocol that shares data channels and request channels, after the host's read and write request information is sent to the bus through arbitration, the decoder determines which address interval the request belongs to through the address information on the bus, thereby selecting the corresponding slave, and the slave can sample the information on the bus to realize data routing. The multiplexer (mux) drives the corresponding signal to the bus according to the corresponding selection signal. For example, in the write transaction of the AXI4 protocol, after the host initiates a write request and obtains authorization, the multiplexer needs to drive the host's request signal to the bus through the corresponding authorization signal for the slave to sample. In the case of a shared write request channel, only one host's request information should be driven to the bus at the same time until the ready response from the slave is received.

[0005] The key to improving the performance of the AXI protocol compared to the AHB bus is that the AXI protocol supports outstanding transmission, that is, when the previous transmission transaction is not completed, the next transmission transaction is allowed to be initiated, and the two different transmission transactions are distinguished by the X_ID signal. On the basis of outstanding, out of order and interleaving can be further realized. These three functions are collectively called "AXI Three Axes", which can greatly improve the transmission efficiency. For the generation of different transaction IDs, the source ID code is generally generated at the host interface, and the ID code transmitted by the host is expanded by additional information in the interconnection to support more parallel processing of unfinished transactions. Figure 2 It is the traditional AXI system ID encoding method, in which the ID bit width issued by the master is 2 bits, supporting four different transactions running on the bus. The interconnect expands the ID bit width issued by the master to 6 bits to support 64 different transactions running on the bus at the same time. Summary of the invention

[0006] The present invention proposes a novel transaction ID encoding method applied to the AXI protocol. Compared with the traditional transaction ID encoding method, the encoding method can improve the maximum frequency and transmission efficiency of the bus system, achieve the purpose of increasing the system memory bandwidth, and effectively alleviate the memory wall bottleneck problem. Technical Solution

[0007] exist Figure 2In the ID encoding scheme, the interconnection expands the 2-bit ID number sent by the host interface to 6 bits and sends it to the slave interface, which means that there can be up to 64 transactions on the bus that can be completed out of order at the same time (assuming that the encoding method uses binary code instead of one-hot code). But the problem here is that the host can actually only recognize four transactions generated by itself. For example, the host first generates a read transaction with an ID number of 2'b01. The interconnection expands the ID by four bits according to the additional information of this transaction: 4'b0100, so the ID received by the slave is 6 bits: 6'b01_0100, and then the host generates a read transaction with an ID number of 2'b01 again. For some reason, the ID numbers of these two transactions (generated by the host) are the same, but the additional information is different. Therefore, the interconnection can expand the ID to four bits different from the previous transaction: 4'b0010, so the ID of the second transaction received by the slave is 6'b01_0010. From the perspective of the slave, the first transaction ID is 6'b01_0100, and the second transaction ID is 6'b01_0010. These two read transactions have different IDs, and the slave can return the read data of the two transactions out of order. However, the host can only recognize the highest two digits of the six-bit ID. The highest two digits of the ID of these two read transactions are both 2'b01, so for the host, the return order of these two transactions needs to be consistent with the order in which the transactions were issued, that is, the host needs to receive all the return data of the first read transaction before it can start receiving the return data of the second read transaction. In this case, the data of the second read transaction returned out of order by the slave needs to be cached in the interconnect, and the data of the second read transaction will be returned in sequence after all the first read data is returned. In the face of such a situation where order preservation is required, the improvement of the system bandwidth by the out-of-order mechanism is limited, and if the components that need to complete the order preservation function are set in the interconnect, the complexity of the interconnect design and the length of the interconnect critical path will increase, affecting the overall area and performance of the interconnect.

[0008] The present invention proposes a read-write transaction ID encoding method based on the mapping of the host number and the slave address. Compared with the traditional interconnection architecture, the transmission efficiency and main frequency of the interconnection system can be significantly improved. The decoder is generally located in the interconnection matrix. Figure 3It represents the data flow of a general decoder, address[31:16] represents the upper 16 bits of the 32-bit address bus, and slave-sel_x (x=0,1,2) represents the selection signal output by the decoder to the slave. Only one slave can be selected at the same time, and only the selected slave can sample the information flow on the shared channel. The present invention transfers the address decoder to the host interface (Master Interface), completes the address decoding in the host interface, and uses a one-hot code to identify the selection signal of each slave, and then encodes it into the AXI transaction ID. Assuming that the length of X_ID is 6, the present invention defines that the highest two bits of the ID are set as the host number, and the 2-bit host code can be mapped to 4 hosts; the lower four bits of the ID are mapped to the selection signal of the slave in a one-hot code encoding manner, so that no additional decoder is needed in the interconnection, the delay of the critical path in the interconnection can be shortened, the system main frequency can be increased, and the readability of the ID code is improved, and the transmission efficiency of the interconnection system is improved. Taking the 6-bit transaction ID encoding as an example, when ID = 6'b10_0100, the highest 2 bits are 10, which means that the access transaction is initiated by the host No. 2, and the lower four bits are 0100, which means that the access transaction is initiated to the slave No. 2; similarly, ID = 6'b11_0001 represents the access transaction initiated by the host No. 3 to the slave No. 1. This encoding method has another advantage: when the transaction data needs to be returned in order, the data cached by the read transaction can be closer to the master end, improving the efficiency of returning data in order. The traditional ID encoding method generally expands the bit width of the ID transaction initiated by the host in the interconnection. Doing so will increase the number of transactions that need to be sequenced in the interconnection. In the case of a large ID bit width, there are relatively high requirements for the cache capacity of the interconnection. In addition, since the interconnection is the information and data transfer station of the entire system, the control logic will also be relatively complex. The access speed of the memory is determined by the position of the memory relative to the CPU and the memory itself. For the same storage unit, the closer it is to the CPU, the faster the access speed. The ID encoding method proposed in the present invention caches the read transaction data that needs to be returned in order in the host interface (Master Interface). Compared with the traditional method of caching data in the interconnect, the location of the cached data under the structure of the present invention is one level closer to the CPU, and has a higher read transaction return efficiency. In addition, since the data return channels of each host interface are independent of each other, the logic of the order-preserving return transaction is greatly simplified.

[0009] In summary, the present invention proposes a novel transaction ID encoding architecture in the AXI protocol. Compared with the traditional AXI interconnect architecture, the present invention has the following advantages: 1. Decoding logic is no longer needed in the interconnect, and the decoder is moved from the critical path of the interconnect to the non-critical path of the upper level (host interface), which increases the maximum frequency of the interconnect system. 2. Simplified the control logic when transactions in the AXI system need to return in order. 3. The read transaction data cache is closer to the CPU, which improves the CPU's memory access efficiency and can effectively alleviate the memory wall problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The traditional AXI interconnect system architecture shows the basic components of a 2master x 2slave AXI interconnect system.

[0011] Figure 2 This is the encoding method of transaction ID and information flow in the traditional AXI interconnect architecture.

[0012] Figure 3 It is the input and output information of the address decoder in the AXI interconnection system.

[0013] Figure 4 It is the critical path in the traditional AXI interconnect system.

[0014] Figure 5 This is a diagram of the new interconnection system architecture proposed by the present invention.

[0015] Figure 6 In order to verify the feasibility of the functions of the present invention, a system architecture of 4master x4slave based on the present invention is described.

[0016] Figure 7 The waveform diagram is used to verify the function of the architecture of the present invention in the VCS+Verdi joint simulation.

[0017] Figure 8 This is a timing waveform diagram of the AXI write host interface in the architecture of the present invention.

[0018] Fig. 9 This is a screenshot of the global log verified for this architecture.

[0019] Fig.10 Write a channel interconnect DC synthesis timing report for the architecture of the present invention.

[0020] Fig.11 Write a channel interconnect DC comprehensive area report for the present invention architecture.

[0021] Fig.12 The DC integrated timing report of the read channel interconnection of the present invention architecture is provided.

[0022] Fig.13 Read channel interconnect DC comprehensive area report for the present invention architecture. DETAILED DESCRIPTION

[0023] The present invention is further described below with reference to the accompanying drawings and specific examples:

[0024] The present invention can be applied in a bus architecture with high performance and low latency requirements. Figure 4 The critical path in the traditional AXI interconnect is presented. For a fully shared bus structure, the interconnection must pass through an arbiter, a decoder, and a mux (multiplexer). The highest clock frequency that the interconnection can achieve is constrained by this combinatorial logic path. Figure 5 For the data flow path of the architecture of the present invention, the decoder is removed from the interconnection, and the decoding work is transferred to the host interface. This not only simplifies the interconnection structure and removes some unnecessary control logic, making the interconnection logic quite concise, but also is equivalent to moving part of the combinational logic on the critical path of the interconnection to the non-critical path of the host interface, which can increase the system main frequency.

[0025] Figure 6 It is a 4Master x 4Slave AXI interconnection system designed based on the architecture of the present invention. core_x is the behavior model of the CPU end, sending memory access commands to the host interface. master_x is the host interface, receiving memory access commands from the core end, translating the corresponding commands into standard AXI interface timing, sending them to the interconnection, and receiving slave feedback signals and data from the interconnection through the selection signal. slave_x is the AXI slave interface, receiving the AXI timing signal stream from the interconnection, and performing corresponding memory access operations on the memory according to the received signal stream. memory_model is an SRAM memory model, which is addressed as 4Byte, and each byte is selected by a 4-bit wide strobe signal. This block diagram simulates a system in which a core accesses the memory model through the AXI interconnection. The main purpose is to verify the functional correctness and high-efficiency memory access characteristics of the architecture of the present invention.

[0026] Figure 7 This is the global waveform diagram of the above system when it is running. U0~U3 are the memory access request and data waveforms sent by the core end, and S0~S3 are the data flow waveforms received by the slave end. It can be clearly seen from the waveform that the first transaction is U1's access to S0, and the second transaction is U2's access to S1. By analogy, after comparing the sent data packets with the received data packets, the data sent by the core end is consistent with the data packets received by the memory end, which proves that its data routing function is correct.

[0027] Figure 8It is the timing of a write transaction of the host interface. The master1 signal group is the AXI timing signal stream sent by the host No. 1, with the first address 0x0200_0000 and the write transaction ID 0x11, that is, 2'b010001. From the ID code, it can be seen that this is a memory access request from the host No. 1 to the slave No. 0. The s0 signal group is the signal stream received by the slave No. 0, which is consistent with expectations, verifying the feasibility of the encoding scheme of the present invention.

[0028] Fig. 9 This is a screenshot of the read-write simulation verification log for the architecture system of the present invention. The verification process is to initialize a write data packet in the testbench, and then write it into the memory array model. After the writing is completed, a read command is issued by the core end, and all the data are read out in the order of writing, and stored in another data packet. Finally, the two data packets are compared. If the two data packets are completely consistent, it means that the basic read and write memory access functions of this interconnection system are correct.

[0029] Figure 10 to Figure 13 It is the DC synthesis result of the RTL (Verilog) code of the present invention, based on the TMSC 65nm process. Since the AXI protocol read and write channels are completely separated and do not affect each other, they are divided into two modules (read interconnection and write interconnection) for synthesis. Fig.10 This is the timing synthesis report for write interconnect. Under the clock constraint of 200 MHz, the slack is 3.39 ns. Since DC is an inert synthesis tool (using as few buffers and logic with as small driving capability as possible), this synthesis result is conservative. Based on this result, it can be conservatively estimated that the write channel interconnect clock frequency can reach at least 600 MHz under this process. Fig.11 This is a comprehensive report on the interconnect area, with a total area of ​​1434.96 μm 2 . Fig.12 , Fig.13 Read the DC comprehensive report of the interconnection channel. Fig.12 This is the timing synthesis report. Similarly, the clock frequency of the read interconnect channel is conservatively estimated to reach 600 MHz. Fig.13 This is the comprehensive area report. The total area of ​​the read interconnect is 1279.08μm 2 The performance and area of ​​the read-write interconnect system designed by the present invention are very competitive in the 4x4 scale AXI interconnect system.

[0029] The above embodiments have fully explained the necessary technical contents of the present invention, and ordinary technicians can implement them according to the description, so other technical details are not repeated.

Claims

1. A new transaction ID encoding method applied to the AXI protocol, characterized in that Based on advance address decoding, the host number and slave selection signal are encoded as part of the ID information, so that the transaction ID is completely encoded in the host interface, instead of increasing the ID bit width step by step. The high bit of the transaction ID represents the host number, which can be encoded in a one-hot code or a binary code, and the low bit of the transaction ID represents the slave selection signal, which is encoded in a one-hot code. Each bit segment of the transaction ID encoded by this method has a clear meaning, which adjusts the traditional AXI bus interconnection architecture. When the order of reading transaction data needs to be preserved, the location of the cached data is closer to the host end.

2. The conventional AXI bus interconnection architecture as described in claim 1 is adjusted, characterized in that The position of the address decoder in the traditional interconnect architecture is adjusted, and the address decoding logic in the interconnect matrix is ​​transferred to the non-critical path in the host interface. The decoding logic of the traditional AXI interconnect architecture is located on the critical path of the interconnect matrix.

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