Manufacturing method of semiconductor structure

Abstract

The invention relates to a manufacturing method of a semiconductor structure. The method comprises the steps of providing a substrate; forming first mask patterns which extend along the first direction and are arranged at intervals along the second direction; forming second mask patterns, wherein the second mask patterns are arranged at intervals above the first mask patterns along the first direction; etching the first mask pattern according to the second mask pattern, and dividing the first mask pattern into first target patterns arranged at intervals along the first direction; forming third mask patterns which extend along the first direction and are arranged at intervals along the second direction; forming fourth mask patterns, wherein the fourth mask patterns are arranged at intervals above the third mask patterns along the first direction; and etching the third mask pattern according to the fourth mask pattern, and dividing the third mask pattern into second target patterns which are arranged at intervals along the first direction. The pattern density of the first target pattern and the second target pattern is reduced, and the pattern quality of the first target pattern and the second target pattern is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] With the continuous advancement of the development of integrated circuits (ICs), the critical dimensions (CD) of electronic components in integrated circuits are constantly decreasing and the integration density is constantly increasing, so that integrated circuits have a higher degree of integration. The production of electronic components in integrated circuits requires the use of photolithography technology to transfer the pattern from the mask to the silicon wafer. The photolithography process includes an exposure step, a development step after the exposure step, and an etching step after the development step. The increase in the density of electronic components in integrated circuits also increases the difficulty of the photolithography process. The resolution of the current photolithography technology is difficult to meet the manufacturing requirements of integrated circuits, and the process technology of integrated circuits faces huge challenges. Summary of the invention

[0003] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure to address the problem that the resolution of the photolithography technology in the prior art is difficult to meet the manufacturing requirements of integrated circuits.

[0004] In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0005] providing a substrate;

[0006] forming a first mask pattern on the substrate, wherein the first mask pattern extends along a first direction and is arranged at intervals along a second direction perpendicular to the first direction;

[0007] forming a second mask pattern, wherein the second mask patterns are arranged above the first mask pattern at intervals along the first direction;

[0008] Etching the first mask pattern according to the second mask pattern to divide the first mask pattern into first target patterns arranged at intervals along the first direction;

[0009] forming a third mask pattern above the first target pattern, wherein the third mask pattern extends along the first direction, and the third mask patterns are arranged at intervals along the second direction, and the projection of the first mask pattern on the substrate and the projection of the third mask pattern on the substrate have no overlapping area;

[0010] forming a fourth mask pattern, wherein the fourth mask pattern is arranged above the third mask pattern at intervals along the first direction;

[0011] The third mask pattern is etched according to the fourth mask pattern to divide the third mask pattern into second target patterns arranged at intervals along the first direction.

[0012] In one of the embodiments, along the second direction, the projections of the first mask pattern on the substrate and the projections of the third mask pattern on the substrate are arranged alternately.

[0013] In one of the embodiments, a projection of the second mask pattern on the substrate and a projection of the fourth mask pattern on the substrate have no overlapping area.

[0014] In one embodiment, forming a first mask pattern includes:

[0015] forming a first sub-mask pattern, wherein the first sub-mask pattern extends along the first direction and is arranged at intervals along the second direction;

[0016] forming a first mask material layer, wherein the first mask material layer covers the sidewalls and the top surface of the first sub-mask patterns and the area between the first sub-mask patterns, and the first mask material layer comprises a first material;

[0017] The first mask material layer on the top surface of the first sub-mask pattern and the first mask material layer between the first sub-mask patterns are removed, and the first mask material layer covering the sidewalls of the first sub-mask pattern forms the first mask pattern.

[0018] In one embodiment, the first material comprises a semiconductor material, and the first material is doped with a Group IIIA element.

[0019] In one embodiment, forming the second mask pattern includes:

[0020] forming a first photoresist layer above the first mask pattern;

[0021] The first photoresist layer is exposed and developed to form a first pattern hole in the first photoresist layer.

[0022] In one embodiment, forming the second mask pattern further includes:

[0023] forming a second mask material layer, wherein the second mask material layer covers the sidewalls and the bottom wall of the first pattern hole and the top surface of the first photoresist layer;

[0024] The second mask material layer covering the bottom wall of the first pattern hole is removed by etching, and the second mask material layer retained by etching is formed in the first pattern hole to form the second mask pattern.

[0025] In one embodiment, forming the second mask pattern includes:

[0026] forming a second sub-mask pattern, wherein the second sub-mask pattern extends along the second direction and is arranged at intervals along the first direction;

[0027] The second mask pattern is formed on the sidewall of the second sub-mask pattern.

[0028] In one embodiment, the first mask pattern has a first size in the second direction, and adjacent first mask patterns have a second size;

[0029] The third mask pattern has a third size in the second direction, and adjacent third mask patterns have a fourth size;

[0030] The size of the second mask pattern in the second direction is greater than or equal to the first size, and the size of the fourth mask pattern in the second direction is greater than or equal to the third size;

[0031] The first size is smaller than the fourth size, and the third size is smaller than the second size.

[0032] In one embodiment, there is a first spacing between the second mask patterns adjacent to each other in the first direction;

[0033] There is a second interval between the fourth mask patterns adjacent to each other in the first direction, and the first interval is equal to the second interval.

[0034] The method for manufacturing a semiconductor structure of the present invention has the following beneficial effects:

[0035] The method for manufacturing a semiconductor structure of the present invention divides a target pattern to be formed into a first target pattern and a second target pattern, and adopts two processes to form the first target pattern and the second target pattern respectively, thereby reducing the pattern density of forming the first target pattern and the second target pattern, increasing the process window of forming the first target pattern and the second target pattern, and improving the pattern quality of the formed first target pattern and the second target pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1The diagram is a schematic diagram after a sub-mask pattern is formed on a first mask material layer, which is provided as an exemplary comparative example.

[0038] Figure 2 The figure is a schematic diagram after forming a first mask pattern provided as an exemplary comparative example.

[0039] Figure 3 A schematic diagram after forming a second mask pattern and a third mask pattern is provided as an exemplary comparative example.

[0040] Figure 4 A projection diagram of a second mask pattern and a third mask pattern formed on a substrate is provided as an exemplary comparative example.

[0041] Figure 5 FIG. 4 is a schematic diagram of a first mask pattern formed in an exemplary comparative example.

[0042] Figure 6 FIG. 1 is a schematic diagram of an active region formed in an exemplary comparative example.

[0043] Figure 7 A flow chart of a method for manufacturing a semiconductor structure is provided for an exemplary embodiment.

[0044] Figure 8 FIG. 1 is a projection diagram of a first sub-mask pattern formed on a substrate according to an exemplary embodiment.

[0045] Fig. 9 for Figure 8 Cross-sectional view of the AA section.

[0046] Fig.10 FIG. 2 is a cross-sectional view of the AA section after forming the first mask material layer according to an exemplary embodiment.

[0047] Fig.11 It is a cross-sectional view of the AA section after forming the first mask pattern according to an exemplary embodiment.

[0048] Fig.12 FIG. 1 is a projection diagram of a first mask pattern formed on a substrate according to an exemplary embodiment.

[0049] Fig.13 FIG. 1 is a projection diagram of a second mask pattern formed on a substrate according to an exemplary embodiment.

[0050] Fig.14 FIG. 5 is a cross-sectional view of a BB cross section after forming a first photoresist layer according to an exemplary embodiment.

[0051] Fig.15 FIG. 4 is a cross-sectional view of a CC cross section after forming a first photoresist layer according to an exemplary embodiment.

[0052] Fig.16FIG. 5 is a cross-sectional view of a BB cross section after forming a second mask material layer according to an exemplary embodiment.

[0053] Fig.17 FIG. 4 is a cross-sectional view of a CC cross section after forming a second mask material layer according to an exemplary embodiment.

[0054] Fig.18 FIG. 5 is a cross-sectional view of a BB section after forming a second mask pattern according to an exemplary embodiment.

[0055] Fig.19 FIG. 4 is a cross-sectional view of a CC section after forming a second mask pattern according to an exemplary embodiment.

[0056] Fig. 20 FIG. 1 is a projection diagram of a second mask pattern formed on a substrate according to an exemplary embodiment.

[0057] Fig.21 FIG. 4 is a cross-sectional view of a DD cross section after forming a second sub-mask pattern according to an exemplary embodiment.

[0058] Fig. 22 FIG. 4 is a cross-sectional view of a DD cross section after forming a second mask material layer according to an exemplary embodiment.

[0059] Fig.23 It is a cross-sectional view of the DD cross section after forming the third sub-mask material layer according to an exemplary embodiment.

[0060] Fig.24 FIG. 4 is a cross-sectional view of a DD cross section after forming a second mask pattern according to an exemplary embodiment.

[0061] Fig.25 FIG. 5 is a cross-sectional view of the EE section after forming the second mask pattern according to an exemplary embodiment.

[0062] Fig.26 FIG. 4 is a cross-sectional view of a DD section after forming a first target pattern according to an exemplary embodiment.

[0063] Fig. 27 FIG. 5 is a cross-sectional view of an EE section after forming a first target pattern according to an exemplary embodiment.

[0064] Fig.28 FIG. 1 is a projection diagram of a first target pattern formed on a substrate according to an exemplary embodiment.

[0065] Fig.29 FIG. 1 is a projection diagram of a fourth sub-mask pattern formed on a substrate according to an exemplary embodiment.

[0066] Fig.30 for Fig.29 Cross-sectional view of the FF section.

[0067] Fig.31FIG. 4 is a cross-sectional view of a FF cross section after forming a third mask material layer according to an exemplary embodiment.

[0068] Fig.32 FIG. 4 is a cross-sectional view of a FF cross section after forming a third mask pattern according to an exemplary embodiment.

[0069] Fig.33 FIG. 1 is a projection diagram of a third mask pattern formed on a substrate according to an exemplary embodiment.

[0070] Fig.34 FIG. 1 is a projection diagram of a fourth mask pattern formed on a substrate according to an exemplary embodiment.

[0071] Fig.35 FIG. 1 is a projection diagram of a fourth mask pattern formed on a substrate according to an exemplary embodiment.

[0072] Fig.36 FIG. 1 is a projection diagram of a second target pattern formed on a substrate according to an exemplary embodiment.

[0073] Fig.37 for Fig.36 Cross-sectional view of the GG section.

[0074] Fig.38 for Fig.36 Cross-sectional view of the HH section.

[0075] Fig.39 FIG. 1 is a top view of a substrate after forming an active region according to an exemplary embodiment.

[0076] Description of reference numerals:

[0077] 10. substrate; 101. shallow trench; 102. active area; 11. first target pattern; 12. second target pattern; 120. first hard mask layer; 130. first sub-mask pattern; 140. first mask pattern; 141. first mask material layer; 150. first dielectric layer; 160. first photoresist layer; 161. first pattern hole; 220. second hard mask layer; 230. second sub-mask pattern; 240. second mask pattern; 241. second mask material layer; 250. second dielectric layer; 331. third sub-mask material layer; 340. third mask pattern; 341. third mask material layer; 430. fourth sub-mask pattern; 440. fourth mask pattern;

[0078] D1, first direction; D2, second direction;

[0079] D1, first size; d2, second size; d3, third size; d4, fourth size; L1, first spacing; L2, second spacing;

[0080] 1', substrate; 2', hard mask layer; 3', first mask pattern; 31', first mask material layer; 4', second mask pattern; 5', third mask pattern; 7', sub-mask pattern. DETAILED DESCRIPTION

[0081] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0082] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0083] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0084] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0085] In the current semiconductor structure manufacturing process, in the process of forming high-density, small-size devices, the self-aligned quadruple patterning technology (Self-Aligned Quadruple Pattern, SAQP) is usually used. With the development of semiconductor technology, the critical dimensions of semiconductor devices are required to be smaller and smaller, and the integration density is required to be higher and higher. However, the number of masks used in the self-aligned quadruple patterning technology is large, and the overlay accuracy between the masks is difficult to control. The formed mask pattern has pattern defects, such as pattern collapse, critical dimension uniformity (CDU), line edge roughness (LER), line width roughness (LWR) or poor pitch uniformity.

[0086] Taking the formation of an active area (Active, AA) as an example for explanation, in the related art, the following implementation methods are adopted in the process of forming the active area:

[0087] First, refer to Figure 1 As shown, a substrate 1' is provided, and a hard mask layer 2' is formed on the top surface of the substrate 1'. A first mask material layer 31' is formed on the hard mask layer 2', and the first mask material layer 31' covers the hard mask layer 2'. Sub-mask patterns 7' are formed on the first mask material layer 31', and the sub-mask patterns 7' extend along a first direction D1 and are arranged at intervals along a second direction D2 perpendicular to the first direction D1. Figure 2 As shown, the first mask material layer 31' is etched according to the sub-mask pattern 7' to form the first mask pattern 3'.

[0088] Next, refer to Figure 3 , Figure 4As shown, a second mask pattern 4' and a third mask pattern 5' are formed on the first mask pattern 3' by using a self-aligned quadruple pattern technology, and the second mask pattern 4' and the third mask pattern 5' intersect to form a cross hole on the first mask pattern 3'. The first mask pattern 3' is etched according to the second mask pattern 4' and the third mask pattern 5', and the cross hole is transferred to the first mask pattern 3', thereby dividing the first mask pattern 3' into a target pattern.

[0089] In the related art, the second mask pattern 4' and the third mask pattern 5' are formed by the self-aligned quadruple pattern technology. The line width uniformity, line edge roughness, line width roughness or pitch uniformity of the cross holes formed by the second mask pattern 4' and the third mask pattern 5' are poor. The sub-mask pattern 7' has a large pattern density and a small size, which may cause a "dog tooth" defect on the top of the sub-mask pattern 7'. The first mask pattern 3' is usually formed of polysilicon, which has poor etching resistance. Figure 2 or Figure 5 As shown in the A area, the first mask pattern 3' may be tilted or adjacent first mask patterns 3' may be connected together, resulting in under-etching (under etch) at the bottom of the position where the first mask pattern 3' is tilted or connected when the substrate 1' is subsequently etched according to the target pattern. Referring to the B area in 6, the pattern quality of the formed active area is affected, and the problem of under-etching is difficult to alleviate by increasing the etching amount.

[0090] In view of this, the present application provides a method for manufacturing a semiconductor structure, providing a substrate; forming a first mask pattern on the substrate, the first mask pattern extending along a first direction, and the first mask pattern is arranged at intervals along a second direction perpendicular to the first direction; forming a second mask pattern, the second mask pattern is arranged at intervals above the first mask pattern along the first direction; etching the first mask pattern according to the second mask pattern, dividing the first mask pattern into first target patterns arranged at intervals along the first direction; forming a third mask pattern above the first target pattern, the third mask pattern extending along the first direction, the third mask pattern is arranged at intervals along the second direction, and the projection of the first mask pattern on the substrate and the projection of the third mask pattern on the substrate have no overlapping area; forming a fourth mask pattern, the fourth mask pattern is arranged at intervals above the third mask pattern along the first direction; etching the third mask pattern according to the fourth mask pattern, dividing the third mask pattern into second target patterns arranged at intervals along the first direction. The present application splits the target pattern to be formed into a first target pattern and a second target pattern, and forms the first target pattern and the second target pattern in two different mask layers, respectively, thereby reducing the pattern density of the first target pattern and the second target pattern, and improving the pattern quality of the first target pattern and the second target pattern. For example, the line width uniformity, line edge roughness and line width roughness of the first target pattern and the second target pattern are better.

[0091] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 7 As shown, Figure 7 A flowchart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. Figure 8-Figure 39 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 8-Figure 39 And refer to Figure 7 The manufacturing method of the semiconductor structure of this embodiment is introduced. This embodiment does not limit the semiconductor structure. The semiconductor structure as an active area will be taken as an example for introduction below, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.

[0092] like Figure 7 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0093] Step S110: providing a substrate.

[0094] Step S120: forming a first mask pattern on the substrate, wherein the first mask pattern extends along a first direction and is arranged at intervals along a second direction perpendicular to the first direction.

[0095] Step S130: forming a second mask pattern, wherein the second mask patterns are arranged above the first mask pattern at intervals along the first direction.

[0096] Step S140: etching the first mask pattern according to the second mask pattern to divide the first mask pattern into first target patterns arranged at intervals along a first direction.

[0097] Step S150: forming a third mask pattern above the first target pattern, the third mask pattern extending along the first direction, the third mask pattern arranged at intervals along the second direction, and the projection of the first mask pattern on the substrate and the projection of the third mask pattern on the substrate have no overlapping area.

[0098] Step S160: forming fourth mask patterns, wherein the fourth mask patterns are arranged above the third mask patterns at intervals along the first direction.

[0099] Step S170: etching the third mask pattern according to the fourth mask pattern to divide the third mask pattern into second target patterns arranged at intervals along the first direction.

[0100] In step S110, refer to Fig. 9 As shown, the base 10 can be a semiconductor substrate, which is made of a semiconductor material, and the semiconductor material can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials with semiconductor properties, such as III-V compounds such as gallium arsenide.

[0101] Alternatively, the substrate 10 may be other material layers used to form semiconductor devices, such as a dielectric layer or a metal layer, etc. For example, the substrate 10 may be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited thereto.

[0102] Before step S120, the following steps are also performed: Figure 8 , Fig. 9 As shown, a first hard mask layer 120 is formed on the substrate 10, and a hard mask material can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form the first hard mask layer 120, and the first hard mask layer 120 covers the top surface of the substrate 10. The material of the first hard mask layer 120 may include nitride, oxynitride or oxide, for example, the material of the first hard mask layer 120 may include silicon nitride. It is understood that the first hard mask layer 120 may include a single layer or a multi-layer structure.

[0103] In step S120, a first mask pattern is formed on the substrate, and the following implementation methods may be adopted:

[0104] Step S121: forming a first sub-mask pattern, wherein the first sub-mask pattern extends along the first direction and is arranged at intervals along the second direction.

[0105] First, a chemical vapor deposition process or a physical vapor deposition process may be used to deposit a first sub-mask material layer (not shown in the figure), and the first sub-mask material layer covers the first hard mask layer 120 (refer to Fig. 9 The material of the first sub-mask material layer may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0106] Then, a photoresist material layer (not shown in the figure) is formed on the top surface of the first sub-mask material layer, the photoresist material layer is shielded by a light-shielding mask, and the photoresist material layer is exposed and developed to transfer the mask pattern of the light-shielding mask to the photoresist material layer to form a photoresist mask, and then the undeveloped photoresist material layer is removed.

[0107] Reference Figure 8 , Fig. 9 As shown, the first sub-mask material layer is then etched according to the photoresist mask to form a plurality of first sub-mask patterns 130. The first sub-mask patterns 130 extend along the first direction D1 and are arranged at intervals along the second direction D2.

[0108] Step S122: forming a first mask material layer, the first mask material layer covers the sidewalls and the top surface of the first sub-mask pattern and the area between the first sub-mask patterns, and the first mask material layer includes a first material.

[0109] like Fig.10 As shown, refer to Fig. 9 , an atomic layer deposition process (ALD) can be used to deposit the first material, and the first material covers the first sub-mask pattern 130 and the exposed top surface of the first hard mask layer 120 to form a first mask material layer 141. The atomic layer deposition process is used to form the first mask material layer 141, and the thickness of the first mask material layer 141 can be more accurately controlled, so that the thickness of the formed first mask material layer 141 is smaller, which is conducive to forming a pattern with higher density.

[0110] The first material includes a semiconductor material, and the first material is doped with a Group IIIA element. For example, the first material may include single crystal silicon or polycrystalline silicon, and the first material is doped with at least one of boron or aluminum. In this embodiment, the first material includes polycrystalline silicon doped with boron or aluminum, and the polycrystalline silicon doped with boron or aluminum has better etching resistance.

[0111] Step S123: removing the first mask material layer on the top surface of the first sub-mask pattern and the first mask material layer between the first sub-mask patterns, and the first mask material layer covering the sidewalls of the first sub-mask pattern to form a first mask pattern.

[0112] like Fig.11 , Fig.12 As shown, refer to Figure 8 , Fig.10 The first mask material layer 141 is etched by an anisotropic etching process, wherein the etching speed of the anisotropic etching process in the vertical direction is greater than the etching speed in the horizontal direction, and the first mask material layer 141 covering the top surface of the first sub-mask pattern 130 and the first mask material layer 141 covering the top surface of the first hard mask layer 120 are removed, and the first mask material layer 141 covering the sidewall of the first sub-mask pattern 130 forms the first mask pattern 140. The first mask pattern 140 has a first size d1 in the second direction D2, and a second size d2 is provided between adjacent first mask patterns 140.

[0113] In this embodiment, the first mask material layer 141 includes a first material, which is polysilicon doped with boron or aluminum. The first material has good etching resistance. Thus, the upper and lower line widths of the first mask pattern 140 formed by anisotropic etching are equal, and the first mask pattern 140 has high graphic accuracy and few graphic defects.

[0114] Next, the first sub-mask patterns 130 are removed by etching to expose the top surface of the first hard mask layer 120 between the first mask patterns 140 .

[0115] In step S130, Fig.13 or Fig. 20 As shown, a second mask pattern 240 is formed, and the second mask patterns 240 are arranged above the first mask pattern 140 along the first direction D1, and there is a first spacing L1 between adjacent second mask patterns 240 in the first direction D1. Fig.13 As shown, the second mask pattern 240 may be pattern holes arranged at intervals along the second direction D2, or, in some examples, as shown in FIG. Fig. 20 As shown, the second mask pattern 240 may be a linear pattern extending along the second direction D2.

[0116] In some embodiments, the second mask pattern 240 may be formed by the following implementations:

[0117] Step S131a: forming a first photoresist layer above the first mask pattern.

[0118] Fig.14 BB after forming the first photoresist layer 160 (refer to Fig.13 ) cross-sectional view, Fig.15 The CC after forming the first photoresist layer 160 is shown (refer to Fig.13 ) section view.

[0119] like Fig.14 , Fig.15 As shown, first, a dielectric material is deposited to cover the first mask pattern 140 and fill the gaps between the first mask patterns 140 to form a first dielectric layer 150. A second hard mask layer 220 is deposited to form the second hard mask layer 220, which covers the top surface of the first dielectric layer 150. The material of the first dielectric layer 150 may include silicon oxide, and the material of the second hard mask layer 220 may include silicon nitride and / or silicon oxynitride. Next, a photoresist is coated on the top surface of the second hard mask layer 220 to form a first photoresist layer 160.

[0120] Step S132a: exposing and developing the first photoresist layer to form a first pattern hole in the first photoresist layer.

[0121] like Fig.14 , Fig.15 As shown, the first photoresist layer 160 is exposed and developed to form a first pattern hole 161 in the first photoresist layer 160, and then the undeveloped first photoresist layer 160 is removed.

[0122] In some embodiments, forming the second mask pattern further includes the following steps:

[0123] Step S133a: forming a second mask material layer, wherein the second mask material layer covers the sidewalls and the bottom wall of the first pattern hole and the top surface of the first photoresist layer.

[0124] like Fig.16 , Fig.17 As shown, refer to Fig.14 , Fig.15 The second mask material layer 241 may be deposited by an atomic layer deposition process, and the second mask material layer 241 covers the sidewalls of the first pattern hole 161, the top surface of the first photoresist layer 160, and the top surface of the second hard mask layer 220 exposed by the first pattern hole 161. The material of the second mask material layer 241 may include silicon oxide or silicon nitride.

[0125] Step S134a: etching and removing the second mask material layer covering the bottom wall of the first pattern hole, and etching the retained second mask material layer to form a second mask pattern in the first pattern hole.

[0126] like Fig.18 , Fig.19 As shown, refer to Fig.16 , Fig.17The second mask material layer 241 is etched by an anisotropic etching process. The etching speed of the anisotropic etching process in the vertical direction is greater than the etching speed in the horizontal direction. The second mask material layer 241 covering the top surface of the first photoresist layer 160 and the second mask material layer 241 covering the second hard mask layer 220 are removed by etching. The second mask material layer 241 covering the side wall of the first graphic hole 161 is etched and retained to form a second mask graphic 240.

[0127] Reference Fig.13 As shown, the second mask pattern 240 formed in this embodiment is a pattern hole, and the second mask pattern 240 is arranged at intervals along the first direction D1 and the second direction D2. The size of the second mask pattern 240 in the second direction D2 is larger than the first size d1 of the first mask pattern 140 in the second direction D2, so that the first mask pattern 140 can be subsequently etched according to the second mask pattern 240 and the second mask pattern 240 is transferred to the first mask pattern 140, so that the first mask pattern 140 can be divided into first target patterns 11 that are independent and spaced along the first direction D1 (which will be described in detail in subsequent steps).

[0128] In some other embodiments, the second mask pattern 240 may be formed by the following implementations:

[0129] Step S131b: forming a second sub-mask pattern, wherein the second sub-mask pattern extends along the second direction and is arranged at intervals along the first direction.

[0130] Fig.21 DD after forming the second sub-mask pattern 230 (refer to Fig. 20 ) section, such as Fig.21 As shown, in this embodiment, the dielectric material is deposited to cover the first mask pattern 140 and fill the gaps between the first mask patterns 140 to form the first dielectric layer 150. Then, the second hard mask layer 220 is deposited to cover the top surface of the first dielectric layer 150.

[0131] Then, a second sub-mask material layer (not shown) is formed on the second hard mask layer 220, and the second sub-mask material layer is etched to form a second sub-mask pattern 230 (eg, Fig.21 As shown), the second sub-mask patterns 230 extend along the second direction D2, and the second sub-mask patterns 230 are arranged at intervals along the first direction D1.

[0132] Step S132b: forming a second mask pattern on the sidewall of the second sub-mask pattern.

[0133] like Fig. 22 As shown, refer to Fig.21First, a second mask material layer 241 is formed, and the second mask material layer 241 covers the top surface and the sidewalls of the second sub-mask patterns 230 and the top surface of the second hard mask layer 220 located between the second sub-mask patterns 230 .

[0134] like Fig.23 As shown, refer to Fig. 22 Then, a third sub-mask material layer 331 is deposited to cover the second mask material layer 241 and fill the unfilled areas between the second sub-mask patterns 230 .

[0135] Fig.24 DD after forming the second mask pattern 240 (refer to Fig. 20 ) cross-sectional view, Fig.25 The EE after forming the second mask pattern 240 (refer to Fig. 20 ) section, such as Fig.24 , Fig.25 As shown, refer to Fig.23 Then, the third sub-mask material layer 331 is ground to expose the top surface of the second mask material layer 241. The second mask material layer 241 covering the sidewall of the second sub-mask pattern 230 is removed by etching, and the second mask pattern 240 is formed in the removed area of ​​the second mask material layer 241.

[0136] Reference Fig. 20 As shown, the second mask pattern 240 formed in this embodiment is a linear pattern extending along the second direction D2, which can ensure that when the first mask pattern 140 is subsequently etched according to the second mask pattern 240, the second mask pattern 240 is transferred to the first mask pattern 140, and the first mask pattern 140 can be divided into first target patterns 11 that are independent and spaced apart along the first direction D1 (which will be described in detail in subsequent steps).

[0137] In step S140, if Fig.26 , Fig. 27 , Fig.28 As shown, refer to 13, Fig. 20 , using the second mask pattern 240 as a mask, the second hard mask layer 220, the first dielectric layer 150 and the first mask pattern 140 are etched layer by layer, and the second hard mask layer 220, the first dielectric layer 150 and the first mask pattern 140 exposed by the second mask pattern 240 are removed until the surface of the first hard mask layer 120 is exposed, and the second mask pattern 240 is transferred to the first mask pattern 140, and the first mask pattern 140 is divided into first target patterns 11 arranged at intervals along the first direction D1.

[0138] In step S150 , the implementation method of forming the third mask pattern 340 in this embodiment is the same as the implementation method of forming the first mask pattern 140 in step S120 .

[0139] First, refer to Fig.30 As shown, a second dielectric layer 250 is formed, and the second dielectric layer 250 fills the gaps between the first target patterns 11 and covers the first target patterns 11. Fig.29 , Fig.30 As shown, then, a fourth sub-mask pattern 430 is formed on the second dielectric layer 250, the fourth sub-mask pattern 430 extends along the first direction D1, and the fourth sub-mask pattern 430 is arranged at intervals along the second direction D2. Fig.31 As shown, a third mask material layer 341 is formed, and the third mask material layer 341 covers the sidewalls and the top surface of the fourth sub-mask pattern 430 and the top surface of the second dielectric layer 250. Then, the third mask material layer 341 covering the top surface of the fourth sub-mask pattern 430 and the third mask material layer 341 covering the top surface of the second dielectric layer 250 are removed by etching. Fig.32 , Fig.33 As shown, the third mask material layer 341 on the sidewall of the fourth sub-mask pattern 430 forms a third mask pattern 340 .

[0140] The material of the third mask pattern 340 includes a first material, the first material includes a semiconductor material, and the first material is doped with a group IIIA element. For example, the first material may include single crystal silicon or polycrystalline silicon, and the first material is doped with at least one of boron or aluminum. In this embodiment, the first material includes polycrystalline silicon doped with boron or aluminum, and the polycrystalline silicon doped with boron or aluminum has better etching resistance. The upper and lower line widths of the third mask pattern 340 formed in this embodiment are equal, and the third mask pattern 340 has high graphic accuracy and few graphic defects.

[0141] In this embodiment, refer to Fig.12 , Fig.33 As shown, the projection formed by the first mask pattern 140 on the substrate 10 and the projection formed by the third mask pattern 340 on the substrate 10 have no overlapping area. For example, the projection formed by the first mask pattern 140 on the substrate 10 and the projection formed by the third mask pattern 340 on the substrate 10 can be arranged at intervals according to a preset rule, or the projection formed by the first mask pattern 140 on the substrate 10 falls in one area of ​​the substrate 10, and the projection formed by the third mask pattern 340 on the substrate 10 falls in another area of ​​the substrate 10.

[0142] In this embodiment, along the second direction D2, the projection formed by the first mask pattern 140 on the substrate 10 and the projection formed by the third mask pattern 340 on the substrate 10 are arranged alternately. The third mask pattern 340 has a third size d3 in the second direction D2, and there is a fourth size d4 between adjacent third mask patterns 340, the first size d1 is smaller than the fourth size d4, and the third size d3 is smaller than the second size d2. In this way, it can be ensured that the projection formed by the first mask pattern 140 on the substrate 10 is located between the projections formed by two adjacent third mask patterns 340 on the substrate 10, and the projection formed by the third mask pattern 340 on the substrate 10 is located between the projections formed by two adjacent first mask patterns 140 on the substrate 10, and the first mask pattern 140 and the third mask pattern 340 form a dense pattern array.

[0143] In step S160, the implementation method of forming the fourth mask pattern 440 in this embodiment is the same as the implementation method of forming the second mask pattern 240 in step S130. Fig.34 or Fig.35 As shown, the fourth mask pattern 440 is arranged at intervals above the third mask pattern 340 along the first direction D1, and there is a second spacing L2 between the adjacent fourth mask patterns 440 in the first direction D1, and the first spacing L1 and the second spacing L2 are equal. The size of the fourth mask pattern 440 in the second direction D2 is greater than the third size d3 of the third mask pattern 340 in the second direction D2, wherein the fourth mask pattern 440 may be pattern holes arranged at intervals along the second direction D2, or the fourth mask pattern 440 may be a linear pattern extending along the second direction D2.

[0144] In step S170, refer to Fig.36 , Fig.37 , Fig.38 As shown, the third mask pattern 340 is etched using the fourth mask pattern 440 as a mask, and the fourth mask pattern 440 is transferred into the third mask pattern 340, so that the third mask pattern 340 is divided into second target patterns 12 arranged at intervals along the first direction D1.

[0145] In some embodiments, the projection of the second mask pattern 240 on the substrate 10 and the projection of the fourth mask pattern 440 on the substrate 10 have no overlapping area, so that the first target pattern 11 and the second target pattern 12 formed in this embodiment are spaced and staggered.

[0146] The method for manufacturing the semiconductor structure of the present embodiment divides the target pattern to be formed into a first target pattern and a second target pattern, and adopts two similar processes to form the first target pattern and the second target pattern respectively, thereby reducing the pattern density of forming the first target pattern and the second target pattern, increasing the process window for forming the first target pattern and the second target pattern, and improving the pattern quality of the formed first target pattern and the second target pattern. For example, the line width uniformity, line edge roughness and line width roughness of the first target pattern and the second target pattern are better. At the same time, the present embodiment adopts two similar processes to form the first target pattern and the second target pattern, which reduces the manufacturing difficulty and reduces the number of mask layers used in the manufacturing process to less than 20 layers, thereby saving process costs.

[0147] The method for manufacturing the semiconductor structure of the present embodiment adopts a first material to form a first mask pattern, and the first material has good etching resistance, so that the formed first mask pattern has equal width at the top and bottom and has no structural defects, and avoids the problem of the first mask pattern being tilted or adjacent first mask patterns being connected together, thereby avoiding the problem of under-etching at the bottom caused by the tilt or adhesion of the first mask pattern. Similarly, the present embodiment adopts the first material to manufacture the third mask pattern, and avoids the problem of the third mask pattern being tilted or adjacent first mask patterns being connected together, thereby avoiding the problem of under-etching at the bottom caused by the tilt or adhesion of the third mask pattern. In this way, the first target pattern and the second target pattern formed in the present embodiment have higher graphic accuracy, can reduce the graphic defects formed by subsequent etching of the substrate according to the first target pattern and the second target pattern, and improve the accuracy and clarity of the pattern formed in the substrate.

[0148] The method for manufacturing the semiconductor structure of the present embodiment adopts a self-aligned double patterning technology (Self-Aligned Double Pattern, SADP) to form a first mask pattern, adopts the self-aligned double patterning technology to form a second mask pattern above the first mask pattern, and then transfers the second mask pattern to the first mask pattern to form a first target pattern. The self-aligned double patterning technology can achieve excellent line width and pitch control effects. Thus, the first target pattern formed in the present embodiment has better line width uniformity, line edge roughness, line width roughness and pitch uniformity; similarly, the second target pattern formed in the present embodiment has better line width uniformity, line edge roughness, line width roughness and pitch uniformity. The first target pattern and the second target pattern can form a pattern array with higher pattern quality and greater density.

[0149] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment. This embodiment includes all the steps of the above embodiment. The difference between this embodiment and the above embodiment is that after step S170, this embodiment further performs the following steps:

[0150] Step S180: etching the substrate according to the first target pattern and the second target pattern.

[0151] In this embodiment, refer to Fig.26 , Fig.36 , Fig.39 As shown, the first hard mask layer 120 is patterned according to the first target pattern 11 and the second target pattern 12 to transfer the first target pattern 11 and the second target pattern 12 to the first hard mask layer 120. Then, the substrate 10 is etched according to the patterned first hard mask layer 120 to remove a portion of the substrate 10 to form shallow trenches 101 in the substrate 10, and the shallow trenches 101 divide the substrate 10 into active areas 102 arrayed along the first direction D1.

[0152] The method for manufacturing the semiconductor structure of the present embodiment reduces the problem of adhesion of the first mask pattern and the third mask pattern, and avoids the problem of under-etching at the bottom of the position where the first mask pattern adheres or the position where the third mask pattern adheres during the process of etching the substrate according to the first target pattern and the second target pattern, thereby improving the morphology of the formed active area, and the line width uniformity, line edge roughness, line width roughness and pitch uniformity of the active area are better.

[0153] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: providing a substrate; forming a first mask pattern on the substrate, wherein the first mask pattern extends along a first direction and is arranged at intervals along a second direction perpendicular to the first direction; forming a second mask pattern, wherein the second mask patterns are arranged above the first mask pattern at intervals along the first direction; Etching the first mask pattern according to the second mask pattern to divide the first mask pattern into first target patterns arranged at intervals along the first direction; forming a third mask pattern above the first target pattern, wherein the third mask pattern extends along the first direction, and the third mask patterns are arranged at intervals along the second direction, and the projection of the first mask pattern on the substrate and the projection of the third mask pattern on the substrate have no overlapping area; forming a fourth mask pattern, wherein the fourth mask pattern is arranged above the third mask pattern at intervals along the first direction; The third mask pattern is etched according to the fourth mask pattern to divide the third mask pattern into second target patterns arranged at intervals along the first direction.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Along the second direction, the projections of the first mask pattern on the substrate and the projections of the third mask pattern on the substrate are arranged alternately.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The projection of the second mask pattern on the substrate and the projection of the fourth mask pattern on the substrate have no overlapping area.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a first mask pattern, comprising: forming a first sub-mask pattern, wherein the first sub-mask pattern extends along the first direction and is arranged at intervals along the second direction; forming a first mask material layer, wherein the first mask material layer covers the sidewalls and the top surface of the first sub-mask patterns and the area between the first sub-mask patterns, and the first mask material layer comprises a first material; The first mask material layer on the top surface of the first sub-mask pattern and the first mask material layer between the first sub-mask patterns are removed, and the first mask material layer covering the sidewalls of the first sub-mask pattern forms the first mask pattern.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that: The first material includes a semiconductor material, and the first material is doped with a Group IIIA element.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a second mask pattern, comprising: forming a first photoresist layer above the first mask pattern; The first photoresist layer is exposed and developed to form a first pattern hole in the first photoresist layer.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: Forming a second mask pattern also includes: forming a second mask material layer, wherein the second mask material layer covers the sidewalls and the bottom wall of the first pattern hole and the top surface of the first photoresist layer; The second mask material layer covering the bottom wall of the first pattern hole is removed by etching, and the second mask material layer retained by etching is formed in the first pattern hole to form the second mask pattern.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming a second mask pattern, comprising: forming a second sub-mask pattern, wherein the second sub-mask pattern extends along the second direction and is arranged at intervals along the first direction; The second mask pattern is formed on the sidewall of the second sub-mask pattern.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first mask pattern has a first size in the second direction, and adjacent first mask patterns have a second size; The third mask pattern has a third size in the second direction, and adjacent third mask patterns have a fourth size; The size of the second mask pattern in the second direction is greater than or equal to the first size, and the size of the fourth mask pattern in the second direction is greater than or equal to the third size; The first size is smaller than the fourth size, and the third size is smaller than the second size.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: There is a first spacing between the second mask patterns adjacent to each other in the first direction; There is a second interval between the fourth mask patterns adjacent to each other in the first direction, and the first interval is equal to the second interval.

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