Wafer pattern measurement method and system, equipment and storage medium

Abstract

A wafer pattern measurement method, system and device, and a storage medium, the wafer pattern measurement method comprising: obtaining a verification result of optical proximity correction verification processing of a corrected layout, the verification result comprising coordinates of weak points; obtaining a critical overlapping distance between the measuring point and the adjacent measuring view field based on the coordinates of the weak point and the measuring view field; the measurement points are removed, so that other measurement points, located within the critical overlapping distance, around the measurement points are removed, and the remaining measurement points are used as processed measurement points; and measuring a pattern formed on the wafer based on the processed measurement point to obtain a measurement result. According to the embodiment of the invention, the accuracy of a measurement result is improved, the data processing difficulty is greatly reduced, and the working efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a wafer pattern measurement method and system, equipment and storage medium. Background Art

[0002] With the development of semiconductor technology and the reduction of critical device dimensions, the number and density of patterns on the layout are also increasing significantly. After the patterns on the mask are transferred to the photoresist and wafer, capturing defects on the full chip becomes a reliable means of inspecting image exposure quality and etching quality.

[0003] For more advanced nodes, measurement equipment is used to directly measure key dimensions of the photoresist and graphics on the wafer. Graphic placement analysis is also performed based on electron beam image and contour extraction, and the graphics are accurately superimposed with the layout to accurately capture the environmental structure and morphological dimensions of the defects.

[0004] However, currently there is a problem of large measurement errors when measuring patterns on wafers. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a wafer pattern measurement method and system, equipment and storage medium, so as to improve the accuracy of the measurement results, greatly reduce the difficulty of data processing and improve work efficiency.

[0006] To solve the above problems, an embodiment of the present invention provides a method for measuring wafer graphics, including: obtaining a verification result of an optical proximity effect correction verification process of a corrected layout, the verification result including the coordinates of a weak point; based on the coordinates of the weak point and the measurement field of view, obtaining a critical overlap distance between a measurement point and an adjacent measurement field of view; performing a clearing process on the measurement point to remove other measurement points around the measurement point that are within the critical overlap distance, and the remaining measurement points are used as processed measurement points; based on the processed measurement points, measuring the graphics formed on the wafer to obtain a measurement result.

[0007] Correspondingly, an embodiment of the present invention further provides a wafer graphics measurement system, comprising: an acquisition module, used to obtain the verification result of the optical proximity effect correction verification processing of the corrected layout, the verification result including the coordinates of the weak point; a distance calculation module, used to obtain the critical overlap distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view; a clearing module, used to perform a clearing process on the measurement point, used to remove other measurement points around the measurement point that are within the critical overlap distance, and the remaining measurement points are used as processed measurement points; a measurement module, used to measure the graphics formed on the wafer based on the processed measurement points to obtain measurement results.

[0008] Correspondingly, an embodiment of the present invention also provides a device, comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the wafer graphics measurement method provided by an embodiment of the present invention.

[0009] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the wafer pattern measurement method provided by the embodiment of the present invention.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] In the wafer graphics measurement method provided by the embodiment of the present invention, based on the coordinates of the weak point and the measurement field of view, a critical overlapping distance between the measurement point and the adjacent measurement field of view is obtained; the measurement point is cleared to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, in the step of measuring the graphics formed on the wafer based on the processed measurement points, not only the number of measurement points can be reduced, but also the problem of overlapping between the measurement fields of adjacent measurement points can be prevented, thereby ensuring that all graphics within the measurement field of view are bombarded by the scanning electron beam only once, preventing the graphics in the overlapping area from being repeatedly bombarded by the scanning electron beam and being deformed and damaged, resulting in inaccurate measurement results, and correspondingly improving the accuracy of the measurement results. There is no need to select and process the measurement results of repeated measurement points in the future, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0012] In an optional scheme, the wafer graphics measurement method also includes: after obtaining the critical overlapping distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view, and before clearing the measurement point, screening the measurement point to select all measurement points with measurement points within the surrounding critical overlapping distance as measurement points to be processed, so that only the measurement points to be processed can be processed subsequently, which is conducive to simplifying the number of measurement points to be processed, and correspondingly simplifying the subsequent measurement steps and simplifying the data processing volume, thereby further improving work efficiency.

[0013] In an optional scheme, the step of clearing the measurement points includes: performing block processing on the corrected layout to divide the corrected layout into a plurality of block units arranged in an array; performing clearing processing on the measurement points in the block units and at the boundaries of adjacent block units to remove other measurement points around the measurement points that are within the critical overlapping distance; by dividing the corrected layout into a plurality of block units arranged in an array, the number of measurement points to be cleared in each block unit and at adjacent block units can be reduced in the step of clearing the measurement points, and it is also beneficial to clear the measurement points in a plurality of block units at the same time or at the boundaries of a plurality of adjacent block units at the same time, thereby improving the efficiency of the clearing processing and reducing the processing time.

[0014] In an optional solution, the step of performing a clearing process on the measurement points in the block unit and at the boundaries of adjacent block units includes: based on the process window size corresponding to the measurement point, performing a priority sorting on the measurement points in the block unit to obtain a first priority order; based on the first priority order, performing a first clearing process on the measurement points in each block unit to remove other measurement points that are within a critical overlap distance and have a lower priority around the measurement point; based on the process window size corresponding to the measurement point, performing a priority sorting on the measurement points at the boundaries of adjacent block units to obtain a second priority order; based on the second priority order, performing a first clearing process on the measurement points in each block unit to remove other measurement points that are within a critical overlap distance and have a lower priority; At the boundary of the block unit, the measurement point is subjected to a second clearing process to remove other measurement points with lower priority that are within the critical overlapping distance around the measurement point at the boundary; by first sorting the measurement points based on the process window size corresponding to the measurement points, other measurement points with lower priority are removed during the first clearing process and the second clearing process, which is beneficial to avoid removing measurement points that have a greater impact on the process window. Accordingly, in the subsequent step of measuring the graphics formed on the wafer based on the processed measurement points, the measurement points with smaller process windows can be measured preferentially, which is beneficial to improve the effectiveness of the measurement.

[0015] In the wafer pattern measurement system provided by the embodiment of the present invention, the distance calculation module obtains the critical overlapping distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view; the clearing module performs clearing processing on the measurement point to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, when the measurement module measures the pattern formed on the wafer based on the processed measurement points, not only the number of measurement points can be reduced, but also the problem of overlapping between the measurement fields of adjacent measurement points can be prevented, thereby ensuring that all the patterns within the measurement field of view are bombarded by the scanning electron beam only once, preventing the pattern in the overlapping area from being repeatedly bombarded by the scanning electron beam and being deformed and damaged, resulting in inaccurate measurement results, and correspondingly improving the accuracy of the measurement results, and there is no need to select and process the measurement results of repeated measurement points in the future, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of a wafer pattern measurement method;

[0017] Figure 2 is to use Figure 1 The wafer pattern measurement method shown is an example of measuring a pattern formed on a wafer;

[0018] Figure 3 It is a flow chart of an embodiment of a method for measuring wafer patterns of the present invention;

[0019] Figure 4 is a schematic diagram of an embodiment of a measurement point and a measurement field of view;

[0020] Figure 5 yes Figure 3 A schematic diagram of a flow chart of an embodiment of step S3;

[0021] Figure 6 is a schematic diagram of an embodiment of performing block processing on a modified layout;

[0022] Figure 7 yes Figure 5 A schematic diagram of a flow chart of an embodiment of step S32;

[0023] Figure 8 A schematic diagram showing a first clearing process for the measurement points in each block unit f is shown;

[0024] Fig. 9 A schematic diagram showing an embodiment of a preset area;

[0025] Fig.10It is a functional block diagram of an embodiment of a wafer pattern measurement system of the present invention;

[0026] Fig.11 It is a hardware structure diagram of an embodiment of the device provided by the present invention. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, currently when measuring patterns on a wafer, there is a problem of large measurement errors.

[0028] Combined with a wafer pattern measurement method, this paper analyzes the reasons why there is a large measurement error when measuring patterns on a wafer. Figure 1 The present invention is a flow chart of a wafer pattern measurement method.

[0029] Figure 2 is to use Figure 1 The wafer pattern measurement method shown is an example of measuring the pattern formed on the wafer.

[0030] Combined with reference Figure 1 and Figure 2 , step s1: obtaining a verification result of an optical proximity effect correction verification process of a corrected layout, wherein the verification result includes the coordinates of a weak point.

[0031] Continue to refer Figure 1 and Figure 2 , step s2: taking the coordinates of the weak point as the measuring point B, measuring the pattern formed on the wafer to obtain a measurement result.

[0032] refer to Figure 1 , step s3: based on the measurement results, identifying the repeatedly measured figures as repeated points.

[0033] refer to Figure 1 , step s4: select and process the multiple measurement results of the repeated points to obtain processed results.

[0034] Among them, in the step of measuring the pattern formed on the wafer with the coordinates of the weak point as the measurement point B, key dimensions of tens of thousands of weak points and the patterns within a certain range around them are measured and contours are extracted to achieve accurate defect capture and environmental structure analysis.

[0035] However, when measuring the graphics on the wafer, the high-power electron beam used will not only cause the photoresist to deform, but also damage the surface of the silicon wafer, which will eventually cause the key dimensions of the graphics to change after scanning once, regardless of whether it is After Development Inspection (ADI) or After Etching Inspection (AEI), and the graphics cannot be used again; moreover, based on the verification results, the coordinates of the obtained weak points are not limited by the distance between adjacent weak points, and it is easy for the measurement fields A of two adjacent measurement points B to overlap, which in turn causes the graphics located in the overlapping area to be repeatedly bombarded by the electron beam, resulting in errors in the measurement results obtained in the final measurement and unreliable data.

[0036] therefore, Figure 1 In the wafer pattern measurement method shown, the pattern to be repeatedly measured is identified as a repeated point, and the measurement points of the repeated points are selected to obtain a processed result to improve the problem of measurement error.

[0037] However, in the semiconductor field, there are a large number of patterns on a wafer, and the amount of data of the measurement results is also large. The amount of calculation required to select and process multiple measurement results of the repeated points is large, resulting in a cumbersome processing process and consuming too much time.

[0038] In order to solve the technical problem, an embodiment of the present invention provides a method for measuring wafer graphics. Figure 3 It is a flow chart of an embodiment of a method for measuring wafer patterns of the present invention.

[0039] like Figure 3 As shown, in this embodiment, the wafer pattern measurement method includes the following basic steps:

[0040] Step S1: obtaining a verification result of an optical proximity effect correction verification process of a corrected layout, wherein the verification result includes coordinates of a weak point;

[0041] Step S2: based on the coordinates of the weak point and the measurement field of view, obtaining a critical overlap distance between the measurement point and an adjacent measurement field of view;

[0042] Step S3: performing a clearing process on the measurement point to remove other measurement points around the measurement point that are within the critical overlapping distance and have a lower priority, and the remaining measurement points are used as processed measurement points;

[0043] Step S4: Based on the post-processing measurement points, the pattern formed on the wafer is measured to obtain a measurement result.

[0044] In the wafer graphics measurement method provided by the embodiment of the present invention, based on the coordinates of the weak point and the measurement field of view, a critical overlapping distance between the measurement point and the adjacent measurement field of view is obtained; the measurement point is cleared to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, in the step of measuring the graphics formed on the wafer based on the processed measurement points, not only the number of measurement points can be reduced, but also the problem of overlapping between the measurement fields of adjacent measurement points can be prevented, thereby ensuring that all graphics within the measurement field of view are bombarded by the scanning electron beam only once, preventing the graphics in the overlapping area from being repeatedly bombarded by the scanning electron beam and being deformed and damaged, resulting in inaccurate measurement results, and correspondingly improving the accuracy of the measurement results. There is no need to select and process the measurement results of repeated measurement points in the future, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0045] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] refer to Figure 3 , step S1: obtaining a verification result of an optical proximity effect correction verification process of a corrected layout, wherein the verification result includes coordinates of weak points.

[0047] The verification result is obtained so as to obtain the coordinates of the weak point, and then the measurement point can be obtained based on the coordinates of the weak point, and the measurement point is cleared, and then the pattern formed on the wafer is measured based on the processed measurement point.

[0048] The corrected layout is a design layout after optical proximity effect correction processing.

[0049] In a specific implementation, after the optical proximity effect correction process is performed, an optical proximity effect correction verification process is usually performed on the corrected layout to verify whether the corrected layout still has weaknesses and defects.

[0050] In this embodiment, the verification result includes the coordinates of the weak point, and the coordinates refer to the coordinate information in the corrected layout.

[0051] refer to Figure 3 , and combined with Figure 4 , Figure 4 is a schematic diagram of an embodiment of a measuring point and a measuring field of view, step S2: based on the coordinates of the weak point and the measuring field of view D, obtaining a critical overlapping distance h between a measuring point C and an adjacent measuring field of view D.

[0052] The measurement point C is used to obtain a post-processing measurement point through a subsequent cleaning process, so that the post-processing measurement point can be used as a reference point for measuring the wafer pattern.

[0053] A critical overlapping distance h between adjacent measurement fields D is obtained, so that adjacent measurement points C with overlapping measurement fields D can be obtained based on the critical overlapping distance h, and the measurement points C with overlapping measurement fields D can be cleared.

[0054] In this embodiment, the critical overlap distance h means that when the distance between adjacent measurement points C is less than the critical overlap distance h, adjacent measurement fields of view D overlap.

[0055] In this embodiment, the measurement field of view D is a square area; based on the coordinates of the weak point and the measurement field of view D, the step S2 of obtaining the critical overlap distance h between the measurement point C and the adjacent measurement field of view D includes: taking the coordinates of the weak point as the measurement point C; taking the side length a of the measurement field of view D as the distance h of the measurement point C; times, as the critical overlapping distance h between adjacent measurement fields D.

[0056] In this embodiment, the measuring field of view D is a square area, and the sides of the measuring field of view D extend along a first direction (not marked) and a second direction (not marked), respectively, and the first direction and the second direction are perpendicular to each other.

[0057] In this embodiment, when the top corners of adjacent measuring fields of view D touch each other along the diagonal direction of the measuring fields of view D, it is the critical position where the adjacent measuring fields of view D overlap. times, as the critical overlapping distance h between adjacent measurement fields of view D, and the critical overlapping distance h includes: a variety of situations in which adjacent measurement fields of view D are arranged along the first direction, the second direction, and the direction at any angle to the first direction, which is conducive to including the distances between all adjacent measurement points C that may cause overlap of the measurement fields of view D, and correspondingly improves the accuracy of subsequent clearing processing of the measurement points C, so that after the measurement points C are cleared, there is a sufficient distance between adjacent processed measurement points, which is conducive to ensuring that the problem of overlap between adjacent measurement fields of view D is avoided.

[0058] It should be noted that, in this embodiment, the wafer graphics measurement method also includes: after obtaining the verification result of the optical proximity effect correction verification processing of the corrected layout, and before the measurement point C is cleared, step S5: based on the coordinates of the weak point, the corrected layout is cropped to remove the part of the layout that does not contain the weak point from the corrected layout to obtain a local layout.

[0059] The corrected layout is cropped to remove the portion of the corrected layout that does not contain the weakness, which is beneficial to reducing the layout area that needs to be cleared later, thereby reducing the amount of data processing and improving computing efficiency.

[0060] It should also be noted that, in this embodiment, the wafer graphics measurement method also includes: after obtaining the critical overlap distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view, and before clearing the measurement point, step S6: screening the measurement point C to select all measurement points with measurement points within the surrounding critical overlap distance h as measurement points to be processed.

[0061] The measurement points are screened to select all measurement points within the surrounding critical overlapping distance h. That is to say, all measurement points that need to be processed are selected first so that only the measurement points to be processed are cleared later, thereby simplifying the number of measurement points that need to be processed, improving the efficiency of clearing processing, and shortening the processing time.

[0062] Specifically, in this embodiment, after the corrected layout is cropped based on the coordinates of the weak points, the measurement points are screened, and accordingly only the measurement points in the local layout are screened, which is conducive to further simplifying the steps of screening the measurement points and improving processing efficiency.

[0063] refer to Figure 3 , step S3: performing a clearing process on the measurement point to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points.

[0064] The measurement points are cleared to remove other measurement points with lower priorities around the measurement points that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, in the step of measuring the graphics formed on the wafer based on the processed measurement points, not only the number of measurement points can be reduced, but also the problem of overlapping between the measurement fields of adjacent measurement points can be prevented, thereby ensuring that all graphics within the measurement field of view are bombarded by the scanning electron beam only once, and preventing the graphics in the overlapping area from being repeatedly bombarded by the scanning electron beam and deformed and damaged, resulting in inaccurate measurement results. The accuracy of the measurement results is correspondingly improved, and there is no need to select and process the measurement results of repeated measurement points subsequently, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0065] In this embodiment, after obtaining the verification result of the optical proximity effect correction verification processing of the corrected layout and before the measurement point is cleared, step S5: based on the coordinates of the weak point, the corrected layout is cropped to remove the part of the layout that does not contain the weak point from the corrected layout to obtain a local layout; accordingly, in this embodiment, the step of clearing the measurement point includes: clearing the measurement point in the local layout.

[0066] It should also be noted that, in this embodiment, after obtaining the critical overlapping distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view, and before clearing the measurement point, step S6: screening the measurement point to select all measurement points with measurement points within the surrounding critical overlapping distance as measurement points to be processed; correspondingly, the step of clearing the measurement point includes: clearing the measurement point to be processed.

[0067] Figure 5 yes Figure 3 FIG. 1 is a flow chart of an embodiment of step S3 in FIG. 1 .

[0068] The following reference Figure 5 , the specific implementation of step S3 of clearing the measurement points in this embodiment is described in detail.

[0069] like Figure 5 As shown, combined Figure 6 , Figure 6 This is a schematic diagram of an embodiment of performing block processing on a modified layout, step S31: performing block processing on the modified layout, for dividing the modified layout into a plurality of block units f arranged in an array.

[0070] The corrected layout is divided into a plurality of block units f arranged in an array, so that the measurement points in the block unit f and at the boundaries of adjacent block units f can be cleared later.

[0071] In the step of performing block processing on the revised layout, the side length b of the block unit f should not be too small or too large. If the side length b of the block unit f is too small, the area of ​​the block unit f is too small, which may easily lead to an excessive number of block units f after the block processing, and may easily lead to the inefficiency of the subsequent clearing processing and the effect of reducing the processing time being not obvious; if the side length of the block unit f is too large, the area of ​​the block unit f is too large, which may easily lead to an insignificant effect of reducing the number of measurement points in each block unit f. For this reason, in this embodiment, the measurement field of view D is a square area; in the step of performing block processing on the revised layout, the side length b of the block unit f is 5 to 10 times the side length of the measurement field of view.

[0072] like Figure 5 As shown, step S32: clearing the measurement points in the block unit f and at the boundaries of adjacent block units f, so as to remove other measurement points around the measurement points within the critical overlap distance h.

[0073] In this embodiment, by dividing the corrected layout into a plurality of block units f arranged in an array, the number of measurement points to be cleared in each block unit f and at adjacent block units f can be reduced in the step of clearing the measurement points. It is also beneficial to clear the measurement points in a plurality of block units f at the same time in parallel, or to clear the measurement points at the boundaries of a plurality of adjacent block units f at the same time in parallel, thereby improving the efficiency of the clearing process and reducing the processing time.

[0074] Figure 7 yes Figure 5 FIG. 1 is a flow chart of an embodiment of step S32 in FIG.

[0075] Specifically, in this embodiment, the step S32 of clearing the measurement points in the block unit and at the boundary of adjacent block units includes:

[0076] like Figure 7 As shown, step S321: based on the process window size corresponding to the measurement point, the measurement points in the block unit f are prioritized to obtain a first priority order.

[0077] The measurement points in the block unit f are prioritized based on the process window size corresponding to the measurement points, so that the measurement points are subsequently cleared in each block unit f based on the first priority order.

[0078] Specifically, in this embodiment, in the step of prioritizing the measurement points in the block unit f based on the process window size corresponding to the measurement points, the smaller the process window, the higher the corresponding priority. The smaller the process window, the higher the probability of defects at the measurement point. By making the points with smaller process windows have higher corresponding priorities, in the subsequent step of performing the first clearing process on the measurement points in each block unit f, the measurement points with smaller process windows can be preferentially retained, thereby facilitating the subsequent measurement of the measurement points with smaller process windows.

[0079] In this embodiment, the process window includes a process variation band (PVband). In other embodiments, the actual process window can also be calculated by using a Focus-Energy Matrix (FEM) and measuring the changes in the critical dimensions of the wafer pattern under different exposure conditions.

[0080] like Figure 7 As shown, combined Figure 8 , Figure 8 A schematic diagram of performing a first clearing process on the measurement points in each block unit f is shown, step S322: based on the first priority order, performing a first clearing process on the measurement points in each block unit f, for removing other measurement points around the measurement points that are within a critical overlapping distance and have a lower priority.

[0081] In each block unit f, based on the first priority order, first remove other measurement points with lower priorities that are within the critical overlap distance around the measurement point with higher priority; then remove other measurement points with lower priorities that are within the critical overlap distance around the measurement point with higher priority; Figure 8 As shown, after the first clearing process is completed on the measurement points in the block unit f, measurement points 1 to 9 are left in the block unit f.

[0082] like Figure 7 As shown, step S323: based on the process window size corresponding to the measurement point, the measurement points at the boundaries of adjacent block units f are prioritized to obtain a second priority order.

[0083] The measurement points at the boundaries of the adjacent block units f are prioritized so that a second clearing process is subsequently performed on the measurement points at the boundaries of the adjacent block units f based on a second priority order.

[0084] Specifically, in this embodiment, in the step of prioritizing the measurement points at the boundary of adjacent block units f based on the process window size corresponding to the measurement points, the smaller the process window, the higher the corresponding priority. The smaller the process window, the higher the probability of defects at the measurement point. By making the points with smaller process windows have higher corresponding priorities, in the subsequent step of performing the second clearing process on the measurement points at the boundary of adjacent block units f, the measurement points with smaller process windows can be preferentially retained, thereby facilitating the subsequent measurement of the measurement points with smaller process windows.

[0085] In this embodiment, the process window includes a process variation band (PVband). In other embodiments, the actual process window can also be calculated by using a Focus-Energy Matrix (FEM) and measuring the changes in the critical dimensions of the wafer pattern under different exposure conditions.

[0086] like Figure 7 As shown, step S324: based on the second priority order, at the boundary of the adjacent block unit f, the measurement points are subjected to a second clearing process to remove other measurement points with lower priority that are within the critical overlapping distance around the measurement points at the boundary.

[0087] Combined with reference Fig. 9 , a schematic diagram of an embodiment of a preset area is shown.

[0088] Specifically, in this embodiment, based on the second priority order, the step of performing a second clearing process on the measurement point at the boundary of the adjacent block unit f includes: setting a preset area with a preset width at the boundary of the adjacent block unit f; within the preset area, based on the second priority order, removing other measurement points with lower priority around the measurement point that are within the critical overlapping distance.

[0089] Among them, in this embodiment, the step of setting a preset area with a preset width at the boundary of adjacent block units f includes: setting a first preset area y1 with a preset width w at the boundary of adjacent block units f along the first direction; setting a second preset area y2 with a preset width w at the boundary of adjacent block units f along the second direction.

[0090] In this embodiment, the measurement field of view is a square area; the preset width w is the length of the side of the measurement field of view. times.

[0091] In this embodiment, for the specific steps of removing other measurement points with lower priority around the measurement point within the preset area and within the critical overlapping distance based on the second priority order, please refer to the aforementioned detailed description of the first clearing processing step of the measurement point in each block unit f based on the first priority order, which will not be repeated here.

[0092] refer to Figure 3 , step S4: based on the processed measurement points, measuring the pattern formed on the wafer to obtain a measurement result.

[0093] In this embodiment, based on the coordinates of the weak point and the measurement field of view, a critical overlapping distance between the measurement point and the adjacent measurement field of view is obtained; the measurement point is cleared to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, in the step of measuring the graphics formed on the wafer based on the processed measurement points, not only the number of measurement points can be reduced, but also the problem of overlapping between the measurement fields of adjacent measurement points can be prevented, thereby ensuring that all graphics within the measurement field of view are bombarded by the scanning electron beam only once, and preventing the graphics in the overlapping area from being repeatedly bombarded by the scanning electron beam and deformed and damaged, resulting in inaccurate measurement results. The accuracy of the measurement results is correspondingly improved, and there is no need to select and process the measurement results of repeated measurement points in the future, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0094] Specifically, in this embodiment, measuring the pattern on the wafer includes: measuring the photoresist pattern on the wafer after the exposure and development process; or measuring the post-etching pattern on the wafer after the photoresist pattern is transferred to the film layer on the wafer.

[0095] In the semiconductor field, in the process of measuring a photoresist pattern, a scanning electron beam is used to scan the photoresist pattern, and the scanning electron beam bombards the photoresist pattern, which can easily deform the photoresist pattern, thereby changing the key dimensions and contours of the photoresist pattern. The measurement method in this embodiment can avoid the problem of overlapping measurement fields, and accordingly prevent the photoresist pattern in the overlapping area from being repeatedly bombarded, resulting in inaccurate measurement results, and there is no need to select and process the measurement results of repeated measurements, which is conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0096] Moreover, in the process of measuring the etched graphics, the scanning electron beam will also cause damage to the etched graphics, which can easily cause changes in the key dimensions and contours of the etched graphics. The measurement method of this embodiment can also improve the measurement accuracy of the etched graphics, reduce the difficulty of data processing, and improve work efficiency.

[0097] Therefore, through the measurement method of this embodiment, after the measurement results are obtained, when the measurement results are analyzed, the inspection effect of the exposure quality and the etching quality can be improved according to the analysis results of the measurement results.

[0098] Correspondingly, the present invention also provides a wafer pattern measurement system. Fig.10 It is a functional block diagram of an embodiment of a wafer pattern measurement system of the present invention.

[0099] refer to Fig.10 In this embodiment, the wafer pattern measurement system includes: an acquisition module 101, which is used to obtain the verification result of the optical proximity effect correction verification processing of the corrected layout, and the verification result includes the coordinates of the weak point; a distance calculation module 102, which is used to obtain the critical overlap distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view; a clearing module 103, which is used to clear the measurement point, and is used to remove other measurement points around the measurement point that are within the critical overlap distance, and the remaining measurement points are used as processed measurement points; a measuring module 104, which is used to measure the pattern formed on the wafer based on the processed measurement point to obtain a measurement result.

[0100] In the wafer pattern measurement system, the distance calculation module 102 obtains the critical overlapping distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view; the clearing module 103 performs a clearing process on the measurement point to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, when the measurement module 104 measures the pattern formed on the wafer based on the processed measurement points, not only the number of measurement points can be reduced, but also the problem of overlapping between the measurement fields of adjacent measurement points can be prevented, thereby ensuring that all the patterns within the measurement field of view are bombarded by the scanning electron beam only once, and preventing the patterns in the overlapping area from being repeatedly bombarded by the scanning electron beam and deformed and damaged, resulting in inaccurate measurement results, thereby correspondingly improving the accuracy of the measurement results, and there is no need to select and process the measurement results of repeated measurement points in the future, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0101] The acquisition module 101 obtains the verification result to obtain the coordinates of the weak point, and then the clearing module 103 can obtain the measurement point based on the coordinates of the weak point and clear the measurement point, and the measurement module 104 measures the pattern formed on the wafer based on the processed measurement point.

[0102] The corrected layout is a design layout after optical proximity effect correction processing.

[0103] In a specific implementation, after the optical proximity effect correction process is performed, an optical proximity effect correction verification process is usually performed on the corrected layout to verify whether the corrected layout still has weaknesses and defects.

[0104] In this embodiment, the verification result includes the coordinates of the weak point, and the coordinates refer to the coordinate information in the corrected layout.

[0105] refer to Figure 3 , and combined with Figure 4 , Figure 4 It is a schematic diagram of an embodiment of a measuring point and a measuring field of view.

[0106] The distance calculation module 102 obtains a critical overlapping distance h between the measurement point C and an adjacent measurement field D based on the coordinates of the weak point and the measurement field D.

[0107] The measurement point C is used to obtain a processed measurement point through a cleaning process by the cleaning module 103, so that the processed measurement point can be used as a reference point for measuring the wafer pattern.

[0108] The critical overlap distance h between adjacent measurement fields D is obtained so that the clearing module 103 can obtain adjacent measurement points with overlapped measurement fields D based on the critical overlap distance h, and then clear the measurement points C with overlapped measurement fields D.

[0109] In this embodiment, the critical overlap distance h means that when the distance between adjacent measurement points C is less than the critical overlap distance h, adjacent measurement fields of view D overlap.

[0110] In this embodiment, the measurement field of view D is a square area; based on the coordinates of the weak point and the measurement field of view D, the distance calculation module 102 is used to use the coordinates of the weak point as the measurement point C, and also to use the side length a of the measurement field of view D as the distance calculation module 102. times, as the critical overlapping distance h between adjacent measurement fields D.

[0111] In this embodiment, the measuring field of view D is a square area, and the sides of the measuring field of view D extend along a first direction (not marked) and a second direction (not marked), respectively, and the first direction and the second direction are perpendicular to each other.

[0112] In this embodiment, when the top corners of adjacent measuring fields of view D touch each other along the diagonal direction of the measuring fields of view D, it is the critical position where the adjacent measuring fields of view D overlap. times, as the critical overlapping distance h between adjacent measurement fields of view D, and the critical overlapping distance h includes: a variety of situations in which adjacent measurement fields of view D are arranged along the first direction, the second direction, and the direction at any angle to the first direction, which is beneficial to include the distances between all adjacent measurement points C that may cause overlap of the measurement fields of view D, and correspondingly improves the accuracy of the clearing module 103 in clearing the measurement point C, so that after the measurement point C is cleared, there is a sufficient distance between adjacent processed measurement points, which is beneficial to ensure that the problem of overlap between adjacent measurement fields of view D is avoided.

[0113] It should be noted that, in this embodiment, the wafer graphic measurement system also includes: a cropping module 105, which is used to crop the corrected layout based on the coordinates of the weak point, so as to remove the part of the layout that does not contain the weak point from the corrected layout, obtain the local layout and output it to the clearing module 103.

[0114] The cropping module 105 crops the corrected layout, thereby removing the portion of the corrected layout that does not contain weaknesses, which is helpful in reducing the layout area that needs to be cleared by the clearing module 103, thereby reducing the amount of data processing and improving computing efficiency.

[0115] It should also be noted that, in this embodiment, the wafer graphics measurement system also includes: a screening module 106, which is used to screen the measurement points to select all measurement points with measurement points within the surrounding critical overlapping distance as measurement points to be processed and output the measurement points to be processed to the clearing module 103.

[0116] The screening module 106 screens the measurement points to select all measurement points with measurement points within the surrounding critical overlapping distance h. That is to say, all measurement points that need to be processed are first selected so that the clearing module 103 only clears the measurement points to be processed, thereby simplifying the number of measurement points that need to be processed, improving the efficiency of clearing processing, and shortening the processing time.

[0117] Specifically, in this embodiment, the cropping module 105 outputs the local layout to the screening module 106. Accordingly, the screening module 106 only screens the measurement points in the local layout, which is conducive to further simplifying the steps of screening the measurement points and improving processing efficiency.

[0118] The clearing module 103 performs a clearing process on the measurement points to remove other measurement points around the measurement points that are within the critical overlapping distance and have a lower priority, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, when the measurement module 104 measures the graphics formed on the wafer based on the processed measurement points, it can not only reduce the number of measurement points, but also help prevent the problem of overlapping between the measurement fields of adjacent measurement points, thereby ensuring that all graphics within the measurement field of view are bombarded by the scanning electron beam only once, and preventing the graphics in the overlapping area from being repeatedly bombarded by the scanning electron beam and deformed and damaged, resulting in inaccurate measurement results. The accuracy of the measurement results is correspondingly improved, and there is no need to select and process the measurement results of repeated measurement points subsequently, which is also conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0119] Specifically, in this embodiment, the clearing module 104 clears the measurement points in the local layout. More specifically, in this embodiment, the clearing module 104 clears the measurement points to be processed.

[0120] In this embodiment, the clearing module 103 includes: a block processing unit (not shown in the figure), which is used to perform block processing on the corrected layout to divide the corrected layout into a plurality of block units f arranged in an array; a clearing processing unit (not shown in the figure), which is used to perform clearing processing on the measurement points within the block unit f and at the boundaries of adjacent block units f to remove other measurement points around the measurement points that are within the critical overlap distance h.

[0121] In this embodiment, by dividing the corrected layout into a plurality of block units arranged in an array, the number of measurement points to be cleared in each block unit and at adjacent block units can be reduced in the step of clearing the measurement points. It is also beneficial to clear the measurement points in a plurality of block units at the same time in parallel, or to clear the measurement points at the boundaries of a plurality of adjacent block units at the same time in parallel, thereby improving the efficiency of the clearing process and reducing the processing time.

[0122] The block processing unit is used to divide the corrected layout into a plurality of block units arranged in an array, so as to perform a clearing process on the measurement points within the block unit and at the boundaries of adjacent block units.

[0123] The side length b of the block unit f should not be too small or too large. If the side length b of the block unit f is too small, the area of ​​the block unit f is too small, which may lead to an excessive number of block units f after the block processing, and may reduce the efficiency of the clearing process and reduce the processing time. If the side length of the block unit f is too large, the area of ​​the block unit f is too large, which may lead to an insignificant effect of reducing the number of measurement points in each block unit f. For this reason, in this embodiment, the measurement field of view D is a square area; the side length b of the block unit f is 5 to 10 times the side length of the measurement field of view.

[0124] In this embodiment, the clearing processing unit includes: a first priority sorting block (not shown in the figure), which is used to prioritize the measurement points in the block unit based on the process window size corresponding to the measurement point to obtain a first priority order; a first clearing block (not shown in the figure), which is used to perform a first clearing process on the measurement point in each block unit based on the first priority order, so as to remove other measurement points with lower priority that are within a critical overlapping distance around the measurement point; a second priority sorting block (not shown in the figure), which is used to prioritize the measurement points at the boundaries of adjacent block units based on the process window size corresponding to the measurement point to obtain a second priority order; a second clearing block (not shown in the figure), which is used to perform a second clearing process on the measurement point at the boundary of adjacent block units based on the second priority order, so as to remove other measurement points with lower priority that are within a critical overlapping distance around the measurement point at the boundary.

[0125] The first priority sorting block prioritizes the measurement points in the block unit f based on the process window size corresponding to the measurement points, so that the first clearing block performs a first clearing process on the measurement points in each block unit f based on the first priority order.

[0126] Specifically, in this embodiment, the smaller the process window of the measurement point, the higher the corresponding priority. The smaller the process window, the higher the probability of defects at the measurement point. By making the points with smaller process windows have higher corresponding priorities, when the first clearing block performs the first clearing process on the measurement points in each block unit f, the measurement points with smaller process windows can be retained preferentially, thereby facilitating the measurement module 104 to measure the measurement points with smaller process windows.

[0127] In this embodiment, the process window includes a process variation band (PVband). In other embodiments, the actual process window can also be calculated by using a Focus-Energy Matrix (FEM) and measuring the critical dimension variation of wafer patterns under different exposure conditions.

[0128] The first clearing block is used to perform a first clearing process on the measurement points in each block unit f based on the first priority order, so as to remove other measurement points with lower priorities that are within a critical overlapping distance around the measurement points.

[0129] In this embodiment, in each block unit f, based on the first priority order, first remove other measurement points with lower priorities that are within the critical overlap distance and around the measurement point with higher priority; then remove other measurement points with lower priorities that are within the critical overlap distance and around the measurement point with higher priority; Figure 8As shown, after the first clearing process is completed on the measurement points in the block unit f, measurement points 1 to 9 are left in the block unit f.

[0130] The second priority sorting block prioritizes the measurement points at the boundaries of adjacent block units f, so that the second clearing block performs a second clearing process on the measurement points at the boundaries of adjacent block units f based on the second priority order.

[0131] Specifically, in this embodiment, the smaller the process window of the measurement point, the higher the corresponding priority. The smaller the process window, the higher the probability of defects at the measurement point. By making the points with smaller process windows have higher corresponding priorities, when the second clearing block performs the second clearing of the measurement points at the boundary of the adjacent block unit f, the measurement points with smaller process windows can be preferentially retained, thereby facilitating the measurement module 104 to measure the measurement points with smaller process windows.

[0132] In this embodiment, the process window includes a process variation band (PVband). In other embodiments, the actual process window can also be calculated by using a Focus-Energy Matrix (FEM) and measuring the critical dimension variation of wafer patterns under different exposure conditions.

[0133] The second clearing block performs a second clearing process on the measurement points at the boundary of adjacent block units f based on the second priority order, so as to remove other measurement points with lower priority around the measurement points at the boundary that are within the critical overlapping distance.

[0134] Combined with reference Fig. 9 , a schematic diagram of an embodiment of a preset area is shown.

[0135] Specifically, in this embodiment, the second clearing block is used to set a preset area with a preset width at the boundary of adjacent block units f, and is also used to remove other measurement points with lower priority around the measurement point within the preset area based on the second priority order.

[0136] In this embodiment, a preset area with a preset width is set at the boundary of adjacent block units f, including: a first preset area y1 with a preset width w is set at the boundary of adjacent block units f along the first direction; and a second preset area y2 with a preset width w is set at the boundary of adjacent block units f along the second direction.

[0137] In this embodiment, the measurement field of view is a square area; the preset width w is the length of the side of the measurement field of view. times.

[0138] In this embodiment, for a specific description of removing other measurement points with lower priorities that are within the critical overlapping distance around the measurement point within the preset area based on the second priority order, please refer to the aforementioned detailed description of performing the first clearing processing step on the measurement points in each block unit f based on the first priority order, which will not be repeated here.

[0139] The measuring module 104 is used to measure the pattern formed on the wafer based on the post-processing measurement points to obtain a measurement result.

[0140] In this embodiment, the clearing module 103 performs a clearing process on the measurement points to remove other measurement points around the measurement points that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points to ensure that there is a sufficient distance between adjacent measurement points. Accordingly, when the measurement module 104 measures the graphics formed on the wafer based on the processed measurement points, not only can the number of measurement points be reduced, but it is also beneficial to prevent the problem of overlapping between the measurement fields of adjacent measurement points, thereby ensuring that all graphics within the measurement field of view are bombarded by the scanning electron beam only once, and preventing the graphics in the overlapping area from being repeatedly bombarded by the scanning electron beam and deformed and damaged, resulting in inaccurate measurement results. The accuracy of the measurement results is correspondingly improved, and there is no need to select and process the measurement results of repeated measurement points subsequently, which is also beneficial to greatly reduce the difficulty of data processing and improve work efficiency.

[0141] Specifically, in this embodiment, measuring the pattern on the wafer includes: measuring the photoresist pattern on the wafer after the exposure and development process; or measuring the post-etching pattern on the wafer after the photoresist pattern is transferred to the film layer on the wafer.

[0142] In the semiconductor field, in the process of measuring a photoresist pattern, a scanning electron beam is used to scan the photoresist pattern, and the scanning electron beam bombards the photoresist pattern, which can easily deform the photoresist pattern, thereby changing the key dimensions and contours of the photoresist pattern. The measurement method in this embodiment can avoid the problem of overlapping measurement fields, and accordingly prevent the photoresist pattern in the overlapping area from being repeatedly bombarded, resulting in inaccurate measurement results, and there is no need to select and process the measurement results of repeated measurements, which is conducive to greatly reducing the difficulty of data processing and improving work efficiency.

[0143] Moreover, in the process of measuring the etched graphics, the scanning electron beam will also cause damage to the etched graphics, which can easily cause changes in the key dimensions and contours of the etched graphics. The measurement method of this embodiment can also improve the measurement accuracy of the etched graphics, reduce the difficulty of data processing, and improve work efficiency.

[0144] Therefore, through the measurement method of this embodiment, after the measurement results are obtained, when the measurement results are analyzed, the inspection effect of the exposure quality and the etching quality can be improved according to the analysis results of the measurement results.

[0145] An embodiment of the present invention further provides a device, which can implement the wafer pattern measuring method provided by the embodiment of the present invention by loading the above-mentioned wafer pattern measuring method in the form of a program.

[0146] An optional hardware structure of the terminal device provided by the embodiment of the present invention can be as follows Fig.11 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0147] In the embodiment of the present invention, the number of the processor 01, the communication interface 02, the memory 03, and the communication bus 04 is at least one, and the processor 01, the communication interface 02, and the memory 03 communicate with each other through the communication bus 04;

[0148] Optionally, the communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module;

[0149] The processor 01 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0150] The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0151] The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the wafer pattern measurement method provided in the embodiment of the present invention.

[0152] It should be noted that the above-mentioned terminal device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; given that these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.

[0153] Correspondingly, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the wafer pattern measurement method provided by the embodiment of the present invention.

[0154] The above-mentioned embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, the embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any one embodiment may be included in another embodiment, and may be replaced by the corresponding construction of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the attached claims may be combined into embodiments of the present invention, or may be included as new claims in the amendment after submitting this application.

[0155] The embodiments of the present invention may be implemented by various means such as hardware, firmware, software or a combination thereof. In a hardware configuration, the method based on the exemplary embodiment of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0156] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, etc. The software code may be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and may send data to and receive data from the processor via various known means.

[0157] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0158] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for measuring wafer patterns, characterized in that: include: Obtaining a verification result of an optical proximity effect correction verification process of the corrected layout, wherein the verification result includes coordinates of a weak point; Based on the coordinates of the weak point and the measurement field of view, obtaining a critical overlap distance between the measurement point and an adjacent measurement field of view; Performing a clearing process on the measurement point to remove other measurement points around the measurement point that are within the critical overlapping distance, and the remaining measurement points are used as processed measurement points; Based on the post-processing measurement points, the pattern formed on the wafer is measured to obtain a measurement result.

2. The wafer pattern measuring method according to claim 1, characterized in that: The wafer pattern measurement method further includes: after obtaining the critical overlap distance between the measurement point and the adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view, and before clearing the measurement point, screening the measurement point to select all measurement points with measurement points within the surrounding critical overlap distance as the measurement points to be processed; The step of clearing the measurement points includes: clearing the measurement points to be processed.

3. The wafer pattern measuring method according to claim 1, characterized in that: The step of performing a clearing process on the measurement points includes: performing a block process on the corrected layout to divide the corrected layout into a plurality of block units arranged in an array; The measurement points in the block unit and at the boundaries of adjacent block units are cleared to remove other measurement points around the measurement points that are within the critical overlap distance.

4. The wafer pattern measuring method according to claim 3, characterized in that: The step of clearing the measurement points in the block unit and at the boundaries of adjacent block units includes: prioritizing the measurement points in the block unit based on the process window size corresponding to the measurement points to obtain a first priority order; Based on the first priority order, in each block unit, the measurement point is subjected to a first clearing process to remove other measurement points with lower priorities that are within a critical overlapping distance around the measurement point; Based on the process window size corresponding to the measurement point, the measurement points at the boundaries of adjacent block units are prioritized to obtain a second priority order; Based on the second priority order, a second clearing process is performed on the measurement points at the boundary between adjacent block units, so as to remove other measurement points with lower priority that are within the critical overlapping distance around the measurement points at the boundary.

5. The wafer pattern measuring method according to claim 4, characterized in that: Based on the second priority order, the step of performing a second clearing process on the measurement point at the boundary of adjacent block units includes: setting a preset area with a preset width at the boundary of adjacent block units; within the preset area, based on the second priority order, removing other measurement points with lower priority around the measurement point that are within the critical overlapping distance.

6. The wafer pattern measuring method according to claim 5, characterized in that: The measuring field of view is a square area; the preset width is twice the side length of the measuring field of view.

7. The wafer pattern measuring method according to claim 3, characterized in that: The measurement field of view is a square area; in the step of dividing the corrected layout into blocks, the side length of the block unit is 5 to 10 times the side length of the measurement field of view.

8. The wafer pattern measuring method according to claim 4, characterized in that: In the step of prioritizing the measurement points in the block unit based on the process window size corresponding to the measurement point, the measurement point with a smaller process window has a higher corresponding priority; In the step of prioritizing the measurement points at the boundaries of adjacent block units based on the process window sizes corresponding to the measurement points, the smaller the process window, the higher the corresponding priority.

9. The wafer pattern measuring method according to claim 4, characterized in that: The process window includes a process variation bandwidth.

10. The wafer pattern measuring method according to claim 1, wherein: The wafer pattern measurement method further includes: after obtaining the verification result of the optical proximity effect correction verification process of the corrected layout and before clearing the measurement point, based on the coordinates of the weak point, cutting the corrected layout to remove the part of the layout that does not contain the weak point from the corrected layout to obtain a local layout; The step of clearing the measurement points includes: clearing the measurement points in the local layout.

11. The wafer pattern measuring method according to claim 1, wherein: The measurement field of view is a square area; based on the coordinates of the weak point and the measurement field of view, the step of obtaining the critical overlap distance between the measurement point and the adjacent measurement field of view includes: taking the coordinates of the weak point as the measurement point; taking the side length of the measurement field of view as the distance between the measurement point and the adjacent measurement field of view; times, as the critical overlapping distance between adjacent measurement fields of view.

12. The wafer pattern measuring method according to claim 1, wherein: Measuring the pattern on the wafer includes: measuring the photoresist pattern on the wafer after performing an exposure and development process; or measuring the post-etching pattern on the wafer after transferring the photoresist pattern to a film layer on the wafer.

13. A wafer pattern measurement system, characterized in that: include: An acquisition module, used to obtain a verification result of an optical proximity effect correction verification process of a corrected layout, wherein the verification result includes coordinates of a weak point; A distance calculation module, used for obtaining a critical overlap distance between a measurement point and an adjacent measurement field of view based on the coordinates of the weak point and the measurement field of view; A clearing module, used for clearing the measurement points, and removing other measurement points around the measurement points within the critical overlapping distance, and the remaining measurement points are used as processed measurement points; The measuring module is used to measure the pattern formed on the wafer based on the post-processing measurement points to obtain a measurement result.

14. A device, characterized in that The method comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the wafer pattern measurement method according to any one of claims 1 to 12.

15. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the wafer pattern measurement method as described in any one of claims 1-12.

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