Power module structure

Abstract

The invention provides a power module structure. The power module structure comprises a substrate; the copper layer is arranged on the substrate; the metal layer is arranged on the copper layer, and the area of the metal layer is smaller than that of the copper layer; and the wafer is arranged on the metal layer, and the area of the wafer is smaller than that of the metal layer.

Description

Technical Field

[0001] The present disclosure relates to a power module structure, and more particularly to a power module structure with a metal heat conducting material disposed below a chip. Background Art

[0002] Currently, ceramic substrates are often used as wafer carriers in power modules. However, when high-power wafers are placed, local hot spots are easily generated on the ceramic substrate below, making it difficult for heat to dissipate. Summary of the invention

[0003] According to one embodiment of the present disclosure, a power module structure is provided, including: a substrate; a copper layer disposed on the substrate; a metal layer disposed on the copper layer, wherein the area of ​​the metal layer is smaller than the area of ​​the copper layer; and a chip disposed on the metal layer, wherein the area of ​​the chip is smaller than the area of ​​the metal layer.

[0004] In some embodiments, the material of the substrate includes aluminum oxide. In some embodiments, the material of the metal layer includes copper, silver, or aluminum. In some embodiments, the shape of the metal layer includes rectangle, circle, polygon, or trapezoid. In some embodiments, the metal layer contacts the copper layer. In some embodiments, the chip includes a power device. In some embodiments, the chip contacts the metal layer.

[0005] According to an embodiment of the present disclosure, a power module structure is provided, including: a substrate; a copper layer disposed on the substrate; a chip disposed on the copper layer; and a metal layer disposed on the copper layer, surrounding the chip, and the area of ​​the metal layer is smaller than the area of ​​the copper layer.

[0006] In some embodiments, the wafer and the metal layer have different thicknesses. In some embodiments, the wafer and the metal layer are in contact with the copper layer. In some embodiments, the wafer is in contact with the metal layer.

[0007] According to an embodiment of the present disclosure, a power module structure is provided, including: a substrate; a copper layer disposed on the substrate; a first metal layer disposed on the copper layer, wherein the area of ​​the first metal layer is smaller than the area of ​​the copper layer; a second metal layer disposed on the copper layer, wherein the area of ​​the second metal layer is smaller than the area of ​​the copper layer, and the second metal layer is disposed separately from the first metal layer; a first chip disposed on the first metal layer, wherein the area of ​​the first chip is smaller than the area of ​​the first metal layer; and a second chip disposed on the second metal layer, wherein the area of ​​the second chip is smaller than the area of ​​the second metal layer.

[0008] In some embodiments, the shapes of the first metal layer and the second metal layer include rectangle, circle, polygon, or trapezoid. In some embodiments, the shapes of the first metal layer and the second metal layer are different. In some embodiments, the thicknesses of the first metal layer and the second metal layer are different. In some embodiments, the first metal layer and the second metal layer are in contact with the copper layer. In some embodiments, the first wafer is in contact with the first metal layer. In some embodiments, the second wafer is in contact with the second metal layer.

[0009] Generally speaking, for the copper layer on the ceramic substrate, the etching ability of the process and the warping problem caused by thermal expansion need to be considered. Therefore, there needs to be some restrictions on the thickness of the copper layer. However, in the case of setting a high-power chip, a copper layer that is too thin will produce local hot spots, making it difficult for heat to dissipate. In the power module structure disclosed in the present invention, an additional metal layer with high thermal conductivity and electrical conductivity is provided under (or around) the chip to locally thicken the copper layer on the substrate, so that the heat is first evenly transferred to the metal layer and the heating area is expanded, and then more efficiently transferred downward. The metal layer disclosed in the present invention is an accessory for amplifying the heat source of the chip, which can achieve the purpose of uniform heat dissipation and increase the heat dissipation area, and is connected to the copper layer on the substrate.

[0010] The present disclosure utilizes a metal layer with an area larger than the heat source to contact the heat source so that the temperature is evenly transferred. The so-called even transfer means that there is a small temperature difference between the center point and the edge of the metal layer, that is, the metal layer tends to be isothermal (forming a temperature-averaging plate). In addition, the bending strength of the substrate can be increased by bonding the metal layer with the upper copper layer, thereby reducing the warping degree of the substrate.

[0011] The metal layer disclosed in the present invention can be locally thickened according to the circuit layout, multiple metal layers can be arranged on the copper layer at the same time, and each metal layer can be designed into different shapes and thicknesses according to product requirements.

[0012] The present invention mainly adds a metal layer between the chip and the substrate, so that the heat source of the chip is evenly dispersed during the transfer process, which can not only avoid the problem of local high temperature, but also effectively increase the heat dissipation area to cool the chip. The advantages of the present invention include increasing the heat dissipation effect of the chip, reducing the warping degree of the substrate, elastically thickening the local copper layer, and saving the use of copper materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are only used for illustration. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present disclosure.

[0014] Figure 1 According to an embodiment of the present disclosure, a cross-sectional schematic diagram of a power module structure;

[0015] Figure 2A According to one embodiment of the present disclosure, a three-dimensional diagram of a power module structure;

[0016] Figure 2B According to one embodiment of the present disclosure, a three-dimensional diagram of a power module structure;

[0017] Figure 2C According to one embodiment of the present disclosure, a three-dimensional diagram of a power module structure;

[0018] Figure 3 According to an embodiment of the present disclosure, a three-dimensional diagram of a power module structure; and

[0019] Figure 4 According to an embodiment of the present disclosure, a three-dimensional view of a power module structure is provided.

[0020] Description of Figure Numbers:

[0021] 10,110,210,310,410,510: Power module structure

[0022] 12,112,212,312,412,512:Substrate

[0023] 12a: first surface of substrate

[0024] 12b: Second surface of substrate

[0025] 14,114,214,314,414,514: first copper layer

[0026] 16,116,216,316,416,516: Second copper layer

[0027] 18,118,218,318,418:Metal layer

[0028] 20,120,220,320,420: Chip

[0029] 22,122,222,322:Solder paste

[0030] 24,124,224,324: Silver paste

[0031] 518a: first metal layer

[0032] 518b: Second metal layer

[0033] 518c: The third metal layer

[0034] 518d: Fourth metal layer

[0035] 518e: Fifth metal layer

[0036] 520a: first chip

[0037] 520b: Second chip

[0038] 520c: The third chip

[0039] 520d: The fourth chip

[0040] 520e: The fifth chip

[0041] A1: Area of ​​metal layer

[0042] A2: Area of ​​the first copper layer

[0043] A3: Area of ​​the chip

[0044] H1: Thickness of the first metal layer

[0045] H2: thickness of the second metal layer

[0046] H3: Thickness of the third metal layer

[0047] H4: Thickness of the fourth metal layer

[0048] H5: Thickness of the fifth metal layer

[0049] T1: thickness of the wafer

[0050] T2: Thickness of metal layer DETAILED DESCRIPTION

[0051] The following disclosure provides many different embodiments to implement the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosed embodiment describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact.

[0052] It should be understood that additional operating steps may be implemented before, during or after the method, and in other embodiments of the method, some operating steps may be replaced or omitted.

[0053] In addition, spatially related words may be used, such as "below", "below", "lower", "above", "above", "higher" and similar words. These spatially related words are used to facilitate the description of the relationship between one (some) element or feature component and another (some) element or feature component in the diagram. These spatially related words include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to different orientations (rotated 45 degrees or other orientations), the spatially related adjectives used therein will also be interpreted according to the orientation after the turn. In some embodiments of the present disclosure, terms such as "connect", "interconnect", etc. regarding joining and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with other structures being arranged between the two structures. And the terms regarding joining and connection may also include situations where both structures are movable, or both structures are fixed.

[0054] In the specification, the terms "about", "approximately", "generally", "substantially", "same", and "similar" generally indicate that a characteristic value is within plus or minus 15%, or within plus or minus 10%, or within plus or minus 5%, or within plus or minus 3%, or within plus or minus 2%, or within plus or minus 1%, or within plus or minus 0.5% of a given value. The quantity given here is an approximate quantity, that is, in the absence of specific description of "about", "approximately", "generally", "substantially", the meaning of "about", "approximately", "generally", "substantially" can still be implied.

[0055] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe different elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the technology disclosed herein, the first element, component, region, layer or section discussed below can be referred to as a second element, component, region, layer or section.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

[0057] See also Figure 1According to an embodiment of the present disclosure, a power module structure 10 is provided. Figure 1 is a schematic cross-sectional view of the power module structure 10 .

[0058] like Figure 1 As shown, the power module structure 10 includes a substrate 12, a first copper layer 14, a second copper layer 16, a metal layer 18, and a wafer 20. The first copper layer 14 is disposed on a first surface 12a of the substrate 12. The second copper layer 16 is disposed on a second surface 12b of the substrate 12, and the second surface 12b is opposite to the first surface 12a. The metal layer 18 is disposed on the first copper layer 14. The wafer 20 is disposed on the metal layer 18. It is worth noting that the area A1 of the metal layer 18 is smaller than the area A2 of the first copper layer 14, and the area A3 of the wafer 20 is smaller than the area A1 of the metal layer 18.

[0059] In some embodiments, the material of the substrate 12 includes aluminum oxide, but the present disclosure is not limited thereto, and other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when the material of the substrate 12 is aluminum oxide (ceramic material), the composite plate composed of the substrate 12, the first copper layer 14, and the second copper layer 16 is called a ceramic substrate, which serves as a carrier for the chip 20 and has the characteristics of high thermal conductivity and electrical insulation.

[0060] In some embodiments, the material of the metal layer 18 includes a metal material with high thermal conductivity and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto, and other suitable metal materials are also applicable to the present disclosure. In some embodiments, the shape of the metal layer 18 includes a rectangle, a circle, a polygon, or a trapezoid, but the present disclosure is not limited thereto, and other suitable metal layer shapes are also applicable to the present disclosure. Figure 2A-2C ), further illustrating the shape of the metal layer 18.

[0061] In some embodiments, the metal layer 18 is in contact with (bonded to) the first copper layer 14. In some embodiments, the metal layer 18 is bonded to the first copper layer 14 by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 18 is bonded to the first copper layer 14 by solder paste 22.

[0062] In some embodiments, the chip 20 includes power devices, such as high power devices.

[0063] In some embodiments, the wafer 20 is in contact with (bonded to) the metal layer 18. In some embodiments, the wafer 20 is bonded to the metal layer 18 via a silver paste 24, for example, the wafer 20 is bonded to the metal layer 18 via a non-pressure sintering silver paste.

[0064] See also Figure 2A According to an embodiment of the present disclosure, a power module structure 110 is provided. Figure 2A It is a three-dimensional diagram of the power module structure 110 , mainly illustrating the shape of the metal layer in the power module structure 110 .

[0065] like Figure 2A As shown, the power module structure 110 includes a substrate 112, a first copper layer 114, a second copper layer 116, a metal layer 118, and a chip 120. The first copper layer 114 and the second copper layer 116 are disposed on two opposite surfaces of the substrate 112. The metal layer 118 is disposed on the first copper layer 114. The chip 120 is disposed on the metal layer 118. Figure 2A It can be seen that the area of ​​the metal layer 118 is smaller than the area of ​​the first copper layer 114 , and the area of ​​the wafer 120 is smaller than the area of ​​the metal layer 118 .

[0066] In some embodiments, the material of the substrate 112 includes aluminum oxide, but the present disclosure is not limited thereto, and other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when the material of the substrate 112 is aluminum oxide (ceramic material), the composite plate composed of the substrate 112, the first copper layer 114, and the second copper layer 116 is called a ceramic substrate, which serves as a carrier for the chip 120 and has the characteristics of high thermal conductivity and electrical insulation.

[0067] In some embodiments, the material of the metal layer 118 includes a metal material with high thermal conductivity and electrical conductivity, such as copper, silver, or aluminum, but the disclosure is not limited thereto, and other suitable metal materials are also applicable to the disclosure.

[0068] It is worth noting that in Figure 2A In the figure, the shape of the metal layer 118 located below the chip 120 is rectangular, but the present disclosure is not limited thereto. Other suitable metal layer shapes, such as circular, polygonal, or trapezoidal, are also applicable to the present disclosure.

[0069] In some embodiments, the metal layer 118 is in contact with (bonded to) the first copper layer 114. In some embodiments, the metal layer 118 is bonded to the first copper layer 114 by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 118 is bonded to the first copper layer 114 by solder paste 122.

[0070] In some embodiments, the chip 120 includes power devices, such as high power devices.

[0071] In some embodiments, the wafer 120 is in contact with (bonded to) the metal layer 118. In some embodiments, the wafer 120 is bonded to the metal layer 118 via a silver paste 124, for example, the wafer 120 is bonded to the metal layer 118 via a non-pressure sintering silver paste.

[0072] See also Figure 2B According to an embodiment of the present disclosure, a power module structure 210 is provided. Figure 2B It is a three-dimensional diagram of the power module structure 210 , and mainly illustrates the shape of the metal layer in the power module structure 210 .

[0073] like Figure 2B As shown, the power module structure 210 includes a substrate 212 , a first copper layer 214 , a second copper layer 216 , a metal layer 218 , a wafer 220 , a solder paste 222 , and a silver paste 224 . Figure 2B The configuration, material, size relationship between components and bonding method of each component in the power module structure 210 are similar to those of Figure 2A The power module structure 110 shown is not described in detail here. Figure 2B The embodiment shown and Figure 2A The main difference between the embodiments shown is the shape of the metal layer. Figure 2B In the embodiment, the shape of the metal layer 218 located below the chip 220 is circular, but the present disclosure is not limited thereto, and other suitable metal layer shapes are also applicable to the present disclosure.

[0074] See also Figure 2C According to an embodiment of the present disclosure, a power module structure 310 is provided. Figure 2C It is a three-dimensional diagram of the power module structure 310 , mainly illustrating the shape of the metal layer in the power module structure 310 .

[0075] like Figure 2C As shown, the power module structure 310 includes a substrate 312 , a first copper layer 314 , a second copper layer 316 , a metal layer 318 , a wafer 320 , a solder paste 322 , and a silver paste 324 . Figure 2C The configuration, material, size relationship between components and bonding method of each component in the power module structure 310 are similar to those of Figure 2A The power module structure 110 shown is not described in detail here. Figure 2C The embodiment shown and Figure 2A The main difference between the embodiments shown is the shape of the metal layer. Figure 2C In the embodiment, the shape of the metal layer 318 located below the chip 320 is a trapezoid, but the present disclosure is not limited thereto, and other suitable metal layer shapes are also applicable to the present disclosure.

[0076] like Figure 2C As shown, when the shape of the metal layer 318 in the power module structure 310 is a trapezoid, the heat diffusion area will gradually expand from the contact surface between the chip 320 and the metal layer 318 to the first copper layer 314 .

[0077] See also Figure 3 According to an embodiment of the present disclosure, a power module structure 410 is provided. Figure 3 is a perspective view of a power module structure 410 .

[0078] like Figure 3 As shown, the power module structure 410 includes a substrate 412, a first copper layer 414, a second copper layer 416, a metal layer 418, and a chip 420. The first copper layer 414 and the second copper layer 416 are disposed on two opposite surfaces of the substrate 412. The chip 420 is disposed on the first copper layer 414. The metal layer 418 is disposed on the first copper layer 414 and surrounds the chip 420. Figure 3 It can be seen that the area of ​​the metal layer 418 is smaller than the area of ​​the first copper layer 414 .

[0079] In some embodiments, the material of the substrate 412 includes aluminum oxide, but the present disclosure is not limited thereto, and other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when the material of the substrate 412 is aluminum oxide (ceramic material), the composite plate composed of the substrate 412, the first copper layer 414, and the second copper layer 416 is called a ceramic substrate, which serves as a carrier for the chip 420 and has the characteristics of high thermal conductivity and electrical insulation.

[0080] In some embodiments, the chip 420 includes power devices, such as high power devices.

[0081] In some embodiments, the wafer 420 is in contact with (bonded to) the first copper layer 414. In some embodiments, the wafer 420 is bonded to the first copper layer 414 via a silver paste (not shown), for example, the wafer 420 is bonded to the first copper layer 414 via a non-pressure sintering silver paste.

[0082] In some embodiments, the material of the metal layer 418 includes a metal material with high thermal conductivity and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto, and other suitable metal materials are also applicable to the present disclosure. Figure 3 As shown, the shape of the metal layer 418 surrounding the chip 420 in the power module structure 410 is a polygon, but the present disclosure is not limited thereto, and other suitable metal layer shapes, such as rectangle, circle, or trapezoid, are also applicable to the present disclosure.

[0083] In some embodiments, the metal layer 418 is in contact with (bonded to) the first copper layer 414. In some embodiments, the metal layer 418 is bonded to the first copper layer 414 by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the metal layer 418 is bonded to the first copper layer 414 by solder paste (not shown).

[0084] In some embodiments, the thickness T1 of the wafer 420 is the same as the thickness T2 of the metal layer 418. In some embodiments, the thickness T1 of the wafer 420 is different from the thickness T2 of the metal layer 418. For example, the thickness T1 of the wafer 420 is less than the thickness T2 of the metal layer 418. Figure 3 As shown, or alternatively, the thickness T1 of the wafer 420 is greater than the thickness T2 of the metal layer 418 (not shown).

[0085] In some embodiments, the wafer 420 is in contact with the metal layer 418, such as Figure 3 shown.

[0086] See also Figure 4 According to an embodiment of the present disclosure, a power module structure 510 is provided. Figure 4 is a three-dimensional diagram of a power module structure 510 .

[0087] like Figure 4 As shown, the power module structure 510 includes a substrate 512, a first copper layer 514, a second copper layer 516, a plurality of metal layers (e.g., a first metal layer 518a, a second metal layer 518b, a third metal layer 518c, a fourth metal layer 518d, and a fifth metal layer 518e), and a plurality of chips (e.g., a first chip 520a, a second chip 520b, a third chip 520c, a fourth chip 520d, and a fifth chip 520e). The first copper layer 514 and the second copper layer 516 are disposed on two opposite surfaces of the substrate 512. The first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively disposed on the first copper layer 514 and are separated from each other. The first chip 520a is disposed on the first metal layer 518a, the second chip 520b is disposed on the second metal layer 518b, the third chip 520c is disposed on the third metal layer 518c, the fourth chip 520d is disposed on the fourth metal layer 518d, and the fifth chip 520e is disposed on the fifth metal layer 518e. Figure 4It can be seen that the areas of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively smaller than the area of ​​the first copper layer 514, the area of ​​the first chip 520a is smaller than the area of ​​the first metal layer 518a, the area of ​​the second chip 520b is smaller than the area of ​​the second metal layer 518b, the area of ​​the third chip 520c is smaller than the area of ​​the third metal layer 518c, the area of ​​the fourth chip 520d is smaller than the area of ​​the fourth metal layer 518d, and the area of ​​the fifth chip 520e is smaller than the area of ​​the fifth metal layer 518e.

[0088] In some embodiments, the material of the substrate 512 includes aluminum oxide, but the present disclosure is not limited thereto, and other suitable substrate materials are also applicable to the present disclosure. In some embodiments, when the material of the substrate 512 is aluminum oxide (ceramic material), the composite plate composed of the substrate 512, the first copper layer 514, and the second copper layer 516 is called a ceramic substrate, which serves as a carrier for the first chip 520a, the second chip 520b, the third chip 520c, the fourth chip 520d, and the fifth chip 520e, and has the characteristics of high thermal conductivity and electrical insulation.

[0089] In some embodiments, the materials of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e include metal materials with high thermal conductivity and electrical conductivity, such as copper, silver, or aluminum, but the present disclosure is not limited thereto, and other suitable metal materials are also applicable to the present disclosure. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e include rectangles, circles, polygons, or trapezoids, but the present disclosure is not limited thereto, and other suitable metal layer shapes are also applicable to the present disclosure. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are the same. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are different. In some embodiments, the shapes of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are partially the same and partially different. For example, the shape of the first metal layer 518a is circular, the shape of the second metal layer 518b is rectangular, the shape of the third metal layer 518c is rectangular, the shape of the fourth metal layer 518d is polygonal, and the shape of the fifth metal layer 518e is rectangular. Figure 4 shown.

[0090] In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively in contact with (bonded to) the first copper layer 514. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively bonded to the first copper layer 514 by soldering or diffusion bonding. In some embodiments, in the soldering bonding method, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are respectively bonded to the first copper layer 514 by solder paste (not shown).

[0091] In some embodiments, the first chip 520a, the second chip 520b, the third chip 520c, the fourth chip 520d, and the fifth chip 520e include power devices, such as high-power devices.

[0092] In some embodiments, the first chip 520a contacts (bonds) the first metal layer 518a, the second chip 520b contacts (bonds) the second metal layer 518b, the third chip 520c contacts (bonds) the third metal layer 518c, the fourth chip 520d contacts (bonds) the fourth metal layer 518d, and the fifth chip 520e contacts (bonds) the fifth metal layer 518e. In some embodiments, the chips and the metal layers are bonded by silver paste (not shown), for example, the chips and the metal layers are bonded by non-pressure sintering silver paste.

[0093] In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e have the same thickness. In some embodiments, the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e have different thicknesses. In some embodiments, the thicknesses of the first metal layer 518a, the second metal layer 518b, the third metal layer 518c, the fourth metal layer 518d, and the fifth metal layer 518e are partially the same and partially different. For example, the thickness H1 of the first metal layer 518a is the same as the thickness H4 of the fourth metal layer 518d, the thickness H2 of the second metal layer 518b is the same as the thickness H3 of the third metal layer 518c and the thickness H5 of the fifth metal layer 518e, and the thickness H1 of the first metal layer 518a is different from the thickness H2 of the second metal layer 518b, the thickness H3 of the third metal layer 518c, and the thickness H5 of the fifth metal layer 518e. Figure 4 shown.

[0094] Generally speaking, for the copper layer on the ceramic substrate, the etching ability of the process and the warping problem caused by thermal expansion need to be considered. Therefore, there needs to be some restrictions on the thickness of the copper layer. However, in the case of setting a high-power chip, a copper layer that is too thin will produce local hot spots, making it difficult for heat to dissipate. In the power module structure disclosed in the present invention, an additional metal layer with high thermal conductivity and electrical conductivity is provided under (or around) the chip to locally thicken the copper layer on the substrate, so that the heat is first evenly transferred to the metal layer and the heating area is expanded, and then more efficiently transferred downward. The metal layer disclosed in the present invention is an accessory for amplifying the heat source of the chip, which can achieve the purpose of uniform heat dissipation and increase the heat dissipation area, and is connected to the copper layer on the substrate.

[0095] The present disclosure utilizes a metal layer with an area larger than the heat source to contact the heat source so that the temperature is evenly transferred. The so-called even transfer means that there is a small temperature difference between the center point and the edge of the metal layer, that is, the metal layer tends to be isothermal (forming a temperature-averaging plate). In addition, the bending strength of the substrate can be increased by bonding the metal layer with the upper copper layer, thereby reducing the warping degree of the substrate.

[0096] The metal layer disclosed in the present invention can be locally thickened according to the circuit layout, multiple metal layers can be arranged on the copper layer at the same time, and each metal layer can be designed into different shapes and thicknesses according to product requirements.

[0097] The present invention mainly adds a metal layer between the chip and the substrate, so that the heat source of the chip is evenly dispersed during the transfer process, which can not only avoid the problem of local high temperature, but also effectively increase the heat dissipation area to cool the chip. The advantages of the present invention include increasing the heat dissipation effect of the chip, reducing the warping degree of the substrate, elastically thickening the local copper layer, and saving the use of copper materials.

[0098] The components of some of the above-mentioned embodiments are provided so that those skilled in the art to which the present disclosure belongs can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined by the scope of the appended claims. In addition, although the present disclosure has been disclosed as above with several preferred embodiments, it is not intended to limit the present disclosure.

[0099] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that may be realized using the present disclosure should or may be realized in any single embodiment of the present disclosure. Rather, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussion of features and advantages and similar language throughout this specification may, but does not necessarily, refer to the same embodiment.

[0100] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Based on the description herein, one skilled in the relevant art will appreciate that the present disclosure may be implemented without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present disclosure.

Claims

1. A power module structure, comprising: substrate; A copper layer is disposed on the substrate; A metal layer is disposed on the copper layer, wherein an area of ​​the metal layer is smaller than an area of ​​the copper layer; as well as A chip is disposed on the metal layer, wherein the area of ​​the chip is smaller than the area of ​​the metal layer.

2. The power module structure according to claim 1, wherein the material of the substrate comprises aluminum oxide. 3 . The power module structure according to claim 1 , wherein the material of the metal layer comprises copper, silver, or aluminum. 4 . The power module structure according to claim 1 , wherein the shape of the metal layer comprises a rectangle, a circle, a polygon, or a trapezoid.

5. The power module structure according to claim 1, wherein the metal layer is in contact with the copper layer.

6. The power module structure according to claim 1, wherein the die includes power components.

7. The power module structure according to claim 1, wherein the wafer is in contact with the metal layer.

8. A power module structure, comprising: substrate; A copper layer is disposed on the substrate; A wafer, disposed on the copper layer; as well as The metal layer is disposed on the copper layer and surrounds the wafer, and the area of ​​the metal layer is smaller than the area of ​​the copper layer.

9. The power module structure according to claim 8, wherein the wafer and the metal layer have different thicknesses.

10. The power module structure according to claim 8, wherein the wafer and the metal layer are in contact with the copper layer.

11. The power module structure according to claim 8, wherein the wafer is in contact with the metal layer.

12. A power module structure, comprising: substrate; A copper layer is disposed on the substrate; A first metal layer is disposed on the copper layer, wherein an area of ​​the first metal layer is smaller than an area of ​​the copper layer; a second metal layer, disposed on the copper layer, wherein an area of ​​the second metal layer is smaller than an area of ​​the copper layer, and the second metal layer is disposed separately from the first metal layer; A first chip is disposed on the first metal layer, wherein an area of ​​the first chip is smaller than an area of ​​the first metal layer; as well as The second chip is disposed on the second metal layer, wherein the area of ​​the second chip is smaller than the area of ​​the second metal layer. 13 . The power module structure according to claim 12 , wherein the shapes of the first metal layer and the second metal layer include rectangle, circle, polygon, or trapezoid.

14. The power module structure according to claim 12, wherein the first metal layer and the second metal layer have different shapes.

15. The power module structure according to claim 12, wherein the first metal layer and the second metal layer have different thicknesses.

16. The power module structure of claim 12, wherein the first metal layer and the second metal layer are in contact with the copper layer.

17. The power module structure of claim 12, wherein the first wafer is in contact with the first metal layer.

18. The power module structure of claim 12, wherein the second wafer is in contact with the second metal layer.

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