Frequency multiplier

Abstract

The invention discloses a frequency multiplier, which simplifies the circuit structure of the frequency multiplier and reduces the cost. The frequency multiplier comprises a dual-input NOR gate, a first low-pass filter, a dual-input exclusive-OR gate, a first PMOS transistor P2, an N-type FDSOI transistor M2, a comparator, a first capacitor C2 and a hysteresis comparator. Two input ends of the double-input NOR gate respectively receive an enable signal and a clock signal; the output end of the double-input NOR gate is connected with the input end of the first low-pass filter and the first input end of the double-input XOR gate; the output end of the first low-pass filter is connected with the second input end of the double-input exclusive-OR gate; the output end of the double-input exclusive-OR gate is connected with the grid electrode of the P2 and the grid electrode of the M2; the drain electrode of the P2 is connected with the drain electrode of the M2, the input end of the comparator, one end of the C2 and the input end of the hysteresis comparator; the output end of the comparator is connected with the back gate of the M2; the source electrode of P2 is connected with the power supply end, and the source electrode of M2 is grounded.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a frequency multiplier. Background Art

[0002] The clock oscillator is responsible for generating the clock signal. The clock oscillator is easy to control the accuracy at low frequencies, but the control accuracy is easily disturbed at high frequencies, resulting in a decrease in the stability and accuracy of the clock signal.

[0003] A frequency multiplier is a circuit that can increase the frequency of an input signal to a multiple of the original frequency. The combination of a clock oscillator and a frequency multiplier is a key technology for achieving precise control of high-frequency clock signals: the clock oscillator is responsible for generating a stable low-frequency clock signal, while the frequency multiplier is responsible for multiplying the frequency of the low-frequency clock signal to meet the needs of high-frequency applications.

[0004] However, existing frequency multipliers have the problems of complex circuit structure and high cost. Summary of the invention

[0005] In view of the above problems, the present application provides a frequency multiplier to simplify the circuit structure of the frequency multiplier and reduce the cost. The specific solution is as follows:

[0006] The present application provides a frequency multiplier, comprising: a dual-input NOR gate, a first low-pass filter, a dual-input XOR gate, a first PMOS tube, an N-type FDSOI transistor, a comparator, a first capacitor, and a hysteresis comparator;

[0007] Wherein, the first input terminal of the dual-input NOR gate is used to receive an enable signal; the enable signal is valid at a low level;

[0008] The second input terminal of the dual-input NOR gate is used as an input terminal of the frequency multiplier to receive the clock signal;

[0009] The output terminal of the dual-input NOR gate is connected to the input terminal of the first low-pass filter and the first input terminal of the dual-input XOR gate;

[0010] An output terminal of the first low-pass filter is connected to a second input terminal of the dual-input XOR gate;

[0011] The output end of the dual-input XOR gate is connected to the gate of the first PMOS tube and the gate of the N-type FDSOI transistor;

[0012] The drain of the first PMOS tube is connected to the drain of the N-type FDSOI transistor, the input end of the comparator, one end of the first capacitor and the input end of the hysteresis comparator;

[0013] The reference terminal of the comparator is used to receive a reference voltage; the output terminal of the comparator is connected to the back gate of the N-type FDSOI transistor;

[0014] The output of the hysteresis comparator serves as the output of the frequency multiplier;

[0015] The power supply terminal of the dual-input NOR gate, the source of the first PMOS tube and the power supply terminal of the hysteresis comparator are connected to receive a power supply signal;

[0016] The ground terminal of the dual-input NOR gate, the ground terminal of the first low-pass filter, the source of the N-type FDSOI transistor, the other end of the first capacitor and the ground terminal of the hysteresis comparator are all grounded.

[0017] In a possible implementation, the dual-input NOR gate includes: a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0018] Wherein, the source of the second PMOS tube is the power supply terminal of the dual-input NOR gate;

[0019] The gate of the second PMOS tube is the first input terminal of the dual-input NOR gate;

[0020] The drain of the second PMOS tube is connected to the source of the third PMOS tube;

[0021] The gate of the third PMOS tube is the second input terminal of the dual-input NOR gate;

[0022] The drain of the third PMOS tube is connected to the drain of the first NMOS tube and the drain of the second NMOS tube;

[0023] The gate of the first NMOS tube is connected to the gate of the second PMOS tube;

[0024] The gate of the second NMOS tube is connected to the gate of the third PMOS tube;

[0025] The source of the first NMOS tube is connected to the source of the second NMOS tube and serves as the ground terminal of the dual-input NOR gate.

[0026] In a possible implementation, the first low-pass filter is an RC low-pass filter.

[0027] In a possible implementation, the hysteresis comparator includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube;

[0028] Wherein, the source of the fourth PMOS tube and the drain of the fifth NMOS tube are connected to serve as the power supply terminal of the hysteresis comparator;

[0029] The gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to serve as the input end of the hysteresis comparator;

[0030] The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube and the source of the sixth PMOS tube;

[0031] The drain of the fifth PMOS tube is connected to the drain of the third NMOS tube, the gate of the sixth PMOS tube and the gate of the fifth NMOS tube, serving as the output end of the hysteresis comparator;

[0032] The source of the third NMOS tube is connected to the drain of the fourth NMOS tube and the source of the fifth NMOS tube;

[0033] The source of the fourth NMOS tube is connected to the drain of the sixth PMOS tube and serves as the ground terminal of the hysteresis comparator.

[0034] In a possible implementation, the N-type FDSOI transistor is a transistor with a flipped well structure using a FDSOI process.

[0035] In a possible implementation, the back gate voltage of the tube with the flipped well structure is adjusted in the range of 0~2V; when the comparator outputs a low level, the back gate voltage of the tube with the flipped well structure is reduced to 0V; when the comparator outputs a high level, the back gate voltage of the tube with the flipped well structure is increased to 2V.

[0036] In a possible implementation, the frequency multiplier further includes: a second low-pass filter;

[0037] Wherein, the input terminal of the second low-pass filter is connected to the output terminal of the comparator;

[0038] An output terminal of the second low-pass filter is connected to a back gate of an N-type FDSOI transistor;

[0039] A ground terminal of the second low pass filter is grounded.

[0040] In a possible implementation, the second low-pass filter is an RC low-pass filter.

[0041] In a possible implementation, the frequency multiplier further includes: a first inverter and a second inverter;

[0042] The input end of the first inverter is connected to the output end of the first low-pass filter; the output end of the first inverter is connected to the input end of the second inverter; and the output end of the second inverter is connected to the second input end of the dual-input XOR gate.

[0043] By means of the above technical scheme, the dual-input NOR gate in the frequency multiplier provided by the present application controls the charging process of the first low-pass filter according to the enable signal and the clock signal, so that the first low-pass filter generates a phase delay, and then uses the dual-input XOR gate to realize the frequency multiplication of the input clock signal; the first PMOS tube and the N-type FDSOI transistor control the charging and discharging of the first capacitor according to the output signal of the dual-input XOR gate; the comparator adjusts the back gate voltage of the N-type FDSOI transistor according to the comparison result between the voltage across the first capacitor and the reference voltage, and the on-resistance of the N-type FDSOI transistor is modulated by the back gate voltage, thereby changing the discharge speed of the first capacitor; the hysteresis comparator shapes the voltage across the first capacitor and enhances the resistance to noise, and finally outputs a double-frequency clock signal with a variable duty cycle. The frequency multiplier circuit structure provided by the present application is simple and low-cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0045] Figure 1 A circuit diagram of a frequency multiplier provided in this application;

[0046] Figure 2 The present application provides a method in which when the enable signal EN_N is at a low level, Figure 1 The waveform diagram of the multi-channel signals in the frequency multiplier shown;

[0047] Figure 3 Another embodiment provided by the present application is that when the enable signal EN_N is at a low level, Figure 1 The waveform diagram of the multi-channel signals in the frequency multiplier shown;

[0048] Figure 4 A circuit schematic diagram of another frequency multiplier provided in this application. DETAILED DESCRIPTION

[0049] In the following description, in order to ensure the accuracy of the citation and the fluency of reading, the key technical terms, abbreviations or abbreviations involved in the text are summarized and explained as follows:

[0050] FDSOI: Fully Depleted Silicon on Insulator, fully depleted silicon on insulator;

[0051] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxide semiconductor field effect transistor, referred to as MOS tube;

[0052] NMOS tube: N-type channel MOS tube;

[0053] PMOS tube: P-type channel MOS tube.

[0054] In analog circuit design, the frequency of the clock signal often needs to be adjusted according to actual needs to meet the requirements of different application scenarios. The clock oscillator is responsible for generating these clock signals. The clock oscillator is easy to control the accuracy at low frequencies because the stability and predictability of the clock signal are high, making the generation of the clock signal relatively simple and accurate. However, when the frequency increases to the high frequency range, the precision control of the clock oscillator becomes complicated and is susceptible to various interference factors, such as power supply noise, temperature changes, and non-ideal characteristics of circuit components, which may cause the stability and accuracy of the clock signal to decrease. Therefore, how to achieve precise control of high-frequency clock signals has become an important technical challenge. It should be noted here that high frequency and low frequency are relative concepts without fixed boundaries; high frequency refers to signals with higher frequencies, while low frequency is just the opposite.

[0055] A frequency multiplier is a circuit that can increase the frequency of an input signal to a multiple of the original frequency. Specifically, if the frequency of the input signal of the frequency multiplier is f1, then the frequency of the output signal of the frequency multiplier will be n×f1, where n is the frequency multiplication factor, and n is a positive integer.

[0056] The combination of clock oscillator and frequency multiplier is a key technology to achieve precise control of high-frequency clock signals. Specifically, the clock oscillator is responsible for generating a stable low-frequency clock signal, while the frequency multiplier is responsible for multiplying the frequency of the low-frequency clock signal to meet the application requirements of high-precision high-frequency clock signals. However, existing frequency multipliers have problems such as complex circuit structure and high cost.

[0057] To solve the above problems, an embodiment of the present application provides a frequency multiplier, which realizes frequency multiplication of an input clock signal (low-frequency clock signal) through a simple circuit structure design, generates a clock signal (high-frequency clock signal) with a frequency twice that of the input, and performs back-gate modulation based on an N-type FDSOI transistor to improve the duty cycle of the high-frequency clock signal.

[0058] A frequency multiplier provided in an embodiment of the present application is described in detail below in conjunction with the accompanying drawings. A person skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

[0059] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0060] See also Figure 1 , a frequency multiplier provided in an embodiment of the present application includes: a dual-input NOR gate 100, a first low-pass filter 200, a dual-input XOR gate XOR0, a first PMOS transistor P2, an N-type (i.e., N-channel) FDSOI transistor M2, a comparator COMP1, a first capacitor C2, and a hysteresis comparator 300;

[0061] Among them, the first input end of the dual-input NOR gate 100 is used to receive the enable signal EN_N; the enable signal EN_N is low level effective, and is used to control the opening and closing of the dual-input NOR gate 100 (because the dual-input NOR gate 100 is located at the front stage of the frequency multiplier, the enable signal EN_N of the dual-input NOR gate 100 is also the enable signal of the frequency multiplier, which is used to control the opening and closing of the frequency multiplier);

[0062] The second input terminal of the dual-input NOR gate 100 is used as the input terminal of the frequency multiplier to receive the clock signal OSC_REF output by the clock oscillator;

[0063] The output terminal of the dual-input NOR gate 100 is connected to the input terminal of the first low-pass filter 200 and the first input terminal of the dual-input XOR gate XOR0;

[0064] The output terminal of the first low-pass filter 200 is connected to the second input terminal of the dual-input XOR gate XOR0;

[0065] The output end of the dual-input XOR gate XOR0 is connected to the gate G of the first PMOS transistor P2 and the gate G of the N-type FDSOI transistor M2;

[0066] The drain D of the first PMOS transistor P2 is connected to the drain D of the N-type FDSOI transistor M2, the input terminal of the comparator COMP1, one end of the first capacitor C2 and the input terminal of the hysteresis comparator 300;

[0067] The reference terminal of the comparator COMP1 is used to receive a reference voltage VB; the reference voltage VB is a controllable and adjustable input reference voltage signal;

[0068] The output terminal of the comparator COMP1 is connected to the back gate BG of the N-type FDSOI transistor M2;

[0069] The output terminal of the hysteresis comparator 300 serves as the output terminal of the frequency multiplier;

[0070] The power supply terminal of the dual-input NOR gate 100, the source S of the first PMOS transistor P2 and the power supply terminal of the hysteresis comparator 300 are connected to receive the power supply signal VCC;

[0071] The ground terminal of the dual-input NOR gate 100 , the ground terminal of the first low-pass filter 200 , the ground terminal of the second low-pass filter 300 , the source S of the N-type FDSOI transistor M2 , the other end of the first capacitor C2 and the ground terminal of the hysteresis comparator 300 are all grounded GND.

[0072] Next, Figure 1 The working principle of the frequency multiplier shown is analyzed:

[0073] The two-input NOR gate 100 is a basic gate circuit in a digital logic circuit, which realizes a logic NOR function. Specifically, the two-input NOR gate 100 has two input terminals and one output terminal. When any input is at a high level (i.e., logic "1"), the output is at a low level (i.e., logic "0"); only when all inputs are at a low level, the output is at a high level.

[0074] The two input terminals of the dual-input NOR gate 100 are used to receive the enable signal EN_N and the clock signal OSC_REF respectively. The enable signal EN_N is low level valid and is used to control the opening and closing of the dual-input NOR gate 100 (hereinafter referred to as EN_N signal); the clock signal OSC_REF signal is a square wave signal with a fixed frequency (a rectangular wave with a duty cycle of 50% is called a square wave. A rectangular wave is a basic pulse signal waveform. The duty cycle is the ratio of the occupation time of the high-level signal in the pulse signal to a complete cycle time). Figure 2 As shown ( Figure 2 When the enable signal EN_N is at a low level, Figure 1 The waveform diagram of multiple signals in the frequency multiplier is shown in the figure).

[0075] When the enable signal EN_N is at a low level, the dual-input NOR gate 100 is activated, allowing the output level to change according to the level change of the clock signal OSC_REF (high level or low level), thereby controlling the charging process of the first low-pass filter 200. Specifically, when and only when the enable signal EN_N and the clock signal OSC_REF are both at a low level, the dual-input NOR gate 100 can output a high level and charge the first low-pass filter 200; otherwise, the dual-input NOR gate 100 outputs a low level and stops charging the first low-pass filter 200. Figure 2 In FIG. 1 , the output signal of the dual-input NOR gate 100 is recorded as OUT_100.

[0076] The first low-pass filter 200 is an electronic filtering device that allows low-frequency signals to pass through and blocks high-frequency signals from passing through. When the signal passes through the first low-pass filter 200, a phase delay will occur due to the energy storage and release process of the signal by the components (such as capacitors, etc.) inside the first low-pass filter 200. This delay is the time offset of the signal waveform relative to the original signal. The phase delay is related to multiple key factors such as the cutoff frequency of the first low-pass filter 200, the filter order, the filter type, the internal component characteristics, and the frequency of the input signal. In practical applications, a suitable filter can be selected according to specific needs.

[0077] The dual-input XOR gate XOR0 is also a basic gate circuit in digital logic circuits, which realizes the logic XOR function. Specifically, the dual-input XOR gate XOR0 has two input terminals and one output terminal. When the two input signals are different (one is low level and the other is high level), the output is high level; when the two input signals are the same (both are low level or both are high level), the output is low level.

[0078] In the embodiment of the present application, the phase delay of the first low-pass filter 200 can be designed to be 135 degrees, that is, the output signal OUT_200 of the first low-pass filter 200 is delayed by 135 degrees relative to the output signal OUT_100 of the dual-input NOR gate 100. Figure 2 Then, after the output signal OUT_100 of the dual-input NOR gate 100 and the output signal OUT_200 of the first low-pass filter 200 are respectively input into the two input terminals of the dual-input XOR gate XOR0, based on the above characteristics of the dual-input XOR gate XOR0, it can be known that the output signal OUT_XOR0 of the dual-input XOR gate XOR0 is a signal with a frequency doubled by the clock signal OSC_REF, as shown in FIG. Figure 2 At this time, the dual-input XOR gate XOR0 is equivalent to an edge detection circuit, and when the rising edge or falling edge of the clock signal OSC_REF appears, a falling pulse with a fixed pulse width is generated.

[0079] When the output signal OUT_XOR0 of the dual-input XOR gate XOR0 is at a low level, the first PMOS tube P2 is turned on and the N-type FDSOI transistor M2 is turned off, and the power signal VCC charges the first capacitor C2 through the first PMOS tube P2; when the output signal OUT_XOR0 of the dual-input XOR gate XOR0 is at a high level, the first PMOS tube P2 is turned off and the N-type FDSOI transistor M2 is turned on, and the first capacitor C2 is discharged through the on-resistance of the N-type FDSOI transistor M2, and the discharge slope depends on the size of the on-resistance (the on-resistance is the degree of resistance to current by the transistor in the on state).

[0080] The on-resistance of the N-type FDSOI transistor M2 is controlled by the back-gate voltage of the N-type FDSOI transistor M2. Specifically, the FDSOI transistor is a transistor manufactured based on the FDSOI technology. FDSOI is an advanced semiconductor manufacturing technology that realizes the full depletion effect of the transistor by forming an ultra-thin silicon film on an insulator and making transistors on the silicon film. This technology can significantly improve the performance and power efficiency of the transistor. In the FDSOI transistor, the back gate is located on the back side of the substrate of the transistor and is isolated from the channel by an insulating layer. The back-gate voltage affects the on-resistance and other key parameters of the FDSOI transistor. Therefore, the on-resistance of the FDSOI transistor can be flexibly changed by back-gate modulation (back-gate modulation refers to the adjustment of the on-resistance and other key parameters of the transistor by changing the back-gate voltage of the transistor in the FDSOI transistor), thereby achieving precise control of the circuit performance; wherein, increasing the back-gate voltage will reduce the on-resistance, while reducing the back-gate voltage will increase the on-resistance. FDSOI transistors are divided into N-type FDSOI transistors and P-type FDSOI transistors according to different doping types. In the embodiment of the present application, N-type FDSOI transistors are selected according to circuit design requirements.

[0081] When the voltage across the first capacitor C2 is lower than the reference voltage VB, the comparator COMP1 outputs a low level, at which time the back gate voltage of the N-type FDSOI transistor M2 decreases. Due to the decrease in the back gate voltage, the on-resistance of the N-type FDSOI transistor M2 increases, thereby slowing down the discharge speed of the first capacitor C2; when the voltage across the first capacitor C2 is higher than the reference voltage VB, the comparator COMP1 outputs a high level, at which time the back gate of the N-type FDSOI transistor M2 increases. Due to the increase in the back gate voltage, the on-resistance of the N-type FDSOI transistor M2 decreases, thereby accelerating the discharge speed of the first capacitor C2. It can be seen that by changing the reference voltage VB, the rate of decrease of the voltage across the first capacitor C2 can be freely adjusted.

[0082] The hysteresis comparator 300, also known as a hysteresis comparator or a Schmitt trigger, is a comparator circuit with a hysteresis loop transmission characteristic. The hysteresis comparator 300 has two different threshold voltages - an upper threshold and a lower threshold. When the input signal of the hysteresis comparator 300 exceeds the upper threshold, the hysteresis comparator 300 outputs a high level; when the input signal of the hysteresis comparator 300 drops below the lower threshold, the hysteresis comparator 300 outputs a low level; when the input signal of the hysteresis comparator 300 fluctuates between the upper threshold and the lower threshold, the output signal remains unchanged. This characteristic enables the hysteresis comparator 300 to process input signals with fluctuations or noise, and reshape them into output signals with clear edges and stable levels. At the same time, this characteristic makes the hysteresis comparator 300 highly resistant to noise and fluctuations, avoiding frequent switching of the output signal due to slight changes in the input signal.

[0083] After the voltage across the first capacitor C2 is shaped and the noise effect is reduced by the hysteresis comparator 300, a rectangular wave signal whose duty cycle changes with the decreasing rate of the voltage across the first capacitor C2 is obtained as the inverter output signal OSC_D. The inverter output signal OSC_D has the same frequency as the output signal OUT_XOR0 of the dual-input XOR gate XOR0, which is a twice-frequency signal of the clock signal OSC_REF.

[0084] In summary, the embodiment of the present application realizes frequency multiplication of the input clock signal OSC_REF (low-frequency clock signal) through a simple circuit structure design, and performs back-gate modulation based on the FDSOI transistor, and only needs to change the reference voltage VB to adjust the duty cycle of the inverter output signal OSC_D.

[0085] Alternatively, the embodiment of the present application can also design the phase delay of the first low-pass filter 200 to be 45 degrees, that is, the output signal OUT_200 of the first low-pass filter 200 is delayed by 45 degrees relative to the output signal OUT_100 of the dual-input NOR gate 100. Figure 3 Then, after the output signal OUT_100 of the dual-input NOR gate 100 and the output signal OUT_200 of the first low-pass filter 200 are respectively input into the two input terminals of the dual-input XOR gate XOR0, based on the above characteristics of the dual-input XOR gate XOR0, it can be known that the output signal OUT_XOR0 of the dual-input XOR gate XOR0 is also a signal with a frequency doubled by the clock signal OSC_REF, as shown in FIG. Figure 3 At this time, the dual-input XOR gate XOR0 is also equivalent to an edge detection circuit, and when the rising edge or falling edge of the clock signal OSC_REF appears, a rising pulse with a fixed pulse width is generated.

[0086] In a possible implementation, the N-type FDSOI transistor M2 in any of the above-mentioned embodiments can use a flip well (flip well structure) tube of the FDSOI process. In the FDSOI process, the flip well tube technology can flexibly change the threshold voltage, on-resistance and other key parameters of the transistor by adjusting the bias voltage of the well, thereby achieving precise control of the circuit performance. This technology provides important support for low-power and high-performance circuit design. In the present embodiment of the application, for example, it can be set as follows: the back gate voltage adjustment range of the flip well tube of the FDSOI process is 0~2V; when the voltage across the first capacitor C2 is lower than the reference voltage VB, the comparator COMP1 outputs a low level, and the back gate voltage of the N-type FDSOI transistor M2 is reduced to 0V; when the voltage across the first capacitor C2 is higher than the reference voltage VB, the comparator COMP1 outputs a high level, and the back gate of the N-type FDSOI transistor M2 is increased to 2V.

[0087] In one possible implementation, see Figure 1 , the dual-input NOR gate 100 in any of the above-mentioned embodiments includes: a second PMOS transistor P0, a third PMOS transistor P1, a first NMOS transistor M0 and a second NMOS transistor M1;

[0088] The source of the second PMOS tube P0 is the power supply terminal of the dual-input NOR gate 100;

[0089] The gate of the second PMOS transistor P0 is the first input terminal of the dual-input NOR gate 100;

[0090] The drain of the second PMOS tube P0 is connected to the source of the third PMOS tube P1;

[0091] The gate of the third PMOS tube P1 is the second input terminal of the dual-input NOR gate 100;

[0092] The drain of the third PMOS tube P1 is connected to the drain of the first NMOS tube M0 and the drain of the second NMOS tube M1;

[0093] The gate of the first NMOS transistor M0 is connected to the gate of the second PMOS transistor P0;

[0094] The gate of the second NMOS tube M1 is connected to the gate of the third PMOS tube P1;

[0095] The source of the first NMOS transistor M0 and the source of the second NMOS transistor M1 are connected to serve as the ground terminal of the dual-input NOR gate 100 .

[0096] In a possible implementation, the first low-pass filter 200 in any of the above embodiments is an RC low-pass filter, but the invention is not limited thereto. Figure 1The first low-pass filter 200 includes a first resistor R0 and a second capacitor C0; wherein one end of the first resistor R0 is the input end of the first low-pass filter 200; the other end of the first resistor R0 is connected to one end of the second capacitor C0 as the output end of the first low-pass filter 200; the other end of the second capacitor C0 is the ground end of the first low-pass filter 200.

[0097] In a possible implementation, the hysteresis comparator 300 in any of the above embodiments includes: a fourth PMOS transistor P3, a fifth PMOS transistor P4, a sixth PMOS transistor P5, a third NMOS transistor M3, a fourth NMOS transistor M4 and a fifth NMOS transistor M5;

[0098] Wherein, the source of the fourth PMOS transistor P3 and the drain of the fifth NMOS transistor M5 are connected to serve as the power supply terminal of the hysteresis comparator 300;

[0099] The gate of the fourth PMOS transistor P3, the gate of the fifth PMOS transistor P4, the gate of the third NMOS transistor M3 and the gate of the fourth NMOS transistor M4 are connected to serve as the input end of the hysteresis comparator 300;

[0100] The drain of the fourth PMOS tube P3 is connected to the source of the fifth PMOS tube P4 and the source of the sixth PMOS tube P5;

[0101] The drain of the fifth PMOS transistor P4 is connected to the drain of the third NMOS transistor M3, the gate of the sixth PMOS transistor P5 and the gate of the fifth NMOS transistor M5, serving as the output end of the hysteresis comparator 300;

[0102] The source of the third NMOS tube M3 is connected to the drain of the fourth NMOS tube M4 and the source of the fifth NMOS tube M5;

[0103] The source of the fourth NMOS transistor M4 and the drain of the sixth PMOS transistor P5 are connected to serve as the ground terminal of the hysteresis comparator 300 .

[0104] In one possible implementation, see Figure 4 , any of the frequency multipliers provided above further includes: a second low-pass filter 400;

[0105] Wherein, the input terminal of the second low-pass filter 400 is connected to the output terminal of the comparator COMP1;

[0106] The output terminal of the second low-pass filter 400 is connected to the back gate of the N-type FDSOI transistor M2;

[0107] A ground terminal of the second low pass filter 400 is grounded.

[0108] The second low-pass filter 400 is used to filter out high-frequency noise in the back-gate voltage, thereby stabilizing the back-gate voltage.

[0109] In a possible implementation, the second low-pass filter 400 may also be an RC low-pass filter. Figure 4 The second low-pass filter 400 includes a second resistor R1 and a third capacitor C1; wherein one end of the second resistor R1 is the input end of the second low-pass filter 400; the other end of the second resistor R1 is connected to one end of the third capacitor C1 as the output end of the second low-pass filter 400; the other end of the third capacitor C1 is the ground end of the second low-pass filter 400.

[0110] In one possible implementation, see Figure 4 Any of the frequency multipliers provided above may also include: a first inverter INV0 and a second inverter INV1; the input end of the first inverter INV0 is connected to the output end of the first low-pass filter 200; the output end of the first inverter INV0 is connected to the input end of the second inverter INV1; the output end of the second inverter INV1 is connected to the second input end of the dual-input XOR gate XOR0.

[0111] Specifically, the basic function of the inverter is to flip the phase of the input signal by 180 degrees, that is, when the input signal is high, the inverter will output a low level; and when the input signal is low, the inverter will output a high level. When the first inverter INV0 and the second inverter INV1 are connected in series, the first inverter INV0 will invert the input signal; the second inverter INV1 will invert the inverted signal output by the first inverter INV0 again to restore it to the original signal direction. In this way, after the two inverters are connected in series, the signal is inverted twice as a whole, but the output signal and the input signal are still consistent in phase.

[0112] In addition to phase reversal, the inverter also has the function of waveform amplification. When two inverters are connected in series, they act as operational amplifiers and can play a very significant role in signal amplification. This is because each inverter amplifies its input signal and then outputs it. Therefore, when two inverters are connected in series, the input signal is amplified twice, thereby obtaining a larger output signal amplitude. This amplification effect can improve the attenuation generated when the signal passes through the first low-pass filter 200.

[0113] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present application. Therefore, the embodiments of the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features disclosed herein.

Claims

1. A frequency multiplier, characterized in that: include: A dual-input NOR gate (100), a first low-pass filter (200), a dual-input XOR gate (XOR0), a first PMOS tube (P2), an N-type FDSOI transistor (M2), a comparator (COMP1), a first capacitor (C2), and a hysteresis comparator (300); The first input terminal of the dual-input NOR gate (100) is used to receive an enable signal (EN_N); the enable signal (EN_N) is valid at a low level; The second input terminal of the dual-input NOR gate (100) is used as an input terminal of the frequency multiplier to receive the clock signal (OSC_REF); The output end of the dual-input NOR gate (100) is connected to the input end of the first low-pass filter (200) and the first input end of the dual-input XOR gate (XOR0); The output terminal of the first low-pass filter (200) is connected to the second input terminal of the dual-input XOR gate (XOR0); The output end of the dual-input XOR gate (XOR0) is connected to the gate of the first PMOS tube (P2) and the gate of the N-type FDSOI transistor (M2); The drain of the first PMOS tube (P2) is connected to the drain of the N-type FDSOI transistor (M2), the input end of the comparator (COMP1), one end of the first capacitor (C2) and the input end of the hysteresis comparator (300); A reference terminal of the comparator (COMP1) is used to receive a reference voltage (VB); an output terminal of the comparator (COMP1) is connected to a back gate of an N-type FDSOI transistor (M2); The output end of the hysteresis comparator (300) serves as the output end of the frequency multiplier; The power supply end of the dual-input NOR gate (100), the source of the first PMOS tube (P2) and the power supply end of the hysteresis comparator (300) are connected to receive a power supply signal (VCC); The ground terminal of the dual-input NOR gate (100), the ground terminal of the first low-pass filter (200), the source of the N-type FDSOI transistor (M2), the other end of the first capacitor (C2) and the ground terminal of the hysteresis comparator (300) are all grounded (GND).

2. The frequency multiplier according to claim 1, characterized in that: The dual-input NOR gate (100) comprises: a second PMOS tube (P0), a third PMOS tube (P1), a first NMOS tube (M0) and a second NMOS tube (M1); Wherein, the source of the second PMOS tube (P0) is the power supply terminal of the dual-input NOR gate (100); The gate of the second PMOS tube (P0) is the first input terminal of the dual-input NOR gate (100); The drain of the second PMOS tube (P0) is connected to the source of the third PMOS tube (P1); The gate of the third PMOS tube (P1) is the second input terminal of the dual-input NOR gate (100); The drain of the third PMOS tube (P1) is connected to the drain of the first NMOS tube (M0) and the drain of the second NMOS tube (M1); The gate of the first NMOS tube (M0) is connected to the gate of the second PMOS tube (P0); The gate of the second NMOS tube (M1) is connected to the gate of the third PMOS tube (P1); The source of the first NMOS transistor (M0) is connected to the source of the second NMOS transistor (M1) and serves as the ground terminal of the dual-input NOR gate (100).

3. The frequency multiplier according to claim 1, characterized in that: The first low-pass filter (200) is an RC low-pass filter.

4. The frequency multiplier according to claim 1, characterized in that: The hysteresis comparator (300) comprises: a fourth PMOS tube (P3), a fifth PMOS tube (P4), a sixth PMOS tube (P5), a third NMOS tube (M3), a fourth NMOS tube (M4) and a fifth NMOS tube (M5); The source of the fourth PMOS tube (P3) and the drain of the fifth NMOS tube (M5) are connected to serve as the power supply terminal of the hysteresis comparator (300); The gate of the fourth PMOS tube (P3), the gate of the fifth PMOS tube (P4), the gate of the third NMOS tube (M3) and the gate of the fourth NMOS tube (M4) are connected to serve as the input end of the hysteresis comparator (300); The drain of the fourth PMOS tube (P3) is connected to the source of the fifth PMOS tube (P4) and the source of the sixth PMOS tube (P5); The drain of the fifth PMOS tube (P4) is connected to the drain of the third NMOS tube (M3), the gate of the sixth PMOS tube (P5) and the gate of the fifth NMOS tube (M5), serving as the output end of the hysteresis comparator (300); The source of the third NMOS tube (M3) is connected to the drain of the fourth NMOS tube (M4) and the source of the fifth NMOS tube (M5); The source of the fourth NMOS transistor (M4) and the drain of the sixth PMOS transistor (P5) are connected to serve as the ground terminal of the hysteresis comparator (300).

5. The frequency multiplier according to claim 1, characterized in that: The N-type FDSOI transistor (M2) is a tube with a flip well structure using the FDSOI process.

6. The frequency multiplier according to claim 5, characterized in that: The back gate voltage of the tube with the flip well structure is adjusted in the range of 0~2V; when the comparator (COMP1) outputs a low level, the back gate voltage of the tube with the flip well structure is reduced to 0V; when the comparator (COMP1) outputs a high level, the back gate voltage of the tube with the flip well structure is increased to 2V.

7. The frequency multiplier according to any one of claims 1 to 6, characterized in that: The frequency multiplier further comprises: a second low-pass filter (400); Wherein, an input terminal of the second low-pass filter (400) is connected to an output terminal of the comparator (COMP1); The output terminal of the second low-pass filter (400) is connected to the back gate of the N-type FDSOI transistor (M2); A ground terminal of the second low-pass filter (400) is grounded.

8. The frequency multiplier according to claim 7, characterized in that: The second low-pass filter (400) is an RC low-pass filter.

9. The frequency multiplier according to any one of claims 1 to 6, characterized in that: The frequency multiplier further includes: a first inverter and a second inverter; The input end of the first inverter is connected to the output end of the first low-pass filter (200); the output end of the first inverter is connected to the input end of the second inverter; and the output end of the second inverter is connected to the second input end of the dual-input XOR gate (XOR0).

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