Equalization circuit and reception circuit including same

Abstract

The invention relates to an equalization circuit and a receiving circuit including the same. An equalization circuit includes a first equalization circuit and a second equalization circuit. When the swing width reduction signal is activated, the first equalization circuit adjusts a voltage level of the first signal line according to the second equalization control signal and adjusts a voltage level of the second signal line according to the first equalization control signal to reduce a swing width of the differentially amplified signal transmitted through the first signal line and the second signal line. When the swing width increasing signal is activated, the second equalization circuit adjusts the voltage level of the second signal line according to the second equalization control signal and adjusts the voltage level of the first signal line according to the first equalization control signal to increase the swing width of the differential amplification signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Application No. 10-2023-0091160 filed on July 13, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as if fully set forth. Technical Field

[0003] Various embodiments relate generally to semiconductor circuits, and more particularly to equalization circuits and receiving circuits including the same. Background Art

[0004] During signal transmission in a semiconductor device, the swing width of the signal changes depending on the environment of the channel, and the signal transmission efficiency may decrease accordingly. Therefore, a receiving circuit with an equalization function can be used to eliminate the decrease in signal transmission efficiency. However, the equalization function alone cannot adjust the swing width of the signal as desired, which limits the improvement of signal transmission efficiency. Summary of the invention

[0005] In one embodiment, an equalization circuit may include a first equalization circuit and a second equalization circuit. The first equalization circuit may be configured to: when a swing width reduction signal is activated, adjust the voltage level of the first signal line according to the second equalization control signal and adjust the voltage level of the second signal line according to the first equalization control signal to reduce the swing width of a differential amplified signal transmitted through the first signal line and the second signal line. The second equalization circuit may be configured to: when a swing width increase signal is activated, adjust the voltage level of the second signal line according to the second equalization control signal and adjust the voltage level of the first signal line according to the first equalization control signal to increase the swing width of the differential amplified signal.

[0006] In one embodiment, a receiving circuit of a semiconductor device may include a first amplifier circuit, an equalizer circuit, and a control circuit. The first amplifier circuit may be configured to amplify an input signal according to a reference voltage to generate a differential amplified signal, and transmit the differential amplified signal to a first signal line and a second signal line. The equalizer circuit may be coupled to the first signal line and the second signal line, and may be configured to reduce the swing width of the differential amplified signal in response to a swing width reduction signal, and increase the swing width of the differential amplified signal in response to a swing width increase signal. The control circuit may be configured to generate a swing width reduction signal and a swing width increase signal according to a swing width increase / decrease selection signal.

[0007] In one embodiment, a receiving circuit of a semiconductor device may include a first amplifier circuit, an equalizer circuit, a swing width adjustment circuit, and a control circuit. The first amplifier circuit may be configured to amplify an input signal according to a reference voltage to generate a differential amplified signal, and transmit the differential amplified signal to a first signal line and a second signal line. The equalizer circuit may be coupled to the first signal line and the second signal line, and configured to reduce the swing width of the differential amplified signal in response to a swing width reduction signal, and increase the swing width of the differential amplified signal in response to a swing width increase signal. The swing width adjustment circuit may be coupled between the equalizer circuit and ground, and configured to adjust the increase and decrease of the swing width of the differential amplified signal according to a swing width adjustment code. The control circuit may be configured to generate a swing width reduction signal and a swing width increase signal according to a swing width increase / decrease selection signal.

[0008] The embodiments of the present disclosure can improve signal transmission efficiency by adjusting the swing width of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram showing a configuration of a receiving circuit according to one embodiment of the present disclosure.

[0010] Figure 2 is a diagram showing an embodiment according to the present disclosure Figure 1 FIG. 1 is a diagram of a configuration of a first amplifier circuit.

[0011] Figure 3 is a diagram showing an embodiment according to the present disclosure Figure 1 Diagram of the configuration of the equalizer circuit.

[0012] Figure 4 is a diagram showing an embodiment according to the present disclosure Figure 1 Diagram of the configuration of the control circuit.

[0013] Figure 5 is a diagram illustrating an equalization operation of a receiving circuit according to an embodiment of the present disclosure.

[0014] Figure 6 is a diagram showing a configuration of a receiving circuit according to another embodiment of the present disclosure.

[0015] Figure 7 is a diagram showing an embodiment according to the present disclosure Figure 6 FIG. 1 is a diagram of the configuration of the swing width adjustment circuit.

[0016] Figure 8 is a diagram illustrating an equalization operation of a receiving circuit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Various embodiments of the present disclosure can improve signal transmission efficiency by adjusting the swing width of a signal. Figure 1 1 is a diagram showing a configuration of a receiving circuit 100 according to an embodiment. Figure 1 According to an embodiment, a receiving circuit 100 may include a first amplifying circuit 110 , a second amplifying circuit 120 , an equalizing control signal generating circuit 130 , a current sink circuit 140 , an equalizing circuit 200 , and a control circuit 300 .

[0018] The first amplification circuit 110 may amplify the input signal IN according to the reference voltage VREF to generate a first differential amplification signal OUTN / OUTP, and transmit the first differential amplification signal OUTN / OUTP to the first signal line 101 and the second signal line 102. The first amplification circuit 110 may transmit one of the first differential amplification signals OUTN / OUTP (e.g., the first amplification signal OUTN) to the first signal line 101, and transmit the second amplification signal OUTP to the second signal line 102.

[0019] The second amplifying circuit 120 may amplify the first differential amplified signal OUTN / OUTP to generate a preliminary output signal OUT_PRE. The second amplifying circuit 120 may have the same circuit configuration as the first amplifying circuit 110.

[0020] The preliminary output signal OUT_PRE may be input to the equalization control signal generation circuit 130, and the equalization control signal generation circuit 130 may output the first and second equalization control signals EQ and EQB and the output signal OUT. The equalization control signal generation circuit 130 may generate the output signal OUT and the first and second equalization control signals EQ and EQB according to the preliminary output signal OUT_PRE.

[0021] The equalization control signal generating circuit 130 may include a clipper SLC 131 and a plurality of logic gates 132-135. The clipper 131 may remove the noise component of the preliminary output signal OUT_PRE and may output a signal from which the noise has been removed. The first logic gate 132 may output by inverting the signal output from the clipper 131. The second logic gate 133 may invert the output of the first logic gate 132 and output it as a first equalization control signal EQ. The third logic gate 134 may invert the first equalization control signal EQ and output it as a second equalization control signal EQB. The fourth logic gate 135 may invert the output of the first logic gate 132 to generate an output signal OUT.

[0022] The input signal IN may be input sequentially, for example, data may be input at 1 unit interval (hereinafter referred to as UI). The preliminary output signal OUT_PRE is passed through the clipper 131, the first logic gate 132, and the second logic gate 133 to generate the first equalization control signal EQ and the second equalization control signal EQB. Each of the first equalization control signal EQ and the second equalization control signal EQB may have a signal processing delay time corresponding to the second amplification circuit 120, the clipper 131, the first logic gate 132, the second logic gate 133, and the third logic gate 134. The signal processing delay time may be less than 1 UI. The equalization circuit 200 may perform an equalization operation on the current input signal IN according to the first equalization control signal EQ and the second equalization control signal EQB.

[0023] The equalization circuit 200 is coupled to the first signal line 101 and the second signal line 102 , and may receive a swing width reduction signal EQEN_SGNDN, a swing width increase signal EQEN_SGNUP, a first equalization control signal EQ, and a second equalization control signal EQB.

[0024] When the swing width reduction signal EQEN_SGNDN is activated, the equalization circuit 200 can adjust the voltage level of the first signal line 101 according to the second equalization control signal EQB, and adjust the voltage level of the second signal line 102 according to the first equalization control signal EQ to reduce the swing width of the first differential amplification signal OUTN / OUTP transmitted through the first signal line 101 and the second signal line 102.

[0025] When the swing width increase signal EQEN_SGNUP is activated, the equalization circuit 200 can adjust the voltage level of the second signal line 102 according to the second equalization control signal EQB, and adjust the voltage level of the first signal line 101 according to the first equalization control signal EQ to increase the swing width of the first differential amplification signal OUTN / OUTP.

[0026] The current sink circuit 140 may be coupled to the equalizing circuit 200 through the first node ND1. The current sink circuit 140 may adjust the amount of sink current in the equalizing circuit 200 based on the bias voltage BIAS_DFE. The current sink circuit 140 may include a transistor.

[0027] The control circuit 300 may receive the swing width increase / decrease selection signal CTRL_SGN and the equalization enable signal EQEN as inputs, and output the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP. The control circuit 300 may selectively activate the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP by combining the swing width increase / decrease selection signal CTRL_SGN and the equalization enable signal EQEN.

[0028] Figure 2 It is shown Figure 1 FIG. 1 is a diagram showing a configuration of the first amplifier circuit 110. Figure 2 , the first amplifying circuit 110 may include a plurality of resistors 111 , 112 and a plurality of transistors 113 - 116 .

[0029] One end of the second resistor 112 may be coupled to a power supply. The voltage of the second resistor 112 may be output as a first amplified signal OUTN of the first differential amplified signal OUTN / OUTP. One end of the first resistor 111 may be coupled to a power supply. The first resistor 111 may be coupled to the power supply in parallel with the second resistor 112. The voltage of the first resistor 111 may be output as a second amplified signal OUTP of the first differential amplified signal OUTN / OUTP. The first transistor 113 may have a drain coupled to the other end of the first resistor 111, and may receive a reference voltage VREF input to its gate. The second transistor 114 may have a drain coupled to the other end of the second resistor 112, and may receive an input signal IN at its gate. The third transistor 115 may have a drain coupled to the source of the first transistor 113, a gate having a bias voltage BIAS_SW input, and a source coupled to ground. The fourth transistor 116 has a drain coupled to the source of the second transistor 114, a gate having a bias voltage BIAS_SW input, and a source coupled to ground. The bias voltage BIAS_SW can be supplied or blocked by external control.

[0030] The first amplification circuit 110 may generate the first differential amplification signal OUTN / OUTP by pulling down the first amplification signal OUTN when the level of the input signal IN is high relative to the reference voltage VREF, and pulling down the second amplification signal OUTP when the level of the input signal IN is low relative to the reference voltage VREF.

[0031] Figure 3 It is shown Figure 1 FIG. 2 is a diagram of a configuration of an equalizer circuit 200. Figure 3 The equalizing circuit 200 may include a first equalizing circuit 210 and a second equalizing circuit 220 .

[0032] When the swing width reduction signal EQEN_SGNDN is activated, the first equalization circuit 210 can adjust the voltage level of the first signal line 101 according to the second equalization control signal EQB, and adjust the voltage level of the second signal line 102 according to the first equalization control signal EQ to reduce the swing width of the first differential amplification signal OUTN / OUTP transmitted through the first signal line 101 and the second signal line 102.

[0033] The first equalization circuit 210 may include a plurality of switch elements 211-215. Each of the plurality of switch elements 211-215 may include a transistor. The first switch element (i.e., the first transistor 211) may have a drain coupled to the first signal line 101 and a gate having a swing width reduction signal EQEN_SGNDN input. The second switch element (i.e., the second transistor 212) has a drain coupled to the source of the first transistor 211 and may receive the second equalization control signal EQB at its gate. The third switch element (i.e., the third transistor 213) has a drain coupled to the second signal line 102, and the swing width reduction signal EQEN_SGNDN may be input to the gate of the third transistor 213. The fourth switch element (i.e., the fourth transistor 214) has a drain coupled to the source of the third transistor 213 and may receive the first equalization control signal EQ at its gate. The fifth switching element (ie, the fifth transistor 215 ) has a drain commonly coupled with the source of the second transistor 212 and the source of the fourth transistor 214 , a gate having the swing width reduction signal EQEN_SGNDN input, and a source coupled with the first node ND1 .

[0034] When the swing width increase signal EQEN_SGNUP is activated, the second equalization circuit 220 can adjust the voltage level of the second signal line 102 according to the second equalization control signal EQB, and adjust the voltage level of the first signal line 101 according to the first equalization control signal EQ to increase the swing width of the first differential amplification signal OUTN / OUTP.

[0035] The second equalization circuit 220 may include a plurality of switch elements 221-225. Each of the plurality of switch elements 221-225 may include a transistor. The first switch element (i.e., the first transistor 221) may have a drain coupled to the second signal line 102, and the swing width increase signal EQEN_SGNUP may be input to the gate of the first transistor 221. The second switch element (i.e., the second transistor 222) has a drain coupled to the source of the first transistor 221, and may receive the second equalization control signal EQB at its gate. The third switch element (i.e., the third transistor 223) has a drain coupled to the first signal line 101, and the swing width increase signal EQEN_SGNUP may be input to the gate of the third transistor 223. The fourth switch element (i.e., the fourth transistor 224) has a drain coupled to the source of the third transistor 223, and may receive the first equalization control signal EQ at its gate. The fifth switching element (ie, the fifth transistor 225 ) has a drain commonly coupled with the source of the second transistor 222 and the source of the fourth transistor 224 , a gate receiving the swing width increasing signal EQEN_SGNUP, and a source coupled with the first node ND1 .

[0036] Figure 4 It is shown Figure 1 FIG. 3 is a diagram of a configuration of a control circuit 300. Figure 4 , the control circuit 300 may include a plurality of logic gates 301 - 305 .

[0037] The first logic gate 301 may invert and output the swing width increase / decrease selection signal CTRL_SGN. The second logic gate 302 may output the output of the first logic gate 301 and the equalization enable signal EQEN through a NAND operation. The third logic gate 303 may invert the output of the second logic gate 302 and output it as a swing width reduction signal EQEN_SGNDN. The fourth logic gate 304 may output the swing width increase / decrease selection signal CTRL_SGN and the equalization enable signal EQEN through a NAND operation. The fifth logic gate 305 may invert the output of the fourth logic gate 304 and output it as a swing width increase signal EQEN_SGNUP.

[0038] When the equalization enable signal EQEN is deactivated to a low level, that is, when the equalization function is deactivated, the control circuit 300 may deactivate the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP to a low level regardless of the swing width increase / decrease selection signal CTRL_SGN.

[0039] When the equalization enable signal EQEN is enabled to a high level, that is, when the equalization function is enabled, the control circuit 300 can select whether to increase or decrease the swing width when performing the equalization function depending on the level of the swing width increase / decrease selection signal CTRL_SGN. For example, when the swing width increase / decrease selection signal CTRL_SGN is at a low level, the swing width reduction signal EQEN_SGNDN is output at a high level and the swing width increase signal EQEN_SGNUP is output at a low level, so that the equalization function of the swing width reduction method is selected. On the other hand, when the swing width increase / decrease selection signal CTRL_SGN is at a high level, the equalization function of the swing width increase method is selected by outputting the swing width reduction signal EQEN_SGNDN at a low level and the swing width increase signal EQEN_SGNUP at a high level.

[0040] Figure 5 FIG. 1 is a diagram showing an equalization operation of the receiving circuit 100 according to an embodiment. Figures 3 to 5 The equalization operation of the receiving circuit 100 according to one embodiment is described.

[0041] First, when the equalization function is disabled (i.e., EQ OFF), as Figure 5 As shown in (a) of FIG. 8 , the equalization enable signal EQEN is at a low level (ie, “L”), and thus the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP are output at a low level.

[0042] Because the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP are low levels, both the first equalization circuit 210 and the second equalization circuit 220 are disabled, so that the swing width of the first differential amplification signal OUTN / OUTP is maintained at the level output from the first amplification circuit 110, and the output signal OUT can be output accordingly.

[0043] When the swing width reduction method is selected, the equalization function (ie, SWING DOWN) is selected. Figure 5 As shown in (b), the equalization enable signal EQEN is at a high level and the swing width increase / decrease selection signal CTRL_SGN is at a low level, so the swing width reduction signal EQEN_SGNDN is output at a high level and the swing width increase signal EQEN_SGNUP is output at a low level.

[0044] Because the swing width reduction signal EQEN_SGNDN is a high level and the swing width increase signal EQEN_SGNUP is a low level, the first equalization circuit 210 is enabled and the second equalization circuit 220 is disabled.

[0045] The first equalization circuit 210 may reduce the voltage level of the second signal line 102 according to the first equalization control signal EQ to reduce the swing width of the first differential amplification signal OUTN / OUTP.

[0046] When the balancing function of the swing width increase method (i.e., SWING UP) is selected, as Figure 5 As shown in (c), the equalization enable signal EQEN is high level and the swing width increase / decrease selection signal CTRL_SGN is high level, so the swing width reduction signal EQEN_SGNDN is output as a low level and the swing width increase signal EQEN_SGNUP is output as a high level.

[0047] Because the swing width reduction signal EQEN_SGNDN is a low level and the swing width increase signal EQEN_SGNUP is a high level, the first equalization circuit 210 is disabled and the second equalization circuit 220 is enabled.

[0048] The second equalization circuit 220 may reduce the voltage level of the first signal line 101 according to the first equalization control signal EQ to increase the swing width of the first differential amplification signal OUTN / OUTP.

[0049] The amplitude of the increase and decrease of the swing width can be determined by the current sink circuit 140. On the other hand, the swing width reduction method and the swing width increase method can be selected through a series of training operations. That is, depending on the environment of the channel of transmission, the input signal IN can have different characteristics, such as signal integrity characteristics, which are the basis of signal quality. Therefore, the level of the swing width increase / decrease selection signal CTRL_SGN can be selected accordingly by selecting one of the swing width reduction method and the swing width increase method, so that in one embodiment, the quality of the output signal OUT is improved by the training operation. For example, when the swing width of the output signal OUT is larger than the target level, the swing width increase / decrease selection signal CTRL_SGN can be set to a low level, so that the equalization circuit 200 performs the equalization operation of the swing width reduction method. On the other hand, if the swing width of the output signal OUT is smaller than the target level, the swing width increase / decrease selection signal CTRL_SGN can be set to a high level, so that the equalization circuit 200 performs the equalization operation with the swing width increase method.

[0050] Figure 6 is a diagram showing a configuration of a receiving circuit 100A according to another embodiment. Figure 6According to another embodiment, a receiving circuit 100A may include a first amplifying circuit 110 , a second amplifying circuit 120 , an equalizing control signal generating circuit 130 , an equalizing circuit 200 , a control circuit 300 , and a swing width adjusting circuit 400 .

[0051] The first amplification circuit 110 may amplify the input signal IN according to the reference voltage VREF to generate a first differential amplification signal OUTN / OUTP, and transmit the first differential amplification signal OUTN / OUTP to the first signal line 101 and the second signal line 102. The first amplification circuit 110 may transmit one of the first differential amplification signals OUTN / OUTP (e.g., the first amplification signal OUTN) to the first signal line 101, and transmit the second amplification signal OUTP to the second signal line 102.

[0052] The second amplifying circuit 120 may amplify the first differential amplified signal OUTN / OUTP to generate a preliminary output signal OUT_PRE.

[0053] The equalization control signal generation circuit 130 may generate an output signal OUT and a first equalization control signal EQ and a second equalization control signal EQB according to the preliminary output signal OUT_PRE.

[0054] The equalization control signal generating circuit 130 may include a clipper SLC 131 and a plurality of logic gates 132-135. The clipper 131 may remove the noise component of the preliminary output signal OUT_PRE and may output a signal from which the noise has been removed. The first logic gate 132 may output by inverting the signal output from the clipper 131. The second logic gate 133 may invert the output of the first logic gate 132 and output it as a first equalization control signal EQ. The third logic gate 134 may invert the first equalization control signal EQ and output it as a second equalization control signal EQB. The fourth logic gate 135 may invert the output of the first logic gate 132 to generate an output signal OUT.

[0055] The input signal IN may be input sequentially, for example, data may be input at 1 unit interval (UI). The preliminary output signal OUT_PRE is passed through the clipper 131, the first logic gate 132, and the second logic gate 133 to generate the first equalization control signal EQ and the second equalization control signal EQB. Each of the first equalization control signal EQ and the second equalization control signal EQB may have a signal processing delay time corresponding to the second amplification circuit 120, the clipper 131, the first logic gate 132, the second logic gate 133, and the third logic gate 134. The signal processing delay time may be less than 1 UI. The equalization circuit 200 may perform an equalization operation on the current input signal IN according to the first equalization control signal EQ and the second equalization control signal EQB.

[0056] The equalization circuit 200 is coupled to the first signal line 101 and the second signal line 102 , and may receive a swing width reduction signal EQEN_SGNDN, a swing width increase signal EQEN_SGNUP, a first equalization control signal EQ, and a second equalization control signal EQB.

[0057] When the swing width reduction signal EQEN_SGNDN is activated, the equalization circuit 200 can adjust the voltage level of the first signal line 101 according to the second equalization control signal EQB, and adjust the voltage level of the second signal line 102 according to the first equalization control signal EQ to reduce the swing width of the first differential amplification signal OUTN / OUTP transmitted through the first signal line 101 and the second signal line 102.

[0058] When the swing width increase signal EQEN_SGNUP is activated, the equalization circuit 200 can adjust the voltage level of the second signal line 102 according to the second equalization control signal EQB, and adjust the voltage level of the first signal line 101 according to the first equalization control signal EQ to increase the swing width of the first differential amplification signal OUTN / OUTP.

[0059] The control circuit 300 may receive the swing width increase / decrease selection signal CTRL_SGN and the equalization enable signal EQEN as inputs, and output the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP. The control circuit 300 may selectively activate the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP by combining the swing width increase / decrease selection signal CTRL_SGN and the equalization enable signal EQEN.

[0060] The swing width adjustment circuit 400 is coupled between the equalization circuit 200 and ground, and can adjust the amount of increase and decrease of the swing width of the first differential amplification signal OUTN / OUTP according to the swing width adjustment code BIAS_DFE<0:N>.

[0061] Figure 7 It is shown Figure 6 FIG. 4 is a diagram showing a configuration of a swing width adjustment circuit 400. Figure 7 The swing width adjustment circuit 400 may be configured to have current driving capability in a binary weighted manner. The swing width adjustment circuit 400 may include a plurality of current sink circuits 400-0 to 400-N. In one embodiment, N may be a natural number greater than 1.

[0062] The plurality of current sink circuits 400-0 to 400-N may be coupled in parallel to be coupled with the equalization circuit 200 through the first node ND1. The plurality of current sink circuits 400-0 to 400-N may activate a current path in response to each signal bit of the swing width adjustment code BIAS_DFE<0:N>.

[0063] The swing width adjustment circuit 400 may change the amount of sink current in the equalization circuit 200 according to the value of the swing width adjustment code BIAS_DFE<0:N> so that the amount of increase and decrease of the swing width of the first differential amplification signal OUTN / OUTP is adjusted.

[0064] Figure 8 FIG. 1 is a diagram showing an equalization operation of a receiving circuit according to another embodiment. Figures 6 to 8 The equalization operation of the receiving circuit 100A according to another embodiment is described.

[0065] First, when the equalization function is disabled, such as Figure 8 As shown in (a) of FIG. 8 , the equalization enable signal EQEN is at a low level, and thus the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP are output at a low level.

[0066] Because the swing width reduction signal EQEN_SGNDN and the swing width increase signal EQEN_SGNUP are low levels, both the first equalization circuit 210 and the second equalization circuit 220 are disabled, so that the swing width of the first differential amplification signal OUTN / OUTP is maintained at the level output from the first amplification circuit 110, and the output signal OUT can be output accordingly.

[0067] When the equalization function of the swing width reduction method is selected, such as Figure 8As shown in (b), the equalization enable signal EQEN is at a high level and the swing width increase / decrease selection signal CTRL_SGN is at a low level, so the swing width reduction signal EQEN_SGNDN is output at a high level and the swing width increase signal EQEN_SGNUP is output at a low level.

[0068] Because the swing width reduction signal EQEN_SGNDN is a high level and the swing width increase signal EQEN_SGNUP is a low level, the first equalization circuit 210 is enabled and the second equalization circuit 220 is disabled.

[0069] The first equalization circuit 210 may reduce the voltage level of the second signal line 102 according to the first equalization control signal EQ to reduce the swing width of the first differential amplification signal OUTN / OUTP.

[0070] The swing width adjustment circuit 400 may adjust the amount of reduction of the swing width of the first differential amplification signal OUTN / OUTP by changing the amount of sink current of the equalization circuit 200 according to the value of the swing width adjustment code BIAS_DFE<0:N>.

[0071] When the equalization function of the swing width enlargement method is selected, such as Figure 8 As shown in (c), the equalization enable signal EQEN is high level and the swing width increase / decrease selection signal CTRL_SGN is high level, so the swing width reduction signal EQEN_SGNDN is output as a low level and the swing width increase signal EQEN_SGNUP is output as a high level.

[0072] Because the swing width reduction signal EQEN_SGNDN is a low level and the swing width increase signal EQEN_SGNUP is a high level, the first equalization circuit 210 is disabled and the second equalization circuit 220 is enabled.

[0073] The second equalization circuit 220 may reduce the voltage level of the first signal line 101 according to the first equalization control signal EQ to increase the swing width of the first differential amplification signal OUTN / OUTP.

[0074] The swing width adjustment circuit 400 may adjust the amount of increase of the swing width of the first differential amplification signal OUTN / OUTP by changing the amount of the sink current of the equalization circuit 200 according to the value of the swing width adjustment code BIAS_DFE<0:N>.

[0075] On the other hand, the swing width reduction method and the swing width increase method can be selected through a series of training operations. That is, depending on the environment of the transmission channel, the input signal IN may have different characteristics, such as signal integrity characteristics, which are the basis of signal quality. Therefore, the level of the swing width increase / decrease selection signal CTRL_SGN and the value of the swing width adjustment code BIAS_DFE<0:N> can be selected accordingly by selecting one of the swing width reduction method and the swing width increase method, so that in one embodiment, the quality of the output signal OUT is improved by the training operation. For example, if the swing width of the output signal OUT is larger than the target level, the swing width increase / decrease selection signal CTRL_SGN can be set to a low level, so that the equalization circuit 200 selects the equalization operation of the swing width reduction method and adjusts the value of the swing width adjustment code BIAS_DFE<0:N> so that the swing width of the output signal OUT is close to the target level. On the other hand, if the swing width of the output signal OUT is less than the target level, the swing width increase / decrease selection signal CTRL_SGN can be set to a high level, so that the equalization circuit 200 selects the equalization operation of the swing width increase method and adjusts the value of the swing width adjustment code BIAS_DFE<0:N> so that the swing width of the output signal OUT is close to the target level.

[0076] Although certain embodiments have been described above, it will be appreciated by those skilled in the art that the described embodiments are by way of example only. Therefore, the equalization circuit and the receiving circuit including the same should not be limited based on the described embodiments. Instead, the equalization circuit and the receiving circuit including the same described herein should be limited only in accordance with the appended claims when read in conjunction with the above description and the accompanying drawings.

Claims

1. An equalization circuit, comprising: a first equalization circuit configured to, when a swing width reduction signal is activated, adjust a voltage level of the first signal line according to a second equalization control signal and adjust a voltage level of the second signal line according to the first equalization control signal to reduce a swing width of a differential amplification signal transmitted through the first signal line and the second signal line, and The second equalization circuit is configured to: when the swing width increase signal is activated, adjust the voltage level of the second signal line according to the second equalization control signal and adjust the voltage level of the first signal line according to the first equalization control signal to increase the swing width of the differential amplification signal.

2. The equalizing circuit according to claim 1, wherein the first equalizing circuit comprises: a first switching element coupled to the first signal line and operating according to the swing width reduction signal, a second switching element coupled to the first switching element and operating according to the second equalization control signal, a third switching element coupled to the second signal line and operated according to the swing width reduction signal, and a fourth switching element coupled to the third switching element and operated according to the first equalization control signal.

3. The equalizing circuit according to claim 1, wherein the second equalizing circuit comprises: a first switching element coupled to the second signal line and operated according to the swing width increasing signal, a second switching element coupled to the first switching element and operating according to the second equalization control signal, a third switching element coupled to the first signal line and operated according to the swing width increasing signal, and A fourth switching element is coupled to the third switching element and operates according to the first equalization control signal.

4. The equalization circuit according to claim 1, further comprising a control circuit configured to selectively activate the swing width reduction signal and the swing width increase signal using a combination of an equalization enable signal and a swing width increase / decrease selection signal.

5. A receiving circuit of a semiconductor device, comprising: a first amplifying circuit configured to amplify an input signal according to a reference voltage to generate a differential amplified signal, and transmit the differential amplified signal to a first signal line and a second signal line; an equalization circuit coupled to the first signal line and the second signal line and configured to reduce the swing width of the differential amplified signal in response to a swing width reduction signal and to increase the swing width of the differential amplified signal in response to a swing width increase signal; as well as A control circuit is configured to generate the swing width reduction signal and the swing width increase signal according to a swing width increase / decrease selection signal.

6. The receiving circuit according to claim 5, wherein the equalization circuit comprises: a first equalization circuit configured to, when the swing width reduction signal is activated, adjust a voltage level of the first signal line according to a second equalization control signal and adjust a voltage level of the second signal line according to the first equalization control signal to reduce the swing width of the differential amplification signal transmitted through the first signal line and the second signal line, and A second equalization circuit is configured to: when the swing width increase signal is activated, adjust the voltage level of the second signal line according to the second equalization control signal and adjust the voltage level of the first signal line according to the first equalization control signal to increase the swing width of the differential amplification signal.

7. The receiving circuit according to claim 6, wherein the first equalization circuit comprises: a first switching element coupled to the first signal line and operating according to the swing width reduction signal, a second switching element coupled to the first switching element and operating according to the second equalization control signal, a third switching element coupled to the second signal line and operated according to the swing width reduction signal, and A fourth switching element is coupled to the third switching element and operates according to the first equalization control signal.

8. The receiving circuit according to claim 6, wherein the second equalization circuit comprises: a first switching element coupled to the second signal line and operated according to the swing width increasing signal, a second switching element coupled to the first switching element and operating according to the second equalization control signal, a third switching element coupled to the first signal line and operated according to the swing width increasing signal, and A fourth switching element is coupled to the third switching element and operates according to the first equalization control signal. 9 . The receiving circuit according to claim 5 , wherein the control circuit is configured to selectively activate the swing width reduction signal and the swing width increase signal using a combination of an equalization enable signal and the swing width increase / decrease selection signal.

10. The receiving circuit according to claim 6, further comprising: a second amplifying circuit configured to amplify the differential amplified signal to generate a preliminary output signal; as well as The equalization control signal generating circuit is configured to generate the first equalization control signal and the second equalization control signal according to the preliminary output signal.

11. A receiving circuit of a semiconductor device, comprising: a first amplifying circuit configured to amplify an input signal according to a reference voltage to generate a differential amplified signal, and transmit the differential amplified signal to a first signal line and a second signal line; an equalization circuit coupled to the first signal line and the second signal line and configured to reduce the swing width of the differential amplified signal in response to a swing width reduction signal and to increase the swing width of the differential amplified signal in response to a swing width increase signal; a swing width adjustment circuit coupled between the equalization circuit and ground and configured to adjust an increase amount and a decrease amount of the swing width of the differential amplified signal according to a swing width adjustment code; as well as A control circuit is configured to generate the swing width reduction signal and the swing width increase signal according to a swing width increase / decrease selection signal.

12. The receiving circuit according to claim 11, wherein the equalization circuit comprises: a first equalization circuit configured to, when the swing width reduction signal is activated, adjust a voltage level of the first signal line according to a second equalization control signal and adjust a voltage level of the second signal line according to the first equalization control signal to reduce the swing width of the differential amplification signal transmitted through the first signal line and the second signal line, and A second equalization circuit is configured to: when the swing width increase signal is activated, adjust the voltage level of the second signal line according to the second equalization control signal and adjust the voltage level of the first signal line according to the first equalization control signal to increase the swing width of the differential amplification signal.

13. The receiving circuit according to claim 12, wherein the first equalization circuit comprises: a first switching element coupled to the first signal line and operating according to the swing width reduction signal, a second switching element coupled to the first switching element and operating according to the second equalization control signal, a third switching element coupled to the second signal line and operated according to the swing width reduction signal, and A fourth switching element is coupled to the third switching element and operates according to the first equalization control signal.

14. The receiving circuit according to claim 12, wherein the second equalization circuit comprises: a first switching element coupled to the second signal line and operated according to the swing width increasing signal, a second switching element coupled to the first switching element and operating according to the second equalization control signal, a third switching element coupled to the first signal line and operated according to the swing width increasing signal, and A fourth switching element is coupled to the third switching element and operates according to the first equalization control signal. 15 . The receiving circuit according to claim 11 , wherein the swing width adjustment circuit comprises a plurality of current sink circuits which are coupled in parallel to be coupled with the equalization circuit and operate in response to each signal bit of the swing width adjustment code. 16 . The receiving circuit according to claim 11 , wherein the control circuit is configured to selectively activate the swing width reduction signal and the swing width increase signal using a combination of an equalization enable signal and the swing width increase / decrease selection signal.

17. The receiving circuit according to claim 12, further comprising: a second amplifying circuit configured to amplify the differential amplified signal to generate a preliminary output signal; as well as The equalization control signal generating circuit is configured to generate the first equalization control signal and the second equalization control signal according to the preliminary output signal.

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